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产品型号OPA2180IDR的概述

OPA2180IDR 概述 OPA2180IDR 是一款由德州仪器（Texas Instruments）公司推出的高精度运算放大器。OP放大器在现代电子应用中扮演着至关重要的角色，从信号放大、滤波到数据采集和转换，应用广泛。OPA2180IDR 设计适用于需要低噪声、高精度和宽带宽的多种应用场合，包括工业自动化、医疗设备和传感器接口等。该芯片采用精密的 CMOS 技术制造，具备出色的电源电压范围和低功耗性能。OPA2180IDR 提供高增益、精准的直流特性和快速的转换响应，使其能够有力支持高分辨率信号的处理。详细参数 OPA2180IDR 主要参数如下： 1. 电源电压范围: - 单电源：2.7 V 至 36 V - 双电源：±1.35 V 至 ±18 V 2. 输入偏置电流: - 典型值为 10 pA，极低的输入偏置电流使其特别适合高阻抗源信号的处理。 3. ...

产品型号OPA2180IDR的Datasheet PDF文件预览

OPA2180

OPA4180

www.ti.com

SBOS584B –NOVEMBER 2011–REVISED DECEMBER 2011

0.1-μV/°C Drift, Low-Noise, Rail-to-Rail Output, 36-V, Zero-Drift

OPERATIONAL AMPLIFIERS

Check for Samples: OPA2180, OPA4180

FEATURES

APPLICATIONS

•

Low Offset Voltage: 75 μV (max)

Zero-Drift: 0.1 μV/°C

•

Bridge Amplifiers

Strain Gauges

Low Noise: 10 nV/√Hz

Very Low 1/f Noise

Test Equipment

Transducer Applications

Temperature Measurement

Electronic Scales

Excellent DC Precision:

–

PSRR: 126 dB

CMRR: 114 dB

Medical Instrumentation

Resister Thermal Detectors

Precision Active Filters

Open-Loop Gain (A_OL): 120 dB

•

Quiescent Current: 525 μA (max)

Wide Supply Range: ±2 V to ±18 V

DESCRIPTION

Rail-to-Rail Output:

The OPA2180 and OPA4180 operational amplifiers

use zero-drift techniques to simultaneously provide

low offset voltage (75 μV), and near zero-drift over

Input Includes Negative Rail

•

Low Bias Current: 250 pA (typ)

RFI Filtered Inputs

time

and

temperature.

These

miniature,

high-precision, low quiescent current amplifiers offer

high input impedance and rail-to-rail output swing

within 18 mV of the rails. The input common-mode

range includes the negative rail. Either single or dual

supplies can be used in the range of +4.0 V to +36 V

(±2 V to ±18 V).

MicroSIZE Packages

The dual version is offered in MSOP-8 and SO-8

packages. The quad is offered in SO-14 and

TSSOP-14 packages. All versions are specified for

operation from –40°C to +105°C.

Peak-to-Peak Noise = 250 nV

Time (1 s/div)

Zero-Drift Amplifier Portfolio

OFFSET VOLTAGE

OFFSET VOLTAGE DRIFT

BANDWIDTH

(MHz)

VERSION

PRODUCT

OPA188 (4 V to 36 V)

OPA333 (5 V)

(µV)

(µV/°C)

Single⁽¹⁾

0.085

0.05

0.25

0.05

0.085

0.35

0.05

0.25

0.05

0.085

0.35

0.25

0.35

0.9

1.6

Single

Dual

OPA378 (5 V)

OPA735 (12 V)

OPA2188 (4 V to 36 V)

OPA2180 (4 V to 36 V)

OPA2333 (5 V)

0.35

0.9

1.6

OPA2378 (5 V)

OPA2735 (12 V)

OPA4188 (4 V to 36 V)

OPA4180 (4 V to 36 V)

OPA4330 (5 V)

Quad⁽¹⁾

Quad

0.35

(1) Shaded rows denote future product releases.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

UNLESS OTHERWISE NOTED this document contains

PRODUCTION DATA information current as of publication date.

Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

OPA2180

OPA4180

SBOS584B –NOVEMBER 2011–REVISED DECEMBER 2011

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE INFORMATION⁽¹⁾

SPECIFIED

PACKAGE-

LEAD

PACKAGE

DESIGNATOR

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT MEDIA,

QUANTITY

PRODUCT

DUAL

OPA2180ID

OPA2180IDR

Rails, 100

OPA2180

SO-8

–40°C to +105°C

2180

TBD

Tape and Reel, 2500

Tape and Reel, 250

Tape and Reel, 2500

OPA2180IDGKT

OPA2180IDGKR

OPA2180⁽²⁾

MSOP-8

DGK

QUAD

OPA4180ID

OPA4180IDR

OPA4180IPW

OPA4180IPWR

Rails, 90

SO-14

–40°C to +105°C

OPA4180

Tape and Reel, 2000

Rails, 90

OPA4180⁽²⁾

TSSOP-14

Tape and Reel, 2000

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

(2) Shaded rows denote future product releases.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

OPA2180, OPA4180

±20, 40 (single supply)

(V–) – 0.5 to (V+) + 0.5

±10

UNIT

Supply voltage

Voltage

Current

Signal input terminals

Output short-circuit⁽²⁾

Operating temperature

Storage temperature

Junction temperature

Continuous

–55 to +125

°C

–65 to +150

+150

1.5

Human body model (HBM)

ESD ratings

Charged device model (CDM)

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond

those specified is not implied.

(2) Short-circuit to ground, one amplifier per package.

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OPA2180

OPA4180

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SBOS584B –NOVEMBER 2011–REVISED DECEMBER 2011

ELECTRICAL CHARACTERISTICS: V_S= ±2 V to ±18 V (V_S= +4 V to +36 V)

At T_A= +25°C, R_L= 10 kΩ connected to V_S/2, and V_COM= V_OUT= V_S/2, unless otherwise noted.

OPA2180, OPA4180

PARAMETER

OFFSET VOLTAGE

CONDITIONS

MIN

TYP

MAX

UNIT

V_OS

Input offset voltage

0.1

0.35

0.5

μV

dV_OS/dT

Input offset voltage drift

T_A= –40°C to +105°C

μV/°C

μV/V

V_S= 4 V to 36 V, V_CM= V_S/2

PSRR

Power-supply rejection ratio

T_A= –40°C to +105°C,

V_S= 4 V to 36 V, V_CM= V_S/2

0.5

μV/V

See

note⁽¹⁾

Long-term stability

μV

Channel separation, dc

μV/V

INPUT BIAS CURRENT

V_CM= V_S/2

±0.25

±0.5

±1

±5

I_B

Input bias current

T_A= –40°C to +105°C

±2

I_OS

Input offset current

T_A= –40°C to +105°C

±2.5

NOISE

Input voltage noise

f = 0.1 Hz to 10 Hz

f = 1 kHz

0.25

μV_PP

nV/Hz

fA/Hz

e_n

i_n

Input voltage noise density

Input current noise density

f = 1 kHz

INPUT VOLTAGE RANGE

V_CM

Common-mode voltage range

V–

(V+) – 1.5

(V–) < V_CM< (V+) – 1.5 V

104

114

104

CMRR

Common-mode rejection ratio

T_A= –40°C to +105°C,

(V–) + 0.5 V < V_CM< (V+) – 1.5 V

100

INPUT IMPEDANCE

Differential

Common-mode

OPEN-LOOP GAIN

100/6

6/9.5

MΩ/pF

10¹²Ω/pF

(V–) + 500 mV < V_O< (V+) – 500 mV, R_L= 10 kΩ

110

104

120

114

A_OL

Open-loop voltage gain

T_A= –40°C to +105°C,

(V–) + 500 mV < V_O< (V+) – 500 mV, R_L= 10 kΩ

FREQUENCY RESPONSE

GBW

Gain-bandwidth product

0.8

MHz

V/μs

μs

Slew rate

G = +1

0.1%

V_S= ±18 V, G = 1, 10-V step

Settling time

0.01%

μs

Overload recovery time

V_IN× G = V_S

μs

THD+N

Total harmonic distortion + noise

f = 1 kHz, G = 1, V_OUT= 1 V_RMS

0.0001

(1) 1000-hour life test at +125°C demonstrated randomly distributed variation in the range of measurement limits, or approximately 4 μV.

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Product Folder Link(s): OPA2180 OPA4180

OPA2180

OPA4180

SBOS584B –NOVEMBER 2011–REVISED DECEMBER 2011

www.ti.com

ELECTRICAL CHARACTERISTICS: V_S= ±2 V to ±18 V (V_S= +4 V to +36 V) (continued)

At T_A= +25°C, R_L= 10 kΩ connected to V_S/2, and V_COM= V_OUT= V_S/2, unless otherwise noted.

OPA2180, OPA4180

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT

No load

250

325

±18

120

300

360

Voltage output swing from rail

R_L= 10 kΩ

T_A= –40°C to +105°C, R_L= 10 kΩ

I_SC

Short-circuit current

R_O

Open-loop output resistance

Capacitive load drive

f = 2 MHz, I_O= 0 mA

C_LOAD

POWER SUPPLY

V_S

Operating voltage range

±2 (or 4)

±18 (or 36)

525

450

μA

I_Q

Quiescent current (per amplifier)

T_A= –40°C to +105°C, I_O= 0 mA

600

TEMPERATURE

Specified range

–40

–65

+105

+125

+150

°C

Operating range

Storage range

THERMAL INFORMATION: OPA2180

OPA2180

THERMAL METRIC⁽¹⁾

D (SO)

8 PINS

111.0

54.9

DGK (MSOP)

8 PINS

159.3

37.4

UNITS

θ_JA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

θ_JCtop

θ_JB

51.7

48.5

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

9.3

1.2

ψ_JB

51.1

77.1

θ_JCbot

n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

THERMAL INFORMATION: OPA4180

OPA4180

THERMAL METRIC⁽¹⁾

D (SO)

14 PINS

TBD

PW (TSSOP)

14 PINS

TBD

UNITS

θ_JA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

θ_JCtop

θ_JB

TBD

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

TBD

ψ_JB

TBD

θ_JCbot

TBD

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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Product Folder Link(s): OPA2180 OPA4180

OPA2180

OPA4180

www.ti.com

SBOS584B –NOVEMBER 2011–REVISED DECEMBER 2011

PIN CONFIGURATIONS

OPA2180

D, DGK PACKAGES (SO-8, MSOP-8)

(TOP VIEW)

OPA4180

D, PW PACKAGES (SO-14, TSSOP-14)

(TOP VIEW)

OUT A

-IN A

+IN A

V-

V+

OUT D

-IN D

+IN D

V-

OUT A

OUT B

-IN B

+IN B

-IN A

+IN A

V+

+IN C

-IN C

OUT C

+IN B

-IN B

OUT B

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OPA2180

OPA4180

SBOS584B –NOVEMBER 2011–REVISED DECEMBER 2011

www.ti.com

TYPICAL CHARACTERISTICS

Table 1. Characteristic Performance Measurements

DESCRIPTION

FIGURE

Figure 1

I_Band I_OSvs Common-Mode Voltage

Input Bias Current vs Temperature

Figure 2

Output Voltage Swing vs Output Current (Maximum Supply)

CMRR vs Temperature

Figure 3

Figure 4

0.1-Hz to 10-Hz Noise

Figure 5

Input Voltage Noise Spectral Density vs Frequency

Open-Loop Gain and Phase vs Frequency

Open-Loop Gain vs Temperature

Figure 6

Figure 7

Figure 8

Open-Loop Output Impedance vs Frequency

Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)

No Phase Reversal

Figure 9

Figure 10, Figure 11

Figure 12

Positive Overload Recovery

Figure 13

Negative Overload Recovery

Figure 14

Small-Signal Step Response (100 mV)

Large-Signal Step Response

Figure 15, Figure 16

Figure 17, Figure 18

Figure 19

Large-Signal Settling Time (10-V Positive Step)

Large-Signal Settling Time (10-V Negative Step)

Short-Circuit Current vs Temperature

Maximum Output Voltage vs Frequency

Channel Separation vs Frequency

Figure 20

Figure 21

Figure 22

Figure 23

EMIRR IN+ vs Frequency

Figure 24

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OPA4180

www.ti.com

SBOS584B –NOVEMBER 2011–REVISED DECEMBER 2011

TYPICAL CHARACTERISTICS

V_S= ±18 V, V_CM= V_S/2, R_LOAD= 10 kΩ connected to V_S/2, and C_L= 100 pF, unless otherwise noted.

I_BAND I_OSvs COMMON-MODE VOLTAGE

INPUT BIAS CURRENT vs TEMPERATURE

500

400

300

200

100

4000

3000

2000

1000

I_B+

I_B-

I_OS

+I_B

-I_B

I_OS

-100

-200

-300

-1000

-2000

-20

-15

-10

-5

-55 -35 -15

105 125

V_CM(V)

Temperature (°C)

Figure 1.

Figure 2.

OUTPUT VOLTAGE SWING vs OUTPUT CURRENT

(Maximum Supply)

CMRR vs TEMPERATURE

(V-) < V_CM< (V+) - 1.5 V

-40°C

+85°C

+125°C

(V-) + 0.5 V < V_CM< (V+) - 1.5 V

V_SUPPLY= ±2 V

-14

-15

-16

-17

-18

-19

-20

10 12 14 16 18 20 22 24

-55 -35 -15

105 125

Output Current (mA)

Temperature (°C)

Figure 3.

Figure 4.

INPUT VOLTAGE NOISE SPECTRAL DENSITY vs

FREQUENCY

0.1-Hz TO 10-Hz NOISE

100

Peak-to-Peak Noise = 250 nV

Time (1 s/div)

0.1

100

10k

100k

Frequency (Hz)

Figure 5.

Figure 6.

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OPA4180

SBOS584B –NOVEMBER 2011–REVISED DECEMBER 2011

www.ti.com

TYPICAL CHARACTERISTICS (continued)

V_S= ±18 V, V_CM= V_S/2, R_LOAD= 10 kΩ connected to V_S/2, and C_L= 100 pF, unless otherwise noted.

OPEN-LOOP GAIN AND PHASE vs FREQUENCY

OPEN-LOOP GAIN vs TEMPERATURE

140

120

100

180

2.5

V_SUPPLY= 4 V, R_L= 10 kW

V_SUPPLY= 36 V, R_L= 10 kW

Gain

Phase

135

1.5

0.5

−20

100

10k

100k

10M

100M

Frequency (Hz)

G007

-55 -35 -15

105 125

Temperature (°C)

Figure 7.

Figure 8.

SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD

(100-mV Output Step)

OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY

10k

R_L= 10 kW

R_OUT= 0 W

100

R_OUT= 25 W

R_OUT= 50 W

G = +1

+18

R_OUT

Device

R_L

C_L

-18

100

10k

100k

10M

100 200 300 400 500 600 700 800 900 1000

Capacitive Load (pF)

Frequency (Hz)

Figure 9.

Figure 10.

SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD

(100-mV Output Step)

NO PHASE REVERSAL

+18 V

R_OUT= 0 W

R_OUT= 25 W

R_OUT= 50 W

Device

-18 V

37 V_PP

Sine Wave

(±18.5 V)

R_F= 10 kW

R_I= 10 kW

G = -1

+18 V

R_OUT

V_IN

Device

C_L

V_OUT

R_L= 10 kW

-18 V

Time (100 ms/div)

100 200 300 400 500 600 700 800 900 1000

Capacitive Load (pF)

Figure 11.

Figure 12.

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SBOS584B –NOVEMBER 2011–REVISED DECEMBER 2011

TYPICAL CHARACTERISTICS (continued)

V_S= ±18 V, V_CM= V_S/2, R_LOAD= 10 kΩ connected to V_S/2, and C_L= 100 pF, unless otherwise noted.

POSITIVE OVERLOAD RECOVERY

NEGATIVE OVERLOAD RECOVERY

V_IN

V_OUT

20 kW

+18 V

2 kW

+18 V

2 kW

V_OUT

Device

V_OUT

V_IN

Device

V_IN

-18 V

G = -10

V_OUT

V_IN

Time (5 ms/div)

Figure 13.

Figure 14.

SMALL-SIGNAL STEP RESPONSE

(100 mV)

SMALL-SIGNAL STEP RESPONSE

(100 mV)

R_L= 10 kW

C_L= 10 pF

R_L= 10 kW

C_L= 10 pF

R_I= 2 kW R_F= 2 kW

G = +1

+18 V

Device

-18 V

+18 V

Device

R_L

C_L

-18 V

G = -1

Time (20 ms/div)

Time (1 ms/div)

Figure 15.

Figure 16.

LARGE-SIGNAL STEP RESPONSE

G = +1

R_L= 10 kW

G = -1

R_L= 10 kW

C_L= 10 pF

Time (50 ms/div)

Figure 17.

Figure 18.

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SBOS584B –NOVEMBER 2011–REVISED DECEMBER 2011

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TYPICAL CHARACTERISTICS (continued)

V_S= ±18 V, V_CM= V_S/2, R_LOAD= 10 kΩ connected to V_S/2, and C_L= 100 pF, unless otherwise noted.

LARGE-SIGNAL SETTLING TIME

(10-V Positive Step)

LARGE-SIGNAL SETTLING TIME

(10-V Negative Step)

G = -1

12-Bit Settling

-2

-4

-6

-8

-10

-2

-4

-6

-8

-10

(±1/2 LSB = ±0.024%)

Time (ms)

Figure 19.

Figure 20.

SHORT-CIRCUIT CURRENT vs TEMPERATURE

MAXIMUM OUTPUT VOLTAGE vs FREQUENCY

12.5

V_S= ±15 V

Maximum output voltage without

slew-rate induced distortion.

I_SC, Source

I_SC, Sink

7.5

V_S= ±5 V

-10

-20

-30

2.5

V_S= ±2.25 V

-55 -35 -15

105 125

10k

100k

10M

Temperature (°C)

Frequency (Hz)

Figure 21.

Figure 22.

CHANNEL SEPARATION vs FREQUENCY

EMIRR IN+ vs FREQUENCY

-60

-70

160

140

120

100

Channel A to B

Channel B to A

-80

-90

-100

-110

-120

-130

-140

-150

100

10k 100k

10M 100M

10M

100M

Frequency (Hz)

10G

Frequency (Hz)

Figure 23.

Figure 24.

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SBOS584B –NOVEMBER 2011–REVISED DECEMBER 2011

APPLICATION INFORMATION

The OPAx180 family of operational amplifiers combine precision offset and drift with excellent overall

performance, making them ideal for many precision applications. The precision offset drift of only 0.085 µV/°C

provides stability over the entire temperature range. In addition, the device offers excellent overall performance

with high CMRR, PSRR, and A_OL. As with all amplifiers, applications with noisy or high-impedance power

supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.

OPERATING CHARACTERISTICS

The OPAx180 family of amplifiers is specified for operation from 4 V to 36 V (±2 V to ±18 V). Many of the

specifications apply from –40°C to +105°C. Parameters that can exhibit significant variance with regard to

operating voltage or temperature are presented in the Typical Characteristics.

EMI REJECTION

The OPAx180 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI

interference from sources such as wireless communications and densely populated boards with a mix of analog

signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx180

benefits from these design improvements. Texas Instruments has developed the ability to accurately measure

and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to

6 GHz. Figure 25 shows the results of this testing on the OPAx180. Detailed information can also be found in the

Application Report EMI Rejection Ratio of Operational Amplifiers (SBOA128), available for download from the TI

website.

160

140

120

100

10M

100M

Frequency (Hz)

10G

Figure 25. OPAx180 EMIRR Testing

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GENERAL LAYOUT GUIDELINES

For best operational performance of the device, good printed circuit board (PCB) layout practices are

recommended. Low-loss, 0.1-µF bypass capacitors should be connected between each supply pin and ground,

placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable to

single-supply applications.

PHASE-REVERSAL PROTECTION

The OPAx180 family has an internal phase-reversal protection. Many op amps exhibit a phase reversal when the

input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting

circuits when the input is driven beyond the specified common-mode voltage range, causing the output to

reverse into the opposite rail. The input of the OPAx180 prevents phase reversal with excessive common-mode

voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 26.

+18 V

Device

-18 V

37 V_PP

Sine Wave

(±18.5 V)

V_IN

V_OUT

Time (100 ms/div)

Figure 26. No Phase Reversal

CAPACITIVE LOAD AND STABILITY

The dynamic characteristics of the OPAx180 have been optimized for a range of common operating conditions.

The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier

and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the

output. The simplest way to achieve this isolation is to add a small resistor (for example, R_OUTequal to 50 Ω) in

series with the output. Figure 27 and Figure 28 illustrate graphs of small-signal overshoot versus capacitive load

for several values of R_OUT. Also, refer to the Applications Report, Feedback Plots Define Op Amp AC

Performance (SBOA015), available for download from the TI website, for details of analysis techniques and

application circuits.

R_L= 10 kW

R_OUT= 0 W

R_OUT= 25 W

R_OUT= 50 W

R_OUT= 0 W

R_OUT= 25 W

R_OUT= 50 W

G = +1

+18

R_F= 10 kW

R_I= 10 kW

G = -1

R_OUT

+18 V

Device

R_OUT

R_L

C_L

-18

Device

C_L

R_L= 10 kW

-18 V

100 200 300 400 500 600 700 800 900 1000

Capacitive Load (pF)

100 200 300 400 500 600 700 800 900 1000

Capacitive Load (pF)

Figure 27. Small-Signal Overshoot versus

Capacitive Load (100-mV Output Step)

Figure 28. Small-Signal Overshoot versus

Capacitive Load (100-mV Output Step)

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Product Folder Link(s): OPA2180 OPA4180

OPA2180

OPA4180

www.ti.com

SBOS584B –NOVEMBER 2011–REVISED DECEMBER 2011

ELECTRICAL OVERSTRESS

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.

These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output

pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown

characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.

Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from

accidental ESD events both before and during product assembly.

These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to

10 mA as stated in the Absolute Maximum Ratings. Figure 29 shows how a series input resistor may be added to

the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and

its value should be kept to a minimum in noise-sensitive applications.

V+

I_OVERLOAD

10 mA max

V_OUT

Device

V_IN

5 kW

Figure 29. Input Current Protection

An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration,

high-current pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to

provide a current path around the operational amplifier core to prevent it from being damaged. The energy

absorbed by the protection circuitry is then dissipated as heat.

When the operational amplifier connects into a circuit, the ESD protection components are intended to remain

inactive and not become involved in the application circuit operation. However, circumstances may arise where

an applied voltage exceeds the operating voltage range of a given pin. Should this condition occur, there is a risk

that some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow

occurs through ESD cells and rarely involves the absorption device.

If there is an uncertainty about the ability of the supply to absorb this current, external zener diodes may be

added to the supply pins. The zener voltage must be selected such that the diode does not turn on during normal

operation.

However, its zener voltage should be low enough so that the zener diode conducts if the supply pin begins to

rise above the safe operating supply voltage level.

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Product Folder Link(s): OPA2180 OPA4180

OPA2180

OPA4180

SBOS584B –NOVEMBER 2011–REVISED DECEMBER 2011

www.ti.com

APPLICATION EXAMPLES

The application examples of Figure 30 and Figure 31 highlight only a few of the circuits where the OPAx180

family of devices can be used.

15 V

V_OUTP

OPA2180

3.3 V

R₅

V_DIFF/2

-15 V

1 kW

Ref 1

Ref 2

R_G

500 W

R₇

INA159

V_OUT

1 kW

VCM

Sense

-15 V

-V_DIFF/2

V_OUTN

OPA2180

15 V

Figure 30. Discrete INA + Attenuation for ADC with 3.3-V Supply

+15 V

(5 V)

Out

REF5050

1 mF

R₂

49.1 kW

R₃

60.4 kW

R₁

4.99 kW

0°C = 0 V

V_OUT

OPA2180

200°C = 5 V

R₅

(1)

RTD

Pt100

105.8 kW

R₄

1 kW

(1) R₅provides positive-varying excitation to linearize output.

Figure 31. RTD Amplifier with Linearization

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Product Folder Link(s): OPA2180 OPA4180

OPA2180

OPA4180

www.ti.com

SBOS584B –NOVEMBER 2011–REVISED DECEMBER 2011

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (November 2011) to Revision B

Page

•

Changed footnote 1 of Electrical Characteristics table ......................................................................................................... 3

Updated Figure 7 .................................................................................................................................................................. 8

Submit Documentation Feedback

Product Folder Link(s): OPA2180 OPA4180

PACKAGE OPTION ADDENDUM

www.ti.com

28-Aug-2012

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

OPA2180ID

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

OPA2180IDGK

OPA2180IDGKR

OPA2180IDR

PREVIEW

ACTIVE

VSSOP

SOIC

DGK

TBD

Call TI

2500

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

OPA4180ID

OPA4180IDR

OPA4180IPW

OPA4180IPWR

PREVIEW

SOIC

2500

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TSSOP

Green (RoHS

& no Sb/Br)

Call TI

Level-2-260C-1 YEAR

2000

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

28-Aug-2012

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

OPA2180IDR

SOIC

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

OPA2180IDR

2500

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

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Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

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OPA2180IDR产品参数

型号:	OPA2180IDR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	SOIC
包装说明：	SOP, SOP8,.25
针数：	8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.33.00.01
Factory Lead Time：	12 weeks
风险等级：	1.13
放大器类型：	OPERATIONAL AMPLIFIER
架构：	VOLTAGE-FEEDBACK
最大平均偏置电流 (IIB)：	0.005 µA
25C 时的最大偏置电流 (IIB)：	0.001 µA
最小共模抑制比：	104 dB
标称共模抑制比：	114 dB
频率补偿：	YES
最大输入失调电流 (IIO)：	0.0025 µA
最大输入失调电压：	75 µV
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e4
长度：	4.9 mm
低-偏置：	YES
低-失调：	YES
微功率：	YES
湿度敏感等级：	2
负供电电压上限：	-20 V
功能数量：	2
端子数量：	8
最高工作温度：	105 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
包装方法：	TR
峰值回流温度（摄氏度）：	260
功率：	YES
电源：	+-2/+-18/4/36 V
可编程功率：	NO
认证状态：	Not Qualified
座面最大高度：	1.75 mm
标称压摆率：	0.8 V/us
子类别：	Operational Amplifier
最大压摆率：	1.05 mA
供电电压上限：	20 V
表面贴装：	YES
技术：	BIPOLAR
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
标称均一增益带宽：	2000 kHz
最小电压增益：	158000
宽带：	NO
宽度：	3.9 mm
Base Number Matches：	1

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