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  • OPA2650P图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • OPA2650P 现货库存
  • 数量5000 
  • 厂家TI 
  • 封装DIP8 
  • 批号24+ 
  • 全新原装现货,低价出售,欢迎询购!
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  • OPA2650U图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • OPA2650U 现货库存
  • 数量3168 
  • 厂家BB 
  • 封装SOP 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
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  • OPA2650U图
  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • OPA2650U 现货库存
  • 数量21688 
  • 厂家TI量大发货 
  • 封装SOP8 
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  • OPA2650P图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • OPA2650P 优势库存
  • 数量10000 
  • 厂家BB 
  • 封装DIP 
  • 批号24+ 
  • ★★专业IC现货,诚信经营,市场最优价★★
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  • OPA2650E/250图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • OPA2650E/250
  • 数量13050 
  • 厂家TI 
  • 封装MSOP 
  • 批号2023+ 
  • 绝对原装正品现货/优势渠道商、原盘原包原盒
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  • OPA2650E-250图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • OPA2650E-250
  • 数量72140 
  • 厂家BB 
  • 封装SSOP8 
  • 批号2023+ 
  • 绝对原装全新正品现货/优势渠道商、原盘原包原盒
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    QQ:515102657QQ:515102657 复制
  • 0755-83777708“进口原装正品专供” QQ:364510898QQ:515102657
  • OPA2650P图
  • 深圳市欧瑞芯科技有限公司

     该会员已使用本站11年以上
  • OPA2650P
  • 数量10000 
  • 厂家TI(德州仪器) 
  • 封装8-DIP(0.300,7.62mm) 
  • 批号23+/24+ 
  • 绝对原装正品,可开13%专票,欢迎采购!!!
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  • 18565729389 QQ:3354557638QQ:3354557638
  • OPA2650P图
  • 集好芯城

     该会员已使用本站13年以上
  • OPA2650P
  • 数量19518 
  • 厂家BB 
  • 封装DIP8 
  • 批号最新批次 
  • 原装原厂 现货现卖
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  • OPA2650U图
  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • OPA2650U
  • 数量7650 
  • 厂家N/A 
  • 封装SOP 
  • 批号22+ 
  • ★只做原装★正品现货★原盒原标★
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  • OPA2650P图
  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • OPA2650P
  • 数量187 
  • 厂家BB 
  • 封装PDIP-8 
  • 批号22+ 
  • ★只做原装★正品现货★原盒原标★
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  • OPA2650U图
  • 千层芯半导体(深圳)有限公司

     该会员已使用本站9年以上
  • OPA2650U
  • 数量12223 
  • 厂家TI 
  • 封装SOP 
  • 批号2018+ 
  • TI一级代理商全新原装现货
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  • OPA2650U图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • OPA2650U
  • 数量5000 
  • 厂家BB 
  • 封装SOP 
  • 批号25+ 
  • 全新原装,公司现货销售!
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  • OPA2650U图
  • 绿盛电子(香港)有限公司

     该会员已使用本站12年以上
  • OPA2650U
  • 数量26976 
  • 厂家TI 
  • 封装SOP8 
  • 批号2018+ 
  • ★★代理原装现货,特价热卖!★★
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  • OPA2650P图
  • 深圳市恒益昌科技有限公司

     该会员已使用本站6年以上
  • OPA2650P
  • 数量5680 
  • 厂家BB 
  • 封装PDIP-8 
  • 批号25+ 
  • 原装正品长期供货
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  • OPA2650P图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
  • OPA2650P
  • 数量26800 
  • 厂家BB/TI 
  • 封装DIP8 
  • 批号24+ 
  • 假一罚十,原装进口正品现货供应,价格优势。
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  • OPA2650P图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站16年以上
  • OPA2650P
  • 数量5680 
  • 厂家BB 
  • 封装PDIP-8 
  • 批号25+ 
  • 原装正品特价销售
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  • OPA2650E图
  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • OPA2650E
  • 数量5600 
  • 厂家TI 
  • 封装MSOP8 
  • 批号23+ 
  • 100%深圳原装现货库存
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  • OPA2650E图
  • 首天国际(深圳)科技有限公司

     该会员已使用本站16年以上
  • OPA2650E
  • 数量638850 
  • 厂家TexasInstruments 
  • 封装MSOP8 
  • 批号2024+ 
  • 百分百原装正品,现货库存
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  • OPA2650P图
  • 深圳市赛尔通科技有限公司

     该会员已使用本站12年以上
  • OPA2650P
  • 数量8460 
  • 厂家BB 
  • 封装DIP 
  • 批号NEW 
  • 【优势库存】实力全新原装现货热卖
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  • OPA2650U图
  • 深圳市卓越微芯电子有限公司

     该会员已使用本站12年以上
  • OPA2650U
  • 数量6500 
  • 厂家BB 
  • 封装SOP8 
  • 批号20+ 
  • 百分百原装正品 真实公司现货库存 本公司只做原装 可开13%增值税发票,支持样品,欢迎来电咨询!
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  • OPA2650P图
  • 深圳市凯信扬科技有限公司

     该会员已使用本站7年以上
  • OPA2650P
  • 数量5660 
  • 厂家BURR-BROWN 
  • 封装DIP 
  • 批号21+ 
  • ▲▲▲诚信经营,服务至上,十年专注▲▲▲
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  • OPA2650P图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • OPA2650P
  • 数量3200 
  • 厂家BB 
  • 封装DIP-8 
  • 批号25+ 
  • 全新原装公司现货库存!
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  • OPA2650P图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • OPA2650P
  • 数量1100 
  • 厂家BB 
  • 封装DIP 
  • 批号24+ 
  • ★★专业IC现货,诚信经营,市场最优价★★
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  • OPA2650图
  • 深圳市科雨电子有限公司

     该会员已使用本站9年以上
  • OPA2650
  • 数量9800 
  • 厂家 
  • 封装原厂原装 
  • 批号24+ 
  • 原厂渠道,全新原装现货,欢迎查询!
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  • 171-4755-1968(微信同号) QQ:97877807
  • OPA2650图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • OPA2650
  • 数量250 
  • 厂家TI/德州仪器 
  • 封装NA/ 
  • 批号23+ 
  • 优势代理渠道,原装正品,可全系列订货开增值税票
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  • OPA2650U图
  • 上海磐岳电子有限公司

     该会员已使用本站11年以上
  • OPA2650U
  • 数量5800 
  • 厂家BB 
  • 封装SOP8 
  • 批号2024+ 
  • 全新原装现货,杜绝假货。
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  • OPA2650U图
  • 深圳市华科泰电子商行

     该会员已使用本站13年以上
  • OPA2650U
  • 数量6800 
  • 厂家BB 
  • 封装SOP-8 
  • 批号9852+ 
  • 绝对原装现货特价
  • QQ:405945546QQ:405945546 复制
    QQ:1439873477QQ:1439873477 复制
  • 0755-82567800 QQ:405945546QQ:1439873477
  • OPA2650U/2K5图
  • 深圳市集创讯科技有限公司

     该会员已使用本站5年以上
  • OPA2650U/2K5
  • 数量8500 
  • 厂家TI/德州仪器 
  • 封装SOP-8 
  • 批号24+ 
  • 原装进口正品现货,假一罚十价格优势
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  • OPA2650P图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • OPA2650P
  • 数量6420 
  • 厂家BB/TI 
  • 封装DIP8 
  • 批号24+ 
  • 全新原装现货,欢迎询购!
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  • 0755-83222787 QQ:1950791264QQ:221698708
  • OPA2650U图
  • 深圳市宏诺德电子科技有限公司

     该会员已使用本站8年以上
  • OPA2650U
  • 数量68000 
  • 厂家BB 
  • 封装SOP 
  • 批号22+ 
  • 全新进口原厂原装,优势现货库存,有需要联系电话:18818596997 QQ:84556259
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  • OPA2650U图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • OPA2650U
  • 数量10000 
  • 厂家BB 
  • 封装SOP8 
  • 批号2024+ 
  • 原装正品,假一罚十
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  • OPA2650E-250图
  • 北京首天国际有限公司

     该会员已使用本站16年以上
  • OPA2650E-250
  • 数量5038 
  • 厂家BB 
  • 封装SSOP8 
  • 批号2024+ 
  • 百分百原装正品,现货库存
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  • OPA2650PA图
  • 北京中其伟业科技有限公司

     该会员已使用本站16年以上
  • OPA2650PA
  • 数量2700 
  • 厂家TI 
  • 封装DIP8 
  • 批号16+ 
  • 特价,原装正品,绝对公司现货库存,原装特价!
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产品型号OPA2650的概述

OPA2650芯片概述 OPA2650是一款高性能的运算放大器,由德州仪器(Texas Instruments)公司制造。该芯片设计用于要求低失真、高增益带宽的应用场景,广泛应用于专业音频设备、电信、仪器仪表、医疗设备以及自动化控制等领域。其特点包括低噪声、低失真、高响应速度和优秀的直流精度,使其在许多高精度测量和信号处理应用中成为理想选择。 OPA2650详细参数 OPA2650的关键参数如下: - 电源电压范围:双电源±2.5V至±18V,单电源+5V至+36V - 增益带宽产品(GBP):50MHz - 输入失调电压:最大±250µV - 输入失调电压漂移:最大±0.1µV/°C - 输入共模范围:-0.1V至V+ - 1.5V - 输出电压摆幅:对于±15V电源,可达±13V(负载10kΩ) - 全电源电压摆幅:支持 rail-to-rail 输出 - 噪声密度:10nV/√H...

产品型号OPA2650的Datasheet PDF文件预览

®
OPA2650  
OPA2650  
OPA2650  
Dual Wideband, Low Power Voltage Feedback  
OPERATIONAL AMPLIFIER  
DESCRIPTION  
FEATURES  
The OPA2650 is a dual, low power, wideband voltage  
feedback operational amplifier. It features a high band-  
width of 360MHz as well as a 12-bit settling time of  
only 20ns. The low distortion allows its use in commu-  
nications applications, while the wide bandwidth and  
true differential input stage make it suitable for use in  
a variety of active filter applications. Its low distortion  
gives exceptional performance for telecommunica-  
tions, medical imaging and video applications.  
LOW POWER: 50mW/Chan.  
UNITY GAIN STABLE BANDWIDTH:  
360MHz  
FAST SETTLING TIME: 20ns to 0.01%  
LOW HARMONICS: –77dBc at 5MHz  
DIFFERENTIAL GAIN/PHASE ERROR:  
0.01%/0.025°  
HIGH OUTPUT CURRENT: 85mA  
The OPA2650 is internally compensated for unity-  
gain stability. This amplifier has a fully symmetrical  
differential input due to its “classical” operational  
amplifier circuit architecture. Its unusual combination  
of speed, accuracy and low power make it an outstand-  
ing choice for many portable, multi-channel and other  
high speed applications, where power is at a premium.  
APPLICATIONS  
HIGH RESOLUTION VIDEO  
BASEBAND AMPLIFIER  
CCD IMAGING AMPLIFIER  
ULTRASOUND SIGNAL PROCESSING  
ADC/DAC GAIN AMPLIFIER  
ACTIVE FILTERS  
The OPA2650 is also available in single (OPA650)  
and quad (OPA4650) configurations.  
+VS  
HIGH SPEED INTEGRATORS  
DIFFERENTIAL AMPLIFIER  
Non-Inverting  
Input  
Output  
Output  
Stage  
Inverting  
Input  
Current  
Mirror  
CC  
–VS  
NOTE: Diagram shows only one-half of the OPA2650.  
International Airport Industrial Park  
Mailing Address: PO Box 11400, Tucson, AZ 85734  
FAXLine: (800) 548-6133 (US/Canada Only)  
• Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111  
Internet: http://www.burr-brown.com/  
Cable: BBRCORP  
Telex: 066-6491  
FAX: (520) 889-1510  
Immediate Product Info: (800) 548-6132  
© 1994 Burr-Brown Corporation  
PDS-1266C  
Printed in U.S.A. June, 1997  
SPECIFICATIONS  
At TA = +25°C, VS = ±5V, RL = 100, and RFB = 402Ω, unless otherwise noted. RFB = 25for a gain of +1.  
OPA2650P, U, E  
MIN TYP MAX  
OPA2650PB, UB  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
FREQUENCY RESPONSE  
(1)  
Closed-Loop Bandwidth(2)  
G = +1  
G = +2  
G = +5  
360  
108  
32  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
V/µs  
V/µs  
ns  
ns  
ns  
ns  
ns  
G = +10  
16  
Gain Bandwidth Product  
Bandwidth for 0.1dB Flatness(2)  
Slew Rate(3)  
Over Temperature Range  
Rise Time  
G +5  
G = +2  
G = +1, 2V Step  
160  
21  
240  
220  
1
1
20  
G = +1, 0.2V Step  
G = +1, 0.2V Step  
G = +1, 2V Step  
G = +1, 2V Step  
G = +1, 2V Step  
Fall Time  
Settling Time  
0.01%  
0.1%  
1%  
11  
6.7  
Spurious Free Dynamic Range  
G = +1, f = 5.0MHz, VO = 2Vp-p  
RL = 100Ω  
72  
77  
0.01  
0.025  
–84  
dB  
dB  
%
Degrees  
dB  
RL = 402Ω  
Differential Gain  
Differential Phase  
Crosstalk(2)  
G = +2, NTSC, VO = 1.4Vp-p, RL = 150Ω  
G = +2, NTSC, VO = 1.4Vp-p, RL = 150Ω  
Input Referred, 5MHz, Channel-to-Channel  
INPUT OFFSET VOLTAGE  
Input Offset Voltage  
Average Drift  
Power Supply Rejection (+VS)  
(–VS)  
VCM = 0V  
±1  
±3  
76  
54  
±5  
±1  
±3  
mV  
µV/°C  
dB  
Input Referred, VS = ±4.5V to ±5.5V  
60  
47  
70  
50  
dB  
INPUT BIAS CURRENT  
Input Bias Current  
Over Temperature Range  
Input Offset Current  
VCM = 0V  
VCM = 0V  
5
20  
30  
1
10  
20  
0.5  
2
µA  
µA  
µA  
µA  
0.5  
0.2  
Over Temperature Range  
3
INPUT NOISE  
Input Voltage Noise  
Noise Density, f = 100Hz  
f = 10kHz  
f 1MHz  
Integrated Noise  
43  
9.4  
8.4  
nV/Hz  
nV/Hz  
nV/Hz  
fB = 10Hz to 100MHz  
Input Bias Current Noise  
Noise Density, f 0.1MHz  
84  
µVrms  
1.2  
pA/Hz  
INPUT VOLTAGE RANGE  
Common-Mode Input Range  
Over Temperature Range  
Common-Mode Rejection  
±2.8  
V
V
dB  
±2.2  
65  
70  
Input Referred, VCM = ±0.5V  
90  
INPUT IMPEDANCE  
Differential  
Common-Mode  
15 || 1  
16 || 1  
K|| pF  
M|| pF  
OPEN-LOOP GAIN  
Open-Loop Voltage Gain  
Over Temperature Range  
VO = ±2V, RL = 100Ω  
45  
43  
51  
47  
45  
dB  
dB  
OUTPUT  
Voltage Output  
Over Temperature Range  
No Load  
RL = 250Ω  
RL = 100Ω  
±2.2  
±2.2  
±2.0  
75  
65  
65  
±3.0  
±2.5  
±2.3  
110  
±2.4  
±2.4  
±2.2  
V
V
V
mA  
mA  
mA  
mA  
mA  
Output Current, Sourcing  
Over Temperature Range  
Output Current, Sinking  
Over Temperature Range  
Short Circuit Current  
85  
35  
150  
0.08  
Output Resistance  
f < 100kHz, G = +1  
POWER SUPPLY  
Specified Operating Voltage  
Operating Voltage Range  
Quiescent Current  
±5  
V
V
mA  
±4.5  
±5.5  
±15.5  
±17.5  
±13.5  
±16  
Both Channels, VS = ±5V  
±11  
Over Temperature Range  
mA  
THERMAL CHARACTERISTICS  
Temperature Range  
Thermal Resistance, θJA  
Specification: P, U, E, PB, UB  
Junction to Ambient  
–40  
+85  
°C  
P
U
E
8-Pin DIP  
SO-8  
MSOP-8  
100  
125  
150  
°C/W  
°C/W  
°C/W  
NOTES: (1) An asterisk () specifies the same value as the grade to the left. (2) Frequency response can be strongly influenced by PC board parasitics. The  
demonstration boards show low parasitic layouts for this part. Refer to the demonstration board layout for details. (3) Slew rate is rate of change from 10% to 90%  
of output voltage step.  
®
2
OPA2650  
ABSOLUTE MAXIMUM RATINGS  
ELECTROSTATIC  
Supply Voltage ................................................................................. ±5.5V  
Internal Power Dissipation ........................... See Thermal Characteristics  
Differential Input Voltage .................................................................. ±1.2V  
Input Voltage Range ............................................................................ ±VS  
Storage Temperature Range: P, PB, U, UB, E ............ –40°C to +125°C  
Lead Temperature (DIP, soldering, 10s) ...................................... +300°C  
(SO-8 and MSOP-8, soldering, 3s) ................ +260°C  
DISCHARGE SENSITIVITY  
Electrostatic discharge can cause damage ranging from per-  
formancedegradationtocompletedevicefailure.Burr-Brown  
Corporationrecommendsthatallintegratedcircuitsbehandled  
and stored using appropriate ESD protection methods.  
Junction Temperature (TJ ) ............................................................ +175°C  
ESD damage can range from subtle performance degradation  
to complete device failure. Precision integrated circuits may  
be more susceptible to damage because very small parametric  
changes could cause the device not to meet published speci-  
fications.  
PIN CONFIGURATION  
Top View  
DIP/SO-8/MSOP-8  
Output 1  
–Input 1  
+VS  
1
2
3
4
8
7
6
5
Output 2  
–Input 2  
+Input 1  
–VS  
+Input 2  
PACKAGE/ORDERING INFORMATION  
PACKAGE  
DRAWING  
NUMBER(1)  
TEMPERATURE  
RANGE  
PACKAGE  
MARKING(2)  
ORDERING  
NUMBER(3)  
PRODUCT  
PACKAGE  
OPA2650P  
OPA2650PB  
8-Pin Plastic DIP  
8-Pin Plastic DIP  
006  
006  
–40°C to +85°C  
–40°C to +85°C  
OPA2650P  
OPA2650PB  
OPA2650P  
OPA2650PB  
OPA2650U  
OPA2650UB  
SO-8 Surface Mount  
SO-8 Surface Mount  
182  
182  
–40°C to +85°C  
–40°C to +85°C  
OPA2650U  
OPA2650UB  
OPA2650U  
OPA2650UB  
OPA2650E  
MSOP-8  
337  
–40°C to +85°C  
B50  
OPA2650E-250  
OPA2650E-2500  
NOTE: (1) For detailed drawing and dimension table, see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) The “B” grade will be marked with a “B”  
by pin 8. (3) The MSOP-8 is available on 7" tape and reel with 250 parts, and on 14" tape and reel with 2500 parts. For example, ordering 250 pieces of “OPA2650E-  
250” will get a single 250 piece tape and reel. Refer to Appendix B of Burr-Brown IC Data Book for detailed Tape and Reel Mechanical information.  
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use  
of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the  
circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.  
®
3
OPA2650  
TYPICAL PERFORMANCE CURVES  
At TA = +25°C, VS = ±5V, RL = 100, and RFB = 402Ω, unless otherwise noted. RFB = 25for a gain of +1.  
COMMON-MODE REJECTION  
vs INPUT COMMON-MODE VOLTAGE  
AOL, PSR AND CMRR vs TEMPERATURE  
100  
90  
80  
70  
60  
50  
40  
100  
90  
80  
70  
60  
CMRR  
PSR+  
PSR–  
AOL  
–50  
–25  
0
25  
50  
75  
125  
–4  
–3  
–2  
–1  
0
1
2
3
4
Temperature (°C)  
Common-Mode Voltage (V)  
INPUT BIAS CURRENT vs TEMPERATURE  
SUPPLY CURRENT vs TEMPERATURE  
6
5
4
3
3
2
1
0
12  
11  
10  
9
IB  
IQ  
VOS  
–50  
–25  
0
25  
50  
75  
100  
–75  
–50  
–25  
0
25  
50  
75  
100  
125  
Temperature (°C)  
Temperature (°C)  
INPUT VOLTAGE AND CURRENT NOISE  
vs FREQUENCY  
OUTPUT CURRENT vs TEMPERATURE  
110  
100  
90  
100  
10  
1
I+O  
Voltage Noise  
80  
IO–  
Non-inverting and  
Inverting Current Noise  
70  
100  
1k  
10k  
100k  
1M  
–50  
–25  
0
25  
50  
75  
100  
Frequency (Hz)  
Temperature (°C)  
®
4
OPA2650  
TYPICAL PERFORMANCE CURVES (CONT)  
At TA = +25°C, VS = ±5V, RL = 100, and RFB = 402Ω, unless otherwise noted. RFB = 25for a gain of +1.  
RECOMMENDED ISOLATION RESISTANCE  
vs CAPACITIVE LOAD  
SMALL SIGNAL TRANSIENT RESPONSE  
(G = +1)  
40  
30  
20  
10  
0
200  
160  
120  
80  
40  
25Ω  
0
RISO  
–40  
–80  
–120  
–160  
–200  
OPA2650  
CL  
1kΩ  
0
20  
40  
60  
80  
100  
Time (5ns/div)  
Capacitive Load, CL (pF)  
LARGE SIGNAL TRANSIENT RESPONSE  
(G = +1)  
CLOSED-LOOP BANDWIDTH (G = +1)  
2.0  
1.6  
6
3
1.2  
DIP Bandwidth  
= 366MHz  
0.8  
0.4  
0
0
–0.4  
–0.8  
–1.2  
–1.6  
–2.0  
–3  
–6  
–9  
SO-8 Bandwidth  
= 331MHz  
MSOP-8 Bandwidth  
= 281MHz  
1M  
10M  
Frequency (Hz)  
100M  
1G  
Time (5ns/div)  
CLOSED-LOOP BANDWIDTH (G = +2)  
CLOSED-LOOP BANDWIDTH (G = +5)  
MSOP-8/SO-8/DIP Bandwidth = 31MHz  
9
6
20  
17  
14  
11  
8
MSOP-8/SO-8/DIP Bandwidth = 108MHz  
3
0
–3  
–6  
–9  
5
2
1M  
10M  
100M  
1G  
1M  
10M  
100M  
Frequency (Hz)  
Frequency (Hz)  
®
5
OPA2650  
TYPICAL PERFORMANCE CURVES (CONT)  
At TA = +25°C, VS = ±5V, RL = 100, and RFB = 402Ω, unless otherwise noted. RFB = 25for a gain of +1.  
OPEN-LOOP GAIN AND PHASE  
vs FREQUENCY  
CLOSED-LOOP BANDWIDTH (G = +10)  
MSOP-8/SO-8/DIP Bandwidth = 16MHz  
60  
50  
40  
30  
20  
10  
0
+45  
0
26  
23  
20  
17  
14  
11  
8
Gain  
–45  
–90  
–135  
–180  
–225  
Phase  
5
2
1k  
10k  
100k  
1M  
10M  
100M  
1G  
1M  
10M  
100M  
Frequency (Hz)  
Frequency (Hz)  
HARMONIC DISTORTION  
vs TEMPERATURE (G = +1, fO = 5MHz)  
HARMONIC DISTORTION vs FREQUENCY  
(G = +1, VO = 2Vp-p)  
–60  
–65  
–70  
–75  
–80  
–45  
–50  
–55  
–60  
–65  
–70  
–75  
–80  
–85  
–90  
–95  
3fO  
2fO  
3fO  
2fO  
100k  
1M  
10M  
Frequency (Hz)  
100M  
–75  
–50  
–25  
0
25  
50  
75  
100  
125  
Temperature (°C)  
5MHz HARMONIC DISTORTION  
vs OUTPUT SWING  
10MHz HARMONIC DISTORTION  
vs OUTPUT SWING  
–60  
–50  
–60  
–70  
–80  
–90  
G = +2  
G = +2  
–70  
–80  
3fO  
2fO  
3fO  
2fO  
–90  
–100  
0.1  
1
10  
0.1  
1
10  
Output Swing (Vp-p)  
Output Swing (Vp-p)  
®
6
OPA2650  
TYPICAL PERFORMANCE CURVES (CONT)  
At TA = +25°C, VS = ±5V, RL = 100, and RFB = 402Ω, unless otherwise noted. RFB = 25for a gain of +1.  
HARMONIC DISTORTION vs GAIN  
(f = 5MHZ, VO = 2Vp-p)  
–40  
3fO  
–50  
–60  
2fO  
–70  
–80  
1
2
3
4
5
6
7
8
9
10  
Non-Inverting Gain (V/V)  
opened in all of the ground and power planes. Otherwise,  
ground and power planes should be unbroken elsewhere on  
the board.  
APPLICATIONS INFORMATION  
DISCUSSION OF PERFORMANCE  
The OPA2650 is a dual low power, wideband voltage feed-  
back operational amplifier. Each channel is internally com-  
pensated to provide unity gain stability. The OPA2650’s  
voltage feedback architecture features true differential and  
fully symmetrical inputs. This minimizes offset errors, mak-  
ing the OPA2650 well suited for implementing filter and  
instrumentation designs. As a dual operational amplifier,  
OPA2650 is an ideal choice for designs requiring multiple  
channels where reduction of board space, power dissipation  
and cost are critical. Its AC performance is optimized to  
provide a gain bandwidth product of 160MHz and a fast 0.1%  
settling time of 11ns, which is an important consideration in  
high speed data conversion applications. Along with its  
excellent settling characteristics, the low DC input offset of  
±1mV and drift of ±3µV/°C support high accuracy require-  
ments. In applications requiring a higher slew rate and wider  
bandwidth, such as video and high bit rate digital communi-  
cations, consider the dual current feedback OPA2658.  
b) Minimize the distance (< 0.25") from the two power pins  
to high frequency 0.1µF decoupling capacitors. At the pins,  
the ground and power plane layout should not be in close  
proximity to the signal I/O pins. Avoid narrow power and  
ground traces to minimize inductance between the pins and  
the decoupling capacitors. Larger (2.2µF to 6.8µF) decoupling  
capacitors, effective at lower frequencies, should also be  
used. These may be placed somewhat farther from the  
device and may be shared among several devices in the same  
area of the PC board.  
c) Careful selection and placement of external compo-  
nents will preserve the high frequency performance of the  
OPA2650. Resistors should be a very low reactance type.  
Surface mount resistors work best and allow a tighter overall  
layout. Metal film or carbon composition axially-leaded  
resistors can also provide good high frequency performance.  
Again, keep their leads as short as possible. Never use  
wirewound type resistors in a high frequency application.  
Since the output pin and the inverting input pin are most  
sensitive to parasitic capacitance, always position the feed-  
back and series output resistor, if any, as close as possible to  
the package pins. Other network components, such as non-  
inverting input termination resistors, should also be placed  
close to the package.  
CIRCUIT LAYOUT AND BASIC OPERATION  
Achieving optimum performance with a high frequency am-  
plifier like the OPA2650 requires careful attention to layout  
parasitics and selection of external components. Recommen-  
dations for PC board layout and component selection include:  
a) Minimize parasitic capacitance to any ac ground for all  
of the signal I/O pins. Parasitic capacitance on the output  
and inverting input pins can cause instability; on the non-  
inverting input it can react with the source impedance to  
cause unintentional bandlimiting. To reduce unwanted ca-  
pacitance, a window around the signal I/O pins should be  
Even with a low parasitic capacitance shunting the resistor,  
excessively high resistor values can create significant time  
constants and degrade performance. Good metal film or  
surface mount resistors have approximately 0.2pF in shunt  
with the resistor. For resistor values > 1.5k, this adds a  
pole and/or zero below 500MHz that can affect circuit  
®
7
OPA2650  
operation. Keep resistor values as low as possible consistent  
with output loading considerations. The 402feedback  
used for the Typical Performance Plots is a good starting  
point for design. Note that a 25feedback resistor, rather  
than a direct short, is suggested for a unity gain follower.  
This effectively reduces the Q of what would otherwise be  
a parasitic inductance (the feedback wire) into the parasitic  
capacitance at the inverting input.  
fied total supply voltage of 11V. Higher supply voltages can  
break down internal junctions possibly leading to catastrophic  
failure. Single supply operation is possible as long as com-  
mon mode voltage constraints are observed. The common  
mode input and output voltage specifications can be inter-  
preted as a required headroom to the supply voltage. Observ-  
ing this input and output headroom requirement will allow  
non-standard or single supply operation. Figure 1 shows one  
approach to single-supply operation.  
d) Connections to other wideband devices on the board  
may be made with short direct traces or through on-board  
transmission lines. For short connections, consider the trace  
and the input to the next device as a lumped capacitive load.  
Relatively wide traces (50 to 100 mils) should be used,  
preferably with ground and power planes opened up around  
them. Estimate the total capacitive load and set RISO from  
the plot of recommended RISO vs capacitive load. Low  
parasitic loads may not need an RISO since the OPA2650 is  
nominally compensated to operate with a 2pF parasitic load.  
+VS  
+VS  
VS  
2
VS  
2
VOUT  
=
+ 2•VAC  
ROUT  
R
R
VAC  
1/2  
OPA2650  
RL  
If a long trace is required and the 6dB signal loss intrinsic to  
doubly terminated transmission lines is acceptable, imple-  
ment a matched impedance transmission line using microstrip  
or stripline techniques (consult an ECL design handbook for  
microstrip and stripline layout techniques). A 50environ-  
ment is not necessary on board, and in fact a higher imped-  
ance environment will improve distortion as shown in the  
distortion vs load plot. With a characteristic impedance  
defined based on board material and desired trace dimen-  
sions, a matching series resistor into the trace from the  
output of the amplifier is used as well as a terminating shunt  
resistor at the input of the destination device. Remember  
also that the terminating impedance will be the parallel  
combination of the shunt resistor and the input impedance of  
the destination device; the total effective impedance should  
match the trace impedance. Multiple destination devices are  
best handled as separate transmission lines, each with their  
own series and shunt terminations.  
402Ω  
402Ω  
FIGURE 1. Single Supply Operation.  
OFFSET VOLTAGE ADJUSTMENT  
If additional offset adjustment is needed, the circuit in  
Figure 2 can be used without degrading offset drift with  
temperature. Avoid external adjustment whenever possible  
since extraneous noise, such as power supply noise, can be  
inadvertently coupled into the amplifier’s inverting input  
terminal. Remember that additional offset errors can be  
created by the amplifier’s input bias currents. Whenever  
possible, match the impedance seen by both inputs as is  
shown with R3. This will reduce the output offset voltage  
caused by the amplifier’s input offset current.  
If the 6dB attenuation loss of a doubly terminated line is  
unacceptable, a long trace can be series-terminated at the  
source end only. This will help isolate the line capacitance  
from the op amp output, but will not preserve signal integrity  
as well as a doubly terminated line. If the shunt impedance  
at the destination end is finite, there will be some signal  
attenuation due to the voltage divider formed by the series  
and shunt impedances.  
R2  
+VCC  
e) Sockets are not recommended for high speed parts like  
the OPA2650. The additional lead length and pin-to-pin  
capacitance introduced by the socket creates an extremely  
troublesome parasitic network which can make it almost  
impossible to achieve a smooth, stable response. Best results  
are obtained by soldering the part onto the board. If socket-  
ing for the DIP package is desired, high frequency flush  
mount pins (e.g., McKenzie Technology #710C) can give  
good results.  
RTrim  
20kΩ  
1/2  
OPA2650  
47kΩ  
0.1µF  
–VCC  
R1  
(1)R3 = R1 || R2  
NOTE: (1) R3 is  
optional and can  
be used to cancel  
offset errors due  
to input bias currents.  
VIN or Ground  
Output Trim Range +VCC  
R2  
RTrim  
R2  
RTrim  
to –VCC  
SUPPLY VOLTAGES  
The OPA2650 is nominally specified for operation using ±5V  
power supplies. A 10% tolerance on the supplies, or an ECL  
–5.2V for the negative supply, is within the maximum speci-  
FIGURE 2. Offset Voltage Trim.  
®
8
OPA2650  
ESD PROTECTION  
supply current for both channels times the total supply  
voltage across the part. PDL1 and PDL2 will depend on the  
required output signals and loads. For a grounded resistive  
loads, and equal bipolar supplies, they would be at a  
maximum when the outputs are fixed at a voltage equal to  
1/2 either supply voltage. Under this condition, PDL1 = VS /  
(4•RL1) where RL1 includes feedback network loading. PDL2  
is calculated the same way.  
ESD damage has been well recognized for MOSFET de-  
vices, but any semiconductor device is vulnerable to this  
potentially damaging source. This is particularly true for  
very high speed, fine geometry processes.  
2
ESD damage can cause subtle changes in amplifier input  
characteristics without necessarily destroying the device. In  
precision operational amplifiers, this may cause a noticeable  
degradation of offset voltage and drift. Therefore, ESD  
handling precautions are strongly recommended when han-  
dling the OPA2650.  
Note that it is the power in the output stages, and not into  
the loads, that determines internal power dissipation.  
Operating junction temperature (TJ) is given by TA + PD  
θJA, where TA is the ambient temperature.  
OUTPUT DRIVE CAPABILITY  
As an example, compute the maximum TJ for an OPA2650U  
where both op amps are at G = +2, RL = 100, RFB = 402,  
±VS = ±5V, and at the specified maximum TA = +85°C.  
This gives:  
The OPA2650 has been optimized to drive 75and 100Ω  
resistive loads. The device can drive 2Vp-p into a 75Ω  
load. This high-output drive capability makes the OPA2650  
an ideal choice for a wide range of RF, IF, and video  
applications. In many cases, additional buffer amplifiers  
are unneeded.  
PDQ = 10V •17.5mA = 175mW  
(
)
2
5V  
(
)
PDL1 = PDL2  
=
= 70mW  
Many demanding high-speed applications such as driving  
A/D converters require op amps with low wideband output  
impedance. For example, low output impedance is essential  
when driving the signal-dependent capacitances at the inputs  
of flash A/D converters. As shown in Figure 3, the OPA2650  
maintains very low-closed loop output impedance over fre-  
quency. Closed-loop output impedance increases with fre-  
quency since loop gain decreases with frequency.  
4 • 100|| 804Ω  
(
)
PD = 175mW + 2 70mW = 315mW  
(
)
TJ = 85°C + 0.315W •125°C / W = 124°C  
CAPACITIVE LOADS  
The OPA2650’s output stage has been optimized to drive low  
resistive loads. Capacitive loads, however, will decrease the  
amplifier’s phase margin which may cause high frequency  
peaking or oscillations. Capacitive loads greater than 10pF  
should be isolated by connecting a small resistance, usually  
15to 30, in series with the output as shown in Figure 4.  
This is particularly important when driving high capacitance  
loads such as flash A/D converters. Increasing the gain from  
+1 will improve the capacitive load drive due to increased  
phase margin.  
SMALL-SIGNAL OUTPUT IMPEDANCE  
vs FREQUENCY  
1k  
G = +1  
100  
10  
1
In general, capacitive loads should be minimized for opti-  
mum high frequency performance. Coax lines can be driven  
if the cable is properly terminated. The capacitance of coax  
cable (29pF/foot for RG-58) will not load the amplifier  
when the coaxial cable or transmission line is terminated in  
its characteristic impedance.  
0.1  
0.01  
10k  
100k  
1M  
10M  
100M  
Frequency (Hz)  
FIGURE 3. Small-Signal Output Impedance vs Frequency.  
25Ω  
(RISO typically 15to 30)  
THERMAL CONSIDERATIONS  
The OPA2650 will not require heatsinking under most  
operating conditions. Maximum desired junction tempera-  
ture will set a maximum allowed internal power dissipation  
as described below. In no case should the maximum junction  
temperature be allowed to exceed 175°C.  
RISO  
OPA2650  
CL  
RL  
The total internal power dissipation (PD) is a the sum of  
quiescent power (PDQ) and additional power dissipated in  
the two output stages (PDL1 and PDL2) while delivering load  
power. Quiescent power is simply the specified no-load  
FIGURE 4. Driving Capacitive Loads.  
®
9
OPA2650  
FREQUENCY RESPONSE COMPENSATION  
The percentage change in closed-loop gain over a specified  
change in output voltage level is defined as dG. dP is defined  
as the change in degrees of the closed-loop phase over the  
same output voltage change. dG and dP are both specified at  
the NTSC sub-carrier frequency of 3.58MHz. dG and dP  
increase closed-loop gain and output voltage transition. All  
measurements were performed using a Tektronix model  
VM700 Video Measurement Set.  
Each channel of the OPA2650 is internally compensated to  
be stable at unity gain with a nominal 60° phase margin.  
This lends itself well to wideband integrator and buffer  
applications. Phase margin and frequency response flatness  
will improve at higher gains. Recall that an inverting gain of  
–1 is equivalent to a gain of +2 for bandwidth purposes, i.e.,  
noise gain = 2. The external compensation techniques devel-  
oped for voltage feedback op amps can be applied to this  
device. For example, in the non-inverting configuration,  
placing a capacitor across the feedback resistor will reduce  
the gain to +1 starting at f = (1/2πRFCF). Alternatively, in the  
inverting configuration, the bandwidth may be limited with-  
out modifying the inverting gain by placing a series RC  
network to ground on the inverting node. This has the effect  
of increasing the noise gain at high frequencies, thereby  
limiting the bandwidth for the inverting input signal through  
the gain-bandwidth product.  
DISTORTION  
The OPA2650’s harmonic distortion characteristics into a  
100load are shown versus frequency and power output in  
the typical performance curves. Distortion can be signifi-  
cantly improved by increasing the load resistance as illus-  
trated in Figure 5. Remember to include the contribution of  
the feedback resistance when calculating the effective load  
resistance seen by the amplifier.  
At higher gains, the gain-bandwidth of this voltage feedback  
topology will limit bandwidth according to the open-loop  
frequency response curve. For applications requiring a wider  
bandwidth at higher gains, consider the dual current feed-  
back model, OPA2658. In applications where a large feed-  
back resistor is required (such as photodiode transimpedance  
circuits), precautions must be taken to avoid gain peaking  
due to the pole formed by the feedback resistor and the  
capacitance on the inverting input. This pole can be compen-  
sated by connecting a small capacitor in parallel with the  
feedback resistor, creating a cancelling zero term. In other  
high-gain applications, use of a three-resistor “T” connec-  
tion will reduce the feedback network impedance which  
–60  
(G = +1, fO = 5MHz)  
–70  
2fO  
–80  
3fO  
–90  
10  
20  
50  
100  
200  
500  
1k  
reacts with the parasitic capacitance at the summing node.  
Load Resistance ()  
FIGURE 5. 5MHz Harmonic Distortion vs Load Resistance.  
PULSE SETTLING TIME  
High speed amplifiers like the OPA2650 are capable of  
extremely fast settling time with a pulse input. Excellent  
frequency response flatness and phase linearity are required  
to get the best settling times. As shown in the specifications  
table, settling time for a 2V step at a gain of +1 for the  
OPA2650 is extremely fast. The specification is defined as  
the time required, after the input transition, for the output to  
settle within a specified error band around its final value. For  
a 2V step, 1% settling corresponds to an error band of  
±20mV, 0.1% to an error band of ±2mV, and 0.01% to an  
error band of ±0.2mV. For the best settling times, particu-  
larly into an ADC capacitive load, little or no peaking in the  
frequency response can be allowed. Using the recommended  
RISO for capacitive loads will limit this peaking and reduce  
the settling times. Fast, extremely fine scale settling (0.01%)  
requires close attention to ground return currents in the  
supply decoupling capacitors. For highest performance, con-  
sider the OPA642 which offers considerably higher open  
loop DC gain.  
CROSSTALK  
Crosstalk is the undesired result of the signal of one channel  
mixing with and reproducing itself in the output of the other  
channel. Crosstalk occurs in most multichannel integrated  
circuits. In dual devices, the effect of crosstalk is measured by  
driving one channel and observing the output of the undriven  
channel over various frequencies. The magnitude of this effect  
is referenced in terms of channel-to-channel crosstalk and  
expressed in decibels. “Input referred” points to the fact that  
there is a direct correlation between gain and crosstalk, there-  
fore at increased gain, crosstalk also increases by a factor  
equal to that of the gain. Figure 6 illustrates the measured  
effect of crosstalk in the OPA2650U.  
SPICE MODELS  
Computer simulation of circuit performance using SPICE is  
often useful when analyzing the performance of analog  
circuits and systems. This is particularly true for Video and  
RF amplifier circuits where parasitic capacitance and induc-  
tance can have a major effect on circuit performance. SPICE  
models are available on a disk from the Burr-Brown Appli-  
cations Department.  
DIFFERENTIAL GAIN AND PHASE  
Differential Gain (dG) and Differential Phase (dP) are among  
the more important specifications for video applications.  
®
10  
OPA2650  
DEMONSTRATION BOARDS  
Demonstration boards are available for each OPA2650 pack-  
age style. These boards implement a very low parasitic  
layout that will produce the excellent frequency and pulse  
responses shown in the Typical Performance Curves. For  
each package style, the recommended demonstration boards  
are:  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
G = +1  
DEMONSTRATION BOARD  
PACKAGE  
PRODUCT  
DEM-OPA265xP  
8-Pin DIP  
OPA2650P  
OPA2650PB  
DEM-OPA265xU  
DEM-OPA26xxE  
SO-8  
OPA2650U  
OPA2650UB  
1M  
10M  
Frequency (Hz)  
100M  
400M  
MSOP-8  
OPA2650E  
Contact your local Burr-Brown sales office or distributor to  
order demonstration boards.  
FIGURE 6. Channel-to-Channel Crosstalk.  
TYPICAL APPLICATION  
402Ω  
402Ω  
75Transmission Line  
75Ω  
1/2  
OPA2650  
VOUT  
Video  
Input  
75Ω  
75Ω  
FIGURE 7. Low Distortion Video Amplifier.  
®
11  
OPA2650  
R12  
R13  
J5  
–InB  
C3  
2.2µF  
R11  
R16  
1
2
+5V  
C1  
GND  
0.1µF  
P1  
6
5
8
R14  
J6  
1/2  
7
OutB  
R9  
J4  
OPA2650  
+InB  
R8  
R10  
R3  
R4  
J2  
–InA  
R2  
R15  
2
3
R1  
J1  
1/2  
1
OutA  
R6  
J3  
OPA2650  
+InA  
4
1
2
GND  
–5V  
R5  
C2  
0.1µF  
R7  
P2  
C4  
2.2µF  
FIGURE 8. Circuit Detail for DEM-OPA265xP Demonstration Board.  
DEM-OPA265xP Demonstration Board Layout  
(A)  
(B)  
(C)  
(D)  
FIGURE 9. Evaluation Board Silkscreen (Solder Side). 9b. Evaluation Board Silkscreen (Component Side). 9c. Evaluation  
Board Layout (Solder Side). 9d. Evaluation Board (Component Side).  
®
12  
OPA2650  
配单直通车
OPA2650E产品参数
型号:OPA2650E
是否Rohs认证: 不符合
生命周期:Obsolete
Reach Compliance Code:unknown
风险等级:5.72
放大器类型:OPERATIONAL AMPLIFIER
架构:VOLTAGE-FEEDBACK
25C 时的最大偏置电流 (IIB):20 µA
频率补偿:YES
最大输入失调电压:5000 µV
JESD-30 代码:R-PDSO-G8
JESD-609代码:e0
低-偏置:NO
低-失调:NO
微功率:NO
标称负供电电压 (Vsup):-5 V
功能数量:2
端子数量:8
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP
封装等效代码:TSSOP8,.19
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
功率:NO
电源:+-5 V
可编程功率:NO
认证状态:Not Qualified
子类别:Operational Amplifiers
最大压摆率:17.5 mA
供电电压上限:5.5 V
标称供电电压 (Vsup):5 V
表面贴装:YES
技术:BIPOLAR
温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING
端子节距:0.635 mm
端子位置:DUAL
最小电压增益:140
宽带:YES
Base Number Matches:1
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