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OPA365

OPA2365

SBOS365A − JUNE 2006 − REVISED JULY 2006

2.2V, 50MHz, Low-Noise,

Single-Supply Rail-to-Rail

OPERATIONAL AMPLIFIERS

FEATURES

DESCRIPTION

The OPAx365 zer∅-crossover series rail-to-rail high-

D

RAIL-TO-RAIL INPUT WITHOUT CROSSOVER

performance CMOS operational amplifiers are opti-

mized for very low voltage, single-supply applications.

Rail-to-rail input/output, low-noise (4.5nV/√Hz) and

high-speed operations (50MHz Gain Bandwidth) make

them ideal for driving sampling analog-to-digital con-

verters (ADCs). Applications incude audio, signal con-

ditioning, and sensor amplification. The OPA365 family

of op amps are well-suited for cell phone power amplifi-

er control loops.

2.2V OPERATION

LOW OFFSET: 200µV

WIDE BANDWIDTH: 50MHz

CMRR: 100dB (min)

HIGH SLEW RATE: 25V/µs

LOW NOISE: 4.5nV//Hz

LOW THD+NOISE: 0.0006%

QUIESCENT CURRENT: 5mA (max)

microPACKAGE: SOT23-5

Special features include excellent common-mode re-

jection ratio (CMRR), no input stage crossover distor-

tion, high input impedance and rail-to-rail input and out-

put swing. The input common-mode range includes

both the negative and positive supplies. The output volt-

age swing is within 10mV of the rails.

APPLICATIONS

D

SIGNAL CONDITIONING

DATA ACQUISITION

PROCESS CONTROL

ACTIVE FILTERS

The OPA365 (single version) is available in the micro-

SIZE SOT23-5 and SO-8 packages. The OPA2365

(dual version) is offered in the microSIZE DFN-8 (3mm

x 3mm) and SO-8 packages. All versions are specified

for operation from −40°C to +125°C. Single and dual

versions have identical specifications for maximum de-

sign flexibility.

TEST EQUIPMENT

AUDIO

WIDEBAND AMPLIFIERS

PACKAGE

OPA365

n

OPA2365

OPA365 vs COMPETITION

SOT23-5

0

20

40

60

f_i= 10kHz

BW = 30kHz

(1)

SO-8

n

+5V

−

(1)

DFN-8

(1)

V_IN

Available Q3, 2006.

Competitor B

−

80

Competitor A

−

100

120

OPA365

1

2

3

4

5

V_IN= V_OUT(V_PP

)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

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Copyright  2006, Texas Instruments Incorporated

www.ti.com

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SBOS365A − JUNE 2006 − REVISED JULY 2006

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be

handledwith appropriate precautions. Failure to observe

(1)

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V

(2)

Signal Input Terminals, Voltage

. . . . (V−) −0.5V to (V+) + 0.5V

. . . . . . . . . . . . . . . . . . . . 10mA

proper handling and installation procedures can cause damage.

(2)

Signal Input Terminals, Current

(3)

ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

Output Short-Circuit

. . . . . . . . . . . . . . . . . . . . . . . . . Continuous

Operating Temperature . . . . . . . . . . . . . . . . . . . . . −40°C to +150°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

ESD Rating

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4000V

Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V

(1)

Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods

may degrade device reliability. These are stress ratings only, and

functional operation of the device at these or any other conditions

beyond those specified is not supported.

(2)

(3)

Input terminals are diode-clamped to the power-supply rails.

Input signals that can swing more than 0.5V beyond the supply

rails should be current limited to 10mA or less.

Short-circuit to ground, one amplifier per package.

ORDERING INFORMATION⁽¹⁾

PRODUCT

PACKAGE-LEAD

PACKAGE DESIGNATOR

PACKAGE MARKING

SOT23-5

DBV

D

OAVQ

O365A

O2365A

BRA

OPA365

(2)

SO-8

(2)

SO-8

D

OPA2365

(2)

DFN-8

DRB

(1)

(2)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site

at www.ti.com.

Available Q3, 2006.

PIN CONFIGURATIONS

Top View

OPA365

OPA2365

OPA365

NC⁽¹⁾

V+

NC⁽¹⁾

1

2

3

4

8

7

6

5

V_OUT

1

2

3

5

4

V+

V_OUT

A

1

2

3

4

8

7

6

5

V+

−

IN

+IN

−

V_OUTB

V

IN A

V_OUT

NC⁽¹⁾

−

+IN

IN

+IN A

IN B

−

V

−

V

+IN B

SOT23−5

SO−8, DFN−8

SO−8

(1)

NC denotes no internal connection.

2

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SBOS365A − JUNE 2006 − REVISED JULY 2006

ELECTRICAL CHARACTERISTICS: V = +2.2V to +5.5V

S

Boldface limits apply over the specified temperature range, T = −40°C to +125°C.

A

At T = +25°C, R = 10kΩ connected to V /2, V

= V /2, and V

= V /2, unless otherwise noted.

A

L

S

CM

S

OUT S

OPAx365

TYP

MIN

MAX

200

PARAMETER

OFFSET VOLTAGE

Input Offset Voltage

TEST CONDITIONS

UNIT

V

100

1

10

0.2

µV

OS

Drift

dV /dT

µV/°C

µV/V

OS

vs Power Supply

PSRR

V

= +2.2V to +5.5V

100

S

Channel Separation, dc

INPUT BIAS CURRENT

Input Bias Current

over Temperature

Input Offset Current

I

0.2

10

pA

B

See Typical Characteristics

I

0.2

10

OS

NOISE

Input Voltage Noise, f = 0.1Hz to 10Hz

Input Voltage Noise Density, f = 100kHz

Input Current Noise Density, f = 10kHz

e

i

5

4.5

4

µV

PP

nV/√Hz

fA/√Hz

n

INPUT VOLTAGE RANGE

Common-Mode Voltage Range

V

(V−) − 0.1

(V+) + 0.1

V

CM

Common-Mode Rejection Ratio

INPUT CAPACITANCE

Differential

CMRR

(V−) − 0.1V 3 V

3 (V+) + 0.1V

100

120

dB

CM

6

2

pF

Common-Mode

OPEN-LOOP GAIN

Open-Loop Voltage Gain

A

R

= 10kΩ, 100mV < V < (V+) − 100mV

100

94

120

dB

OL

L

O

= 600Ω, 200mV < V < (V+) − 200mV

O

R

L

= 600Ω, 200mV < V < (V+) − 200mV

O

FREQUENCY RESPONSE

Gain-Bandwidth Product

Slew Rate

V = 5V

S

GBW

SR

50

25

200

MHz

V/µs

ns

G = +1

4V Step, G = +1

Settling Time, 0.1%

t

S

0.01%

300

ns

Overload Recovery Time

Total Harmonic Distortion + Noise

OUTPUT

V

x Gain > V

< 0.1

0.0006

µs

%

IN

S

THD+N R = 600Ω, V = 4V , G = +1, f = 1kHz

L

O

PP

Voltage Output Swing from Rail

over Temperature

R

= 10kΩ, V = 5.5V

10

20

mV

L

S

Short-Circuit Current

Capacitive Load Drive

Open-Loop Output Impedance

I

C

65

mA

SC

See Typical Characteristics

30

L

f = 1MHz, I = 0

Ω

O

POWER SUPPLY

Specified Voltage Range

Quiescent Current Per Amplifier

over Temperature

TEMPERATURE RANGE

Specified Range

Thermal Resistance

SOT23-5

V

2.2

5.5

5

V

mA

S

I

= 0

4.6

Q

O

−40

+125

°C

q

°C/W

JA

200

150

46

SO-8

DFN-8

3

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SBOS365A − JUNE 2006 − REVISED JULY 2006

TYPICAL CHARACTERISTICS

At T = +25°C, V = +5V, and C = 0pF, unless otherwise noted.

A

S

L

POWER SUPPLY AND COMMON−MODE

REJECTION RATIO vs FREQUENCY

OPEN−LOOP GAIN/PHASE vs FREQUENCY

140

120

100

80

0

−

140

120

100

80

CMRR

45

Phase

Gain

60

90

PSRR

60

40

20

135

180

20

0

−

20

0

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

Frequency (Hz)

OFFSET VOLTAGE

OFFSET VOLTAGE DRIFT

PRODUCTION DISTRIBUTION

V_S= 5.5V

µ

_

µ

Offset Voltage ( V)

Offset Voltage Drift ( V/ C)

INPUT BIAS CURRENT vs TEMPERATURE

INPUT BIAS CURRENT vs COMMON−MODE VOLTAGE

500

400

300

200

100

0

1000

900

800

700

600

500

400

300

200

100

0

V_CMSpecified Range

−

25

−

0.5

0

−

50

25

0

25

50

75

100

125

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

V_CM(V)

_

Temperature ( C)

4

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SBOS365A − JUNE 2006 − REVISED JULY 2006

TYPICAL CHARACTERISTICS (continued)

At T = +25°C, V = +5V, and C = 0pF, unless otherwise noted.

A

S

L

OUTPUT VOLTAGE vs OUTPUT CURRENT

SHORT−CIRCUIT CURRENT vs TEMPERATURE

3

2

1

0

70

60

50

40

30

20

10

0

10

20

30

40

50

60

70

80

V_S

=

1.1V

2.75V

I_SC

+

−

_

40 C

−

_

40 C

_

+25 C

_

+25 C

−

_

+125 C

_

+125 C

−

1

2

3

−

I_SC

−

25

0

10

20

30

40

50

60

70

80

90 100

50

0

25

50

75

100

125

_

Output Current (mA)

Temperature ( C)

QUIESCENT CURRENT vs TEMPERATURE

QUIESCENT CURRENT vs SUPPLY VOLTAGE

4.80

4.74

4.68

4.62

4.56

4.50

4.75

4.50

4.25

4.00

3.75

−

50

25

0

25

50

75

100

125

2.2 2.5

3.0

3.5

4.0

4.5

5.0

5.5

_

Temperature ( C)

Supply Voltage (V)

TOTAL HARMONIC DISTORTION + NOISE

vs FREQUENCY

0.1Hz to 10Hz

INPUT VOLTAGE NOISE

0.01

Ω

G = 10, R_L= 600

V_O= 1V_RMS

0.001

V_O= 1.448V_RMS

V_O= 1V_RMS

Ω

G = +1, R_L= 600

0.0001

1s/div

10

100

1k

10k 100k

Frequency (Hz)

5

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TYPICAL CHARACTERISTICS (continued)

At T = +25°C, V = +5V, and C = 0pF, unless otherwise noted.

A

S

L

OVERSHOOT vs CAPACITIVE LOAD

G = +1

INPUT VOLTAGE NOISE SPECTRAL DENSITY

1k

100

10

60

50

40

30

20

10

0

−

G =

1

G = +10

−

G = 10

1

0

100

1k

10

100

1k

10k

100k

Capacitive Load (pF)

Frequency (Hz)

SMALL−SIGNAL STEP RESPONSE

LARGE−SIGNAL STEP RESPONSE

G = 1

Ω

R_L= 10k

Ω

R_L= 10k

V_S

= 2.5

V_S

= 2.5

Time (50ns/div)

Time (250ns/div)

SMALL−SIGNAL STEP RESPONSE

LARGE−SIGNAL STEP RESPONSE

G = 1

R_L= 600

V_S2.5

G = 1

R_L= 600

V_S2.5

Ω

=

Time (50ns/div)

Time (250ns/div)

6

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APPLICATIONS INFORMATION

R₂

Ω

10k

OPERATING CHARACTERISTICS

The OPA365 amplifier parameters are fully specified

from +2.2V to +5.5V. Many of the specifications apply

from −40°C to +125°C. Parameters that can exhibit sig-

nificant variance with regard to operating voltage or

temperature are presented in the Typical Characteris-

tics.

+1.5V

C₁

100nF

R₁

V+

Ω

1k

OPA365

V_OUT

GENERAL LAYOUT GUIDELINES

V_IN

The OPA365 is a wideband amplifier. To realize the full

operational performance of the device, good high-fre-

quency printed circuit board (PCB) layout practices are

required. Low-loss, 0.1µF bypass capacitors must be

connected between each supply pin and ground as

close to the device as possible. The bypass capacitor

traces should be designed for minimum inductance.

−

V

C₂

100nF

−

1.5V

a) Dual Supply Connection

BASIC AMPLIFIER CONFIGURATIONS

R₂

Ω

10k

As with other single-supply op amps, the OPA365 may

be operated with either a single supply or dual supplies.

A typical dual-supply connection is shown in Figure 1,

which is accompanied by a single-supply connection.

The OPA365 is configured as a basic inverting amplifier

with a gain of −10V/V. The dual-supply connection has

an output voltage centered on zero, while the single−

supply connection has an output centered on the com-

+3V

C₁

100nF

R₁

V+

Ω

1k

mon-mode voltage V . For the circuit shown, this volt-

age is 1.5V, but may be any value within the common-

CM

V_OUT

OPA365

mode input voltage range. The OPA365 V

extends 100mV beyond the power-supply rails.

range

V_IN

CM

−

V

V_CM= 1.5V

b) Single−Supply Connection

Figure 1. Basic Circuit Connections

7

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Figure 2 shows a single-supply, electret microphone

application where V is provided by a resistive divider.

CM

The divider also provides the bias voltage for the elec-

tret element.

Ω

49k

Clean 3.3V Supply

3.3V

Ω

4k

6k

INPUT AND ESD PROTECTION

V_OUT

OPA365

The OPA365 incorporates internal electrostatic dis-

charge (ESD) protection circuits on all pins. In the case

of input and output pins, this protection primarily con-

sists of current steering diodes connected between the

input and power-supply pins. These ESD protection

diodes also provide in-circuit, input overdrive protec-

tion, provided that the current is limited to 10mA as

stated in the Absolute Maximum Ratings. Figure 3

shows how a series input resistor may be added to the

driven input to limit the input current. The added resistor

contributes thermal noise at the amplifier input and its

value should be kept to the minimum in noise-sensitive

applications.

Ω

5k

Electret

Microphone

µ

1 F

Figure 2. Microphone Preamplifier

V+

RAIL−TO−RAIL INPUT

I_OVERLOAD

The OPA365 product family features true rail-to-rail in-

put operation, with supply voltages as low as 1.1V

(2.2V). A unique zer∅-crossover input topology elimi-

nates the input offset transition region typical of many

rail-to-rail, complementary stage operational amplifiers.

This topology also allows the OPA365 to provide superi-

or common−mode performance over the entire input

range, which extends 100mV beyond both power-sup-

ply rails; see Figure 4. When driving ADCs, the highly

linear VCM range of the OPA365 assures that the op

amp/ADC system linearity performance is not compro-

mised.

10mA max

V_OUT

OPA365

V_IN

Ω

5k

Figure 3. Input Current Protection

OFFSET VOLTAGE vs COMMON−MODE VOLTAGE

200

150

100

50

V_S

= 2.75V

OPA365

0

−

50

−

100

150

200

Competitors

0

−

1

3

2

1

2

3

Common−Mode Voltage (V)

Figure 4. OPA365 has Linear Offset Over the

Entire Common-Mode Range

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A simplified schematic illustrating the rail-to-rail input

circuitry is shown in Figure 5.

V_S

Regulated

Charge Pump

V

_OUT= V_CC+1.8V

CAPACITIVE LOADS

V_CC+ 1.8V

The OPA365 may be used in applications where driving

a capacitive load is required. As with all op amps, there

may be specific instances where the OPA365 can be-

come unstable, leading to oscillation. The particular op

amp circuit configuration, layout, gain and output load-

ing are some of the factors to consider when establish-

ing whether an amplifier will be stable in operation. An

op amp in the unity-gain (+1V/V) buffer configuration

and driving a capacitive load exhibits a greater tenden-

cy to be unstable than an amplifier operated at a higher

noise gain. The capacitive load, in conjunction with the

op amp output resistance, creates a pole within the

feedback loop that degrades the phase margin. The

degradation of the phase margin increases as the ca-

pacitive loading increases.

Patent Pending

Very Low Ripple

Topology

I_BIAS

V_OUT

V_IN

−

V_IN+

When operating in the unity-gain configuration, the

OPA365 remains stable with a pure capacitive load up

to approximately 1nF. The equivalent series resistance

(ESR) of some very large capacitors (C > 1µF) is suffi-

L

cient to alter the phase characteristics in the feedback

loop such that the amplifier remains stable. Increasing

the amplifier closed-loop gain allows the amplifier to

drive increasingly larger capacitance. This increased

capability is evident when observing the overshoot re-

sponse of the amplifier at higher voltage gains. See the

typical characteristic graph, Small-Signal Overshoot

vs. Capacitive Load.

I_BIAS

Figure 5. Simplified Schematic

One technique for increasing the capacitive load drive

capability of the amplifier operating in unity gain is to in-

sert a small resistor, typically 10Ω to 20Ω, in series with

the output; see Figure 6. This resistor significantly re-

duces the overshoot and ringing associated with large

capacitive loads. A possible problem with this technique

is that a voltage divider is created with the added series

resistor and any resistor connected in parallel with the

capacitive load. The voltage divider introduces a gain

error at the output that reduces the output swing. The

error contributed by the voltage divider may be insignifi-

V+

R_S

V_OUT

OPA365

Ω

10 to

V_IN

C_L

R_L

Ω

20

cant. For instance, with a load resistance, R = 10kΩ,

L

and R = 20Ω, the gain error is only about 0.2%. Howev-

S

er, when R is decreased to 600Ω, which the OPA365

L

Figure 6. Improving Capacitive Load Drive

is able to drive, the error increases to 7.5%.

9

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ACHIEVING AN OUTPUT LEVEL OF

ZERO VOLTS (0V)

V+ = +5V

Certain single-supply applications require the op amp

output to swing from 0V to a positive full-scale voltage

and have high accuracy. An example is an op amp

employed to drive a single-supply ADC having an input

range from 0V to +5V. Rail-to-rail output amplifiers with

very light output loading may achieve an output level

OPA365

V_OUT

V_IN

µ

500 A

Ω

R_P= 10k

Op Amps

Negative

Supply

within millivolts of 0V (or +V at the high end), but not

S

0V. Furthermore, the deviation from 0V only becomes

greater as the load current required increases. This in-

creased deviation is a result of limitations of the CMOS

output stage.

−

V = 5V

(Additional

Negative Supply)

Grounded

When a pull-down resistor is connected from the ampli-

fier output to a negative voltage source, the OPA365

can achieve an output level of 0V, and even a few milli-

volts below 0V. Below this limit, nonlinearity and limiting

conditions become evident. Figure 7 illustrates a circuit

using this technique.

Figure 7. Swing-to-Ground

R₃

Ω

549

A pull-down current of approximately 500µA is required

C₂

150pF

when OPA365 is connected as a unity-gain buffer.

A practical termination voltage (V

) is −5V, but

NEG

other convenient negative voltages also may be

used. The pull-down resistor R is calculated from

V+

L

R₁

R₂

1.24k

R = [(V −V )/(500µA)]. Using a minimum output

L

O

NEG

Ω

549

voltage (V ) of 0V, R = [0V−(−5V)]/(500µA)] = 10kΩ.

O

L

V_IN

Keep in mind that lower termination voltages result in

smaller pull-down resistors that load the output during

positive output voltage excursions.

OPA365

V_OUT

C₁

1nF

−

V

Note that this technique does not work with all op amps

and should only be applied to op amps such as the

OPA365 that have been specifically designed to oper-

ate in this manner. Also, operating the OPA365 output

at 0V changes the output stage operating conditions,

resulting in somewhat lower open-loop gain and band-

width. Keep these precautions in mind when driving a

capacitive load because these conditions can affect cir-

cuit transient response and stability.

Figure 8. Second-Order Butterworth 500kHz

Low-Pass Filter

ACTIVE FILTERING

The OPA365 is well-suited for active filter applications

requiring a wide bandwidth, fast slew rate, low-noise,

single-supply operational amplifier. Figure 8 shows a

500kHz, 2nd-order, low-pass filter utilizing the multiple−

feedback (MFB) topology. The components have been

selected to provide a maximally-flat Butterworth

response. Beyond the cutoff frequency, roll-off is

−40dB/dec. The Butterworth response is ideal for ap-

plications requiring predictable gain characteristics

such as the anti-aliasing filter used ahead of an ADC.

10

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ꢂ ꢀꢉ ꢣꢠꢡ ꢢ

www.ti.com

SBOS365A − JUNE 2006 − REVISED JULY 2006

One point to observe when considering the MFB filter

is that the output is inverted, relative to the input. If this

inversion is not required, or not desired, a noninverting

output can be achieved through one of these options:

1) adding an inverting amplifier; 2) adding an additional

2nd-order MFB stage; or 3) using a noninverting filter

topology such as the Sallen-Key (shown in Figure 9).

OPA365 an ideal driver for modern ADCs. Also, be-

cause it is free of the input offset transition characteris-

tics inherent to some rail-to-rail CMOS op amps, the

OPA365 provides low THD and excellent linearity

throughout the input voltage swing range.

Figure 10 shows the OPA365 driving an ADS8326,

16-bit, 500kSPS converter. The amplifier is connected

as a unity-gain, noninverting buffer and has an output

swing to 0V, making it directly compatible with the ADC

minus full-scale input level. The 0V level is achieved by

powering the OPA365 V− pin with a small negative volt-

age established by the diode forward voltage drop.

A small, signal-switching diode or Schottky diode

provides a suitable negative supply voltage of −0.3 to

−0.7V. The supply rail-to-rail is equal to V+, plus the

small negative voltage.

MFB and Sallen-Key, low-pass and high-pass filter syn-

thesis is quickly accomplished using TI’s FilterPro pro-

gram. This software is available as a free download at

www.ti.com.

DRIVING AN ANALOG-TO-DIGITAL CONVERTER

Very wide common-mode input range, rail-to-rail input

and output voltage capability and high speed make the

C₃

220pF

R₃

R₁

R₂

Ω

150k

Ω

1.8k

19.5k

V_IN= 1V_RMS

C₁

3.3nF

C₂

47pF

OPA365

V_OUT

Figure 9. Configured as a 3-Pole, 20kHz, Sallen-Key Filter

+5V

C₁

100nF

+5V

(1)

R₁

V+

Ω

100

+IN

OPA365

ADS8326

16−Bit

100kSPS

(1)

C₃

1nF

−

V

−

IN

V_IN

0 to 4.096V

REF IN

Optional⁽²⁾

+5V

R₂

SD1

BAS40

Ω

500

REF3240

4.096V

−

5V

C₂

C₄

100nF

(1) Suggested value; may require adjustment based on specific application.

(2) Single−supply applications lose a small number of ADC codes near ground

due to op amp output swing limitation. If a negative power supply is available,

NOTES:

−

this simple circuit creates a 0.3V supply to allow output swing to true ground

potential.

Figure 10. Driving the ADS8326

11

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ꢂꢀꢉꢣ ꢠꢡ ꢢ

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SBOS365A − JUNE 2006 − REVISED JULY 2006

One method for driving an ADC that negates the need

for an output swing down to 0V uses a slightly com-

pressed ADC full-scale input range (FSR). For exam-

ple, the 16-bit ADS8361 (shown in Figure 11) has a

maximum FSR of 0V to 5V, when powered by a +5V

to maintain the ADC gain accuracy. An additional bene-

fit of this method is the elimination of the negative sup-

ply voltage; it requires no additional power-supply cur-

rent.

An RC network, consisting of R and C , is included be-

1

supply and V

of 2.5V. The idea is to match the ADC

REF

tween the op amp and the ADS8361. It not only pro-

vides a high-frequency filter function, but more impor-

tantly serves as a charge reservoir used for charging

the converter internal hold capacitance. This capability

assures that the op amp output linearity is maintained

as the ADC input characteristics change throughout the

conversion cycle. Depending on the particular applica-

input range with the op amp full linear output swing

range; for example, an output range of +0.1 to +4.9V.

The reference output from the ADS8361 ADC is divided

down from 2.5V to 2.4V using a resistive divider. The

ADC FSR then becomes 4.8V centered on a com-

PP

mon-mode voltage of +2.5V. Current from the ADS8361

reference pin is limited to about 10µA. Here, 5µA was

used to bias the divider. The resistors must be precise

tion and ADC, some optimization of the R and C val-

1

ues may be required for best transient performance.

R₂

Ω

10k

+5V

C₁

100nF

+5V

R₁

V+

(1)

Ω

10k

R₃

Ω

100

−

IN

ADS8361

16−Bit

100kSPS

OPA365

(1)

V_IN

C₂

1nF

0.1V to 4.9V

+IN

−

V

REF IN

REF OUT

+2.5V

R₄

NOTE: (1) Suggested value; may require adjustment

based on specific application.

Ω

20k

+2.4V

R₅

C₃

Ω

480k

µ

1 F

Figure 11. Driving the ADS8361

12

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SBOS365A − JUNE 2006 − REVISED JULY 2006

Figure 12 illustrates the OPA2365 dual op amp provid-

ing signal conditioning within an ADS1258 bridge sen-

sor circuit. It follows the ADS1258 16:1 multiplexer and

is connected as a differential in/differential out amplifier.

The voltage gain for this stage is approximately 10V/V.

Driving the ADS1258 internal ADC in differential mode,

rather than in a single-ended, exploits the full linearity

performance capability of the converter. For best com-

For best performance, the +5V supply should be as free

as possible of noise and transients.

When the ADS1258 data rate is set to maximum and

the chop feature enabled, this circuit yields 12 bits of

noise-free resolution with a 50mV full-scale input.

The chop feature is used to reduce the ADS1258 offset

and offset drift to very low levels. A 2.2nF capacitor is

required across the ADC inputs to bypass the sampling

currents. The 47Ω resistors provide isolation for the

OPA2365 outputs from the relatively large, 2.2nF ca-

pacitive load. For more information regarding the

ADS1258, see the product data sheet available for

down load at www.ti.com.

mon-mode rejection the two R resistors should be

2

closely matched.

Note that in Figure 12, the amplifiers, bridges,

ADS1258 and internal reference are powered by the

same single +5V supply. This ratiometric connection

helps cancel excitation voltage drift effects and noise.

+5V

+

RFI

µ

10 F

0.1 F

Ω

2k

RFI

AIN0

AIN1

AVSS

AVDD

2k

REFP

REFN

+

µ

0.1 F

10 F

Ω

2k

ADS1258

RFI

AIN14

2k

AIN15

AINCOM

+5V

2.2nF

µ

0.1 F

R₃

Ω

47

OPA2365

Ω

R₂= 10k

Ω

R₁= 2.2k

Ω

R₂= 10k

R₃

Ω

47

OPA2365

NOTE: G = 1 + 2R₂/R₁. Match R₂resistors for optimum CMRR.

Figure 12. Conditioning Input Signals to the ADS1258 on a Single-Supply

13

PACKAGE OPTION ADDENDUM

www.ti.com

21-Jul-2006

PACKAGING INFORMATION

Orderable Device

OPA365AIDBVR

OPA365AIDBVRG4

OPA365AIDBVT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOT-23

DBV

5

3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOT-23

DBV

3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

OPA365AIDBVTG4

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

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