PCM1789PWR原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

PCM1789

Burr-Brown Audio

www.ti.com.............................................................................................................................................................................................. SBAS451–OCTOBER 2008

24-Bit, 192-kHz Sampling, Enhanced Multi-Level ΔΣ,

Stereo, Audio Digital-to-Analog Converter

1

FEATURES

•

External Reset Pin

Power Supplies:

2345

•

Enhanced Multi-Level Delta-Sigma DAC:

–

High Performance: Differential, f_S= 48 kHz

THD+N: –94 dB

– 5 V for Analog and 3.3 V for Digital

•

Package: TSSOP-24

SNR: 113 dB

Operating Temperature Range:

Dynamic Range: 113 dB

Sampling Rate: 8 kHz to 192 kHz

– –40°C to +85°C

APPLICATIONS

System Clock: 128 f_S, 192 f_S, 256 f_S, 384 f_S,

512 f_S, 768 f_S, 1152 f_S

•

Blu-ray Disc™ Players

DVD Players

AV Receivers

Home Theaters

Car Audio External Amplifiers

Car Audio AVN Applications

–

Differential Voltage Output: 8 V_PP

Analog Low-Pass Filter Included

4x/8x Oversampling Digital Filter:

–

Passband Ripple: ±0.0018 dB

Stop Band Attenuation: –75 dB

–

Zero Flags (16-/20-/24-Bits)

DESCRIPTION

•

Flexible Audio Interface:

The PCM1789 is a high-performance, single-chip,

24-bit, stereo, audio digital-to-analog converter (DAC)

with differential outputs. The two-channel, 24-bit DAC

employs an enhanced multi-level, delta-sigma (ΔΣ)

modulator, and supports 8 kHz to 192 kHz sampling

rates and a 16-/20-/24-/32-bit width digital audio input

word on the audio interface. The audio interface of

PCM1789 supports a 24-bit, DSP format in addition

to I²S, left-justified, and right-justified formats.

–

I/F Format: I²S™, Left-/Right-Justified, DSP

Data Length: 16, 20, 24, 32 Bits

•

Flexible Mode Control:

–

3-Wire SPI™, 2-Wire I²C™-Compatible

Serial Control Interface, or

Hardware Control

–

Connect Up To 4 Devices on One SPI Bus

Multi Functions via SPI or I²C I/F:

The PCM1789 can be controlled through a three-wire,

SPI-compatible or two-wire, I²C-compatible serial

interface in software, which provides access to all

functions including digital attenuation, soft mute,

de-emphasis, and so forth. Also, hardware control

mode provides two user-programmable functions

through two control pins. The PCM1789 is available

in a 24-pin TSSOP package.

–

Audio I/F Format Select: I²S, Left-Justified,

Right-Justified, DSP

–

Digital Attenuation and Soft Mute

Digital De-Emphasis: 32 kHz, 44.1 kHz,

48 kHz

–

Data Polarity Control

Power-Save Mode

•

1

Multi Functions via Hardware Control:

–

Audio I/F Format Select: I²S, Left-Justified

Digital De-Emphasis Filter: 44.1 kHz

Analog Mute by Clock Halt Detection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

4

5

Blu-ray Disc is a trademark of Blu-ray Disc Association.

SPI is a trademark of Motorola, Inc.

I2S, I2C are trademarks of NXP Semiconductors.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

PCM1789

SBAS451–OCTOBER 2008.............................................................................................................................................................................................. www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION⁽¹⁾

SPECIFIED

PACKAGE-

LEAD

PACKAGE

DESIGNATOR

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT MEDIA,

QUANTITY

PRODUCT

PCM1789PW

Tube, 60

PCM1789

TSSOP-24

PW

–40°C to +85°C

PCM1789

PCM1789PWR

Tape and Reel, 2000

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

VCC1, VCC2

VDD

PCM1789

UNIT

V

–0.3 to +6.5

Supply voltage

–0.3 to +4.0

V

Ground voltage differences: AGND1, AGND2, DGND

Supply voltage differences: VCC1, VCC2

±0.1

V

±0.1

V

RST, ADR5, MS, MC, MD, SCKI, AMUTEI

BCK, LRCK, DIN, MODE, ZERO1, ZERO2

–0.3 to +6.5

V

Digital input voltage

–0.3 to (VDD + 0.3) < +4.0

V

Analog input voltage: VCOM, VOUTL±, VOUTR±

Input current (all pins except supplies)

Ambient temperature under bias

Storage temperature

–0.3 to (VCC + 0.3) < +6.5

V

±10

–40 to +125

–55 to +150

+150

mA

°C

Junction temperature

Lead temperature (soldering, 5s)

Package temperature (IR reflow, peak)

+260

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Over operating free-air temperature range (unless otherwise noted).

PCM1789

PARAMETER

MIN

4.5

TYP

MAX

5.5

UNIT

V

Analog supply voltage, VCC

Digital supply voltage, VDD

Digital Interface

5.0

3.3

3.0

3.6

V

LVTTL-compatible

Sampling frequency, LRCK

8

192

kHz

MHz

V_PP

kΩ

Digital input clock frequency

Analog output voltage

System clock frequency, SCKI

Differential

2.048

36.864

8

To ac-coupled GND

To dc-coupled GND

5

Analog output load resistance

15

kΩ

Analog output load capacitance

Digital output load capacitance

Operating free-air temperature

50

20

pF

PCM1789 consumer grade

–40

+25

+85

°C

2

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PCM1789

www.ti.com.............................................................................................................................................................................................. SBAS451–OCTOBER 2008

ELECTRICAL CHARACTERISTICS: Digital Input/Output

All specifications at T_A= +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, f_S= 48 kHz, SCKI = 512 f_S, 24-bit data, and Sampling

mode = Auto, unless otherwise noted.

PCM1789

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DATA FORMAT

Audio data interface format

Audio data word length

Audio data format

I²S, LJ, RJ, DSP

16, 20, 24, 32

Bits

MSB first, twos complement

Sampling frequency

f_S

8

48

192

kHz

128 f_S, 192 f_S, 256 f_S,

384 f_S, 512 f_S, 768 f_S, 1152 f_S

System clock frequency

2.048

36.864

MHz

INPUT LOGIC

(1)(2)

(3)(4)

(2)(3)

(1)(4)

V_IH

V_IL

V_IH

V_IL

I_IH

2.0

VDD

0.8

VDC

µA

Input logic level

Input logic current

5.5

0.8

V_IN= VDD

V_IN= 0 V

V_IN= VDD

V_IN= 0 V

±10

+100

±10

I_IL

µA

I_IH

+65

µA

Input logic current

OUTPUT LOGIC

Output logic level

I_IL

µA

(5)

V_OH

I_OUT= –4 mA

I_OUT= +4 mA

2.4

VDC

(5)(6)

V_OL

0.4

REFERENCE OUTPUT

VCOM output voltage

VCOM output impedance

0.5 ×

VCC1

V

7.5

kΩ

µA

Allowable VCOM output source/sink current

1

(1) BCK and LRCK (Schmitt trigger input with 50-kΩ typical internal pull-down resistor).

(2) DIN (Schmitt trigger input).

(3) SCKI, ADR5/ADR1/RSV, MC/SCL/FMT, MD/SDA/DEMP, and AMUTEI (Schmitt trigger input, 5-V tolerant).

(4) RST and MS/ADR0/RSV (Schmitt trigger input with 50-kΩ typical internal pull-down resistor, 5-V tolerant).

(5) ZERO1 and ZERO2.

(6) AMUTEO and SDA (I²C mode, open-drain low output).

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PCM1789

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ELECTRICAL CHARACTERISTICS: DAC

All specifications at T_A= +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, f_S= 48 kHz, SCKI = 512 f_S, 24-bit data, and Sampling

mode = Auto, unless otherwise noted.

PCM1789

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RESOLUTION

16

24

Bits

DC ACCURACY

Gain mismatch channel-to-channel

Gain error

±2.0

±1.0

±6.0

% of FSR

Bipolar zero error

DYNAMIC PERFORMANCE⁽¹⁾⁽²⁾

f_S= 48 kHz

–94

113

109

108

–88

dB

Total harmonic distortion + noise

Dynamic range

THD+N

V_OUT= 0 dB

f_S= 96 kHz

f_S= 192 kHz

f_S= 48 kHz, EIAJ, A-weighted

f_S= 96 kHz, EIAJ, A-weighted

f_S= 192 kHz, EIAJ, A-weighted

f_S= 48 kHz, EIAJ, A-weighted

f_S= 96 kHz, EIAJ, A-weighted

f_S= 192 kHz, EIAJ, A-weighted

f_S= 48 kHz

106

103

Signal-to-noise ratio

Channel separation

SNR

f_S= 96 kHz

f_S= 192 kHz

ANALOG OUTPUT

Output voltage

Differential

1.6 × VCC1

0.5 × VCC1

V_PP

V

Center voltage

To ac-coupled GND⁽³⁾

To dc-coupled GND⁽³⁾

f = 20 kHz

5

kΩ

dB

Load impedance

15

–0.04

–0.18

LPF frequency response

f = 44 kHz

DIGITAL FILTER PERFORMANCE WITH SHARP ROLL-OFF

Except SCKI = 128 f_Sand 192 f_S

0.454 × f_S

0.432 × f_S

Hz

dB

Passband (single, dual)

Passband (quad)

SCKI = 128 f_Sand 192 f_S

Except SCKI = 128 f_Sand 192 f_S

SCKI = 128 f_Sand 192 f_S

0.546 × f_S

0.569 × f_S

Stop band (single, dual)

Stop band (quad)

Passband ripple

< 0.454 × f_S, 0.432 × f_S

> 0.546 × f_S, 0.569 × f_S

±0.0018

Stop band attenuation

–75

(1) In differential mode at VOUTx± pin, f_OUT= 1 kHz, using Audio Precision System II, Average mode with 20-kHz LPF and 400-Hz HPF.

(2) f_S= 48 kHz: SCKI = 512 f_S(single), f_S= 96 kHz : SCKI = 256 f_S(dual), f_S= 192 kHz : SCKI = 128 f_S(quad).

(3) Allowable minimum input resistance of differential-to-single-ended converter with D-to-S gain = G is calculated as (1 + 2G)/(1 + G) × 5k

for ac-coupled, and (1+ 0.9G)/(1 + G) × 15k for dc-coupled connection; refer to Figure 38 and Figure 39.

4

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PCM1789

www.ti.com.............................................................................................................................................................................................. SBAS451–OCTOBER 2008

ELECTRICAL CHARACTERISTICS: DAC (continued)

All specifications at T_A= +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, f_S= 48 kHz, SCKI = 512 f_S, 24-bit data, and Sampling

mode = Auto, unless otherwise noted.

PCM1789

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL FILTER PERFORMANCE WITH SLOW ROLL-OFF

Passband

Stop band

0.328 × f_S

±0.0013

Hz

dB

0.673 × f_S

–75

Passband ripple

< 0.328 × f_S

Stop band attenuation

> 0.673 × f_S

DIGITAL FILTER PERFORMANCE

Except SCKI = 128 f_Sand 192 f_S

SCKI = 128 f_Sand 192 f_S

28/f_S

19/f_S

±0.1

sec

dB

Group delay time (single, dual)

Group delay time (quad)

De-emphasis error

ELECTRICAL CHARACTERISTICS: Power-Supply Requirements

All specifications at T_A= +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, f_S= 48 kHz, SCKI = 512 f_S, 24-bit data, and Sampling

mode = Auto, unless otherwise noted.

PCM1789

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER-SUPPLY REQUIREMENTS

VCC1/2

VDD

4.5

3.0

5.0

3.3

19

5.5

3.6

28

VDC

mA

µA

Voltage range

f_S= 48 kHz

f_S= 192 kHz

Full power-down⁽¹⁾

I_CC

19

170

18

Supply current

f_S= 48 kHz

30

mA

µA

I_DD

f_S= 192 kHz

Full power-down⁽¹⁾

22

60

f_S= 48 kHz

154

168

1.05

239

mW

Power dissipation

f_S= 192 kHz

Full power-down⁽¹⁾

TEMPERATURE RANGE

Operating temperature

Thermal resistance

PCM1789 consumer grade

TSSOP-24

–40

+85

°C

θ_JA

115

°C/W

(1) SCKI, BCK, and LRCK stopped.

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PCM1789

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PIN CONFIGURATION

PW PACKAGE

TSSOP-24

(TOP VIEW)

ADR5/ADR1/RSV

MS/ADR0/RSV

MC/SCL/FMT

MD/SDA/DEMP

MODE

LRCK

BCK

1

2

3

4

5

6

7

8

9

24

23

22

21

20

19

18

17

16

15

14

13

DIN

RST

SCKI

VDD

ZERO1

PCM1789

ZERO2/AMUTEO

AMUTEI

DGND

VCC1

VCOM

VCC2

AGND2

AGND1 10

VOUTL- 11

VOUTL+ 12

VOUTR-

VOUTR+

TERMINAL FUNCTIONS

TERMINAL

PULL-

5-V

NAME

LRCK

1

I/O

I

DOWN TOLERANT

DESCRIPTION

Yes

No

Yes

No

—

No

Yes

—

Audio data word clock input

Audio data bit clock input

Audio data input

BCK

2

I

DIN

3

I

RST

4

I

Reset and power-down control input with active low

System clock input

SCKI

5

I

VDD

6

—

O

—

I

Digital power supply, +3.3 V

DGND

VCC1

7

—

Digital ground

8

—

Analog power supply 1, +5 V

VCOM

AGND1

VOUTL–

VOUTL+

VOUTR+

VOUTR–

AGND2

VCC2

9

—

Voltage common decoupling

10

11

12

13

14

15

16

17

18

19

—

Analog ground 1

No

—

No

—

Negative analog output from DAC left channel

Positive analog output from DAC left channel

Positive analog output from DAC right channel

Negative analog output from DAC right channel

Analog ground 2

—

Analog power supply 2, +5 V

AMUTEI

No

Yes

No

Analog mute control input with active low

Zero detect flag output 2/Analog mute control output⁽¹⁾with active low

Zero detect flag output 1

ZERO2/AMUTEO

ZERO1

O

Control port mode selection. Tied to VDD: SPI, ADR6 = 1, pull-up: SPI,

ADR6 = 0, pull-down: H/W auto mode, tied to DGND: I²C

MODE

20

I

No

Input data for SPI, data for I²C⁽¹⁾, de-emphasis control for hardware

control mode

Clock for SPI, clock for I²C, format select for hardware control mode

Chip Select for SPI, address select 0 for I²C, reserve (set low) for

hardware control mode

MD/SDA/DEMP

MC/SCL/FMT

MS/ADR0/RSV

21

22

23

I/O

No

Yes

I

Yes

Address select 5 for SPI, address select 1 for I²C, reserve (set low) for

hardware control mode

ADR5/ADR1/RSV

24

I

No

Yes

(1) Open-drain configuration in out mode.

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PCM1789

www.ti.com.............................................................................................................................................................................................. SBAS451–OCTOBER 2008

FUNCTIONAL BLOCK DIAGRAM

VOUTL+

BCK

LRCK

DIN

DAC

(Left Ch)

Interpolation

Filter

Audio Interface

Clock Manager

VOUTL-

Digital Attenuation

Digital Mute

De-Emphasis

VOUTR+

DAC

(Right Ch)

VOUTR-

SCKI

VCOM

MODE

ADR5/ADR1/RSV

MS/ADR0/RSV

MC/SCL/FMT

MD/SDA/DEMP

RST

VCC1

AGND1

VCC2

AGND2

VDD

Control Interface

(SPI/I²C/Hardware)

Power Supply

and

Common Voltage

AMUTEI

ZERO1

DGND

ZERO2/AMUTEO

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PCM1789

SBAS451–OCTOBER 2008.............................................................................................................................................................................................. www.ti.com

TYPICAL CHARACTERISTICS: Digital Filter

All specifications at T_A= +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, f_S= 48 kHz, SCKI = 512 f_S, 24-bit data, and Sampling

mode = Auto, unless otherwise noted.

FREQUENCY RESPONSE

(Single Rate)

FREQUENCY RESPONSE PASSBAND

(Single Rate)

0

-20

0.010

0.008

0.006

0.004

0.002

0

Sharp

Slow

Sharp

Slow

-40

-60

-80

-0.002

-0.004

-0.006

-0.008

-0.010

-100

-120

-140

0

1

2

3

4

0

0.1

0.2

0.3

0.4

0.5

Normalized Frequency (f_S)

Figure 1.

Normalized Frequency (f_S)

Figure 2.

FREQUENCY RESPONSE

(Dual Rate)

FREQUENCY RESPONSE PASSBAND

(Dual Rate)

0

-20

0.010

0.008

0.006

0.004

0.002

0

Sharp

Slow

Sharp

Slow

-40

-60

-80

-0.002

-0.004

-0.006

-0.008

-0.010

-100

-120

-140

2

3

4

0.1

0.2

0.3

0.4

1

Normalized Frequency (f_S)

Figure 3.

Normalized Frequency (f_S)

Figure 4.

FREQUENCY RESPONSE

(Quad Rate)

FREQUENCY RESPONSE PASSBAND

(Quad Rate)

0

-20

0.010

0.008

0.006

0.004

0.002

0

Sharp

Slow

Sharp

Slow

-40

-60

-80

-0.002

-0.004

-0.006

-0.008

-0.010

-100

-120

-140

1.0

1.5

2.0

0.1

0.2

0.3

0.4

0.5

Normalized Frequency (f_S)

Figure 5.

Normalized Frequency (f_S)

Figure 6.

8

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PCM1789

www.ti.com.............................................................................................................................................................................................. SBAS451–OCTOBER 2008

TYPICAL CHARACTERISTICS: Digital De-Emphasis Filter

All specifications at T_A= +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, f_S= 48 kHz, SCKI = 512 f_S, 24-bit data, and Sampling

mode = Auto, unless otherwise noted.

DE-EMPHASIS CHARACTERISTIC

(f_S= 48 kHz)

DE-EMPHASIS CHARACTERISTIC

(f_S= 44.1 kHz)

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

10 12 14 16 18 20

Frequency (kHz)

22

10

12

14

16

18

20

0

2

4

6

8

0

2

4

6

8

Frequency (kHz)

Figure 7.

Figure 8.

DE-EMPHASIS CHARACTERISTIC

(f_S= 32 kHz)

ANALOG FILTER CHARACTERISTIC

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

0

-10

-20

-30

-40

-50

10

12

14

1M

10M

0

2

4

6

8

1k

10k

100k

Frequency (kHz)

Frequency (Hz)

Figure 9.

Figure 10.

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PCM1789

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TYPICAL CHARACTERISTICS: Dynamic Performance

All specifications at T_A= +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, f_S= 48 kHz, SCKI = 512 f_S, 24-bit data, and Sampling

mode = Auto, unless otherwise noted.

TOTAL HARMONIC DISTORTION + NOISE

vs TEMPERATURE

DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO

vs TEMPERATURE

-92

-94

118

116

114

112

110

108

106

Dynamic Range

SNR

-96

-98

-100

-102

-104

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

Figure 11.

Figure 12.

TOTAL HARMONIC DISTORTION + NOISE

vs SUPPLY VOLTAGE

DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO

vs SUPPLY VOLTAGE

-92

-94

118

116

114

112

110

108

106

Dynamic Range

SNR

-96

-98

-100

-102

-104

4.50

4.75

5.00

5.25

5.50

4.50

4.75

5.00

5.25

5.50

Supply Voltage (V)

Figure 13.

Figure 14.

10

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TYPICAL CHARACTERISTICS: Output Spectrum

All specifications at T_A= +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, f_S= 48 kHz, SCKI = 512 f_S, 24-bit data, and Sampling

mode = Auto, unless otherwise noted.

OUTPUT SPECTRUM

(0 dB, N = 32768)

OUTPUT SPECTRUM

(–60 dB, N = 32768)

0

-20

0

-20

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

0

5

10

15

20

0

5

10

15

20

Frequency (kHz)

Figure 15.

Figure 16.

OUTPUT SPECTRUM

(BPZ, N = 32768)

0

-20

-40

-60

-80

-100

-120

-140

-160

0

5

10

15

20

Frequency (kHz)

Figure 17.

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PCM1789

SBAS451–OCTOBER 2008.............................................................................................................................................................................................. www.ti.com

PRODUCT OVERVIEW

The PCM1789 is a high-performance stereo DAC targeted for consumer audio applications such as Blu-ray Disc

players and DVD players, as well as home multi-channel audio applications (such as home theater and A/V

receivers). The PCM1789 consists of a two-channel DAC. The DAC output type is fixed with a differential

configuration. The PCM1789 supports 16-/20-/24-/32-bit linear PCM input data in I²S and left-justified audio

formats, and 24-bit linear PCM input data in right-justified and DSP formats with various sampling frequencies

from 8 kHz to 192 kHz. The PCM1789 offers three modes for device control: two-wire I²C software, three-wire

SPI software, and hardware.

ANALOG OUTPUTS

The PCM1789 includes a two-channel DAC, with a pair of differential voltage outputs pins. The full-scale output

voltage is (1.6 × VCC1) V_PPin differential output mode. A dc-coupled load is allowed in addition to an ac-coupled

load, if the load resistance conforms to the specification. These balanced outputs are each capable of driving 0.8

VCC1 (4 V_PP) typical into a 5-kΩ ac-coupled or 15-kΩ dc-coupled load with VCC1 = +5 V. The internal output

amplifiers for VOUTL and VOUTR are biased to the dc common voltage, equal to 0.5 VCC1.

The output amplifiers include an RC continuous-time filter that helps to reduce the out-of-band noise energy

present at the DAC outputs as a result of the noise shaping characteristics of the PCM1789 delta-sigma (ΔΣ)

DACs. The frequency response of this filter is shown in the Analog Filter Characteristic (Figure 10) of the Typical

Characteristics. By itself, this filter is not enough to attenuate the out-of-band noise to an acceptable level for

most applications. An external low-pass filter is required to provide sufficient out-of-band noise rejection. Further

discussion of DAC post-filter circuits is provided in the Application Information section.

VOLTAGE REFERENCE VCOM

The PCM1789 includes a pin for the common-mode voltage output, VCOM. This pin should be connected to the

analog ground via a decoupling capacitor. This pin can also be used to bias external high-impedance circuits, if

they are required.

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SYSTEM CLOCK INPUT

The PCM1789 requires an external system clock input applied at the SCKI input for DAC operation. The system

clock operates at an integer multiple of the sampling frequency, or f_S. The multiples supported in DAC operation

include 128 f_S, 192 f_S, 256 f_S, 384 f_S, 512 f_S, 768 f_S, and 1152 f_S. Details for these system clock multiples are

shown in Table 1. Figure 18 and Table 2 show the SCKI timing requirements.

Table 1. System Clock Frequencies for Common Audio Sampling Rates

DEFAULT

SAMPLING

MODE

SAMPLING

FREQUENCY, f_S

(kHz)

SYSTEM CLOCK FREQUENCY (MHz)

128 f_S

N/A

192 f_S

N/A

256 f_S

2.0480

4.0960

8.1920

11.2896

12.2880

22.5792

24.5760

N/A

384 f_S

3.0720

6.1440

12.2880

16.9344

18.4320

33.8688

36.8640

N/A

512 f_S

4.0960

8.1920

16.3840

22.5792

24.5760

N/A

768 f_S

6.1440

12.2880

24.5760

33.8688

36.8640

N/A

1152 f_S

9.2160

18.4320

36.8640

N/A

8

16

2.0480

4.0960

5.6448

6.1440

11.2896

12.2880

22.5792

24.5760

3.0720

6.1440

8.4672

9.2160

16.9344

18.4320

33.8688

36.8640

Single rate

32

44.1

48

N/A

88.2

96

N/A

Dual rate

Quad rate

N/A

176.4

192

N/A

t_SCH

High

Low

2.0 V

0.8 V

System Clock

(SCKI)

t_SCL

t_SCY

Figure 18. System Clock Timing Diagram

Table 2. Timing Requirements for Figure 18

SYMBOL

t_SCY

PARAMETER

MIN

27

MAX

UNIT

ns

System clock cycle time

System clock width high

System clock width low

System clock duty cycle

t_SCH

10

ns

t_SCL

10

ns

—

40

60

%

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SAMPLING MODE

The PCM1789 supports three sampling modes (single rate, dual rate, and quad rate) in DAC operation. In single

rate mode, the DAC operates at an oversampling frequency of x128 (except when SCKI = 128 f_Sand 192 f_S);

this mode is supported for sampling frequencies less than 50 kHz. In dual rate mode, the DAC operates at an

oversampling frequency of x64; this mode is supported for sampling frequencies less than 100 kHz. In quad rate

mode, the DAC operates at an oversampling frequency of x32. The sampling mode is automatically selected

according to the ratio of system clock frequency and sampling frequency by default (that is, single rate for 512 f_S,

768 f_S, and 1152 f_S; dual rate for 256 f_Sand 384 f_S; and quad rate for 128 f_Sand 192 f_S), but manual selection is

also possible for specified combinations through the serial mode control register.

Table 3 and Figure 19 show the relationship among the oversampling rate (OSR) of the digital filter and ΔΣ

modulator, the noise-free shaped bandwidth, and each sampling mode setting.

Table 3. Digital Filter OSR, Modulator OSR, and Noise-Free Shaped Bandwidth for Each Sampling Mode

SAMPLING

MODE

REGISTER

SETTING

NOISE-FREE SHAPED BANDWIDTH⁽¹⁾

(kHz)

SYSTEM CLOCK

FREQUENCY

(xf_S)

DIGITAL FILTER

OSR

MODULATOR

OSR

f_S= 48 kHz

f_S= 96 kHz

f_S= 192 kHz

512, 768, 1152

256, 384

128, 192⁽²⁾

512, 768, 1152

256, 384

40

20

10

40

20

10

N/A

40

N/A

40

×8

x8

x4

x8

x4

x8

x4

x128

x64

Auto

20

x32

N/A

40

N/A

40

x128

x64

Single

128, 192⁽²⁾

256, 384

x64

Dual

128, 192⁽²⁾

40

x64

Quad

20

x32

(1) Bandwidth in which noise is shaped out.

(2) Quad mode filter characteristic is applied.

0

DSM_Single

DF_Single

-20

-40

DSM_Dual

DSM_Quad

DF_Dual

DF_Quad

-60

-80

-100

-120

-140

-160

-180

-200

0

0.5

1.0

1.5

2.0

Normalized Frequency (f_S)

Figure 19. ΔΣ Modulator and Digital Filter Characteristic

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RESET OPERATION

The PCM1789 has both an internal power-on reset circuit and an external reset circuit. The sequences for both

reset circuits are shown in Figure 20 and Figure 21. Figure 20 illustrates the timing at the internal power-on reset.

Initialization is triggered automatically at the point where VDD exceeds 2.2 V typical, and the internal reset is

released after 3846 SCKI clock cycles from power-on, if RST is held high and SCKI is provided. VOUTx from the

DAC is forced to the VCOM level initially (that is, 0.5 × VCC1) and settles at a specified level according to the

rising VCC. If synchronization among SCKI, BCK, and LRCK is maintained, VOUT provides an output that

corresponds to DIN after 3846 SCKI clocks from power-on. If the synchronization is not held, the internal reset is

not released, and both operating modes are maintained at reset and power-down states. After synchronization

forms again, the DAC returns to normal operation with the previous sequences.

Figure 21 illustrates a timing diagram at the external reset. RST accepts an externally-forced reset with RST low,

and provides a device reset and power-down state that achieves the lowest power dissipation state available in

the PCM1789. If RST goes from high to low under synchronization among SCKI, BCK, and LRCK, the internal

reset is asserted, all registers and memory are reset, and finally, the PCM1789 enters into all power-down states.

At the same time, VOUT is immediately forced into the AGND1 level. To begin normal operation again, toggle

RST high; the same power-up sequence is performed as the power-on reset shown in Figure 20.

The PCM1789 does not require particular power-on sequences for VCC and VDD; it allows VDD on and then

VCC on, or VCC on and then VDD on. From the viewpoint of the Absolute Maximum Ratings, however,

simultaneous power-on is recommended for avoiding unexpected responses on VOUTx. Figure 20 illustrates the

response for VCC on with VDD on.

(VDD = 3.3 V, typ)

VDD

(VDD = 2.2 V, typ)

0 V

SCKI,

BCK,

LRCK

Synchronous Clocks

RST

3846 ´ SCKI

Normal Operation

Internal Reset

0.5 ´ VCC

VOUTx±

VCOM

(0.5 ´ VCC1)

Figure 20. Power-On-Reset Timing Requirements

(VDD = 3.3 V, typ)

VDD

0 V

SCKI,

BCK,

LRCK

Synchronous Clocks

100 ns (min)

Power-Down

RST

3846 ´ SCKI

Normal Operation

Internal Reset

0.5 ´ VCC

VOUTx±

Figure 21. External Reset Timing Requirements

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AUDIO SERIAL PORT OPERATION

The PCM1789 audio serial port consists of three signals: BCK, LRCK, and DIN. BCK is a bit clock input. LRCK is

a left/right word clock or frame synchronization clock input. DIN is the audio data input for VOUTL/R.

AUDIO DATA INTERFACE FORMATS AND TIMING

The PCM1789 supports six audio data interface formats: 16-/20-/24-/32-bit I²S, 16-/20-/24-/32-bit left-justified,

24-bit right-justified, 16-bit right-justified, 24-bit left-justified mode DSP, and 24-bit I²S mode DSP. In the case of

I²S, left-justified, and right-justified data formats, 64 BCKs, 48 BCKs, and 32 BCKs per LRCK period are

supported; however, 48 BCKs are limited to 192/384/768 f_SSCKI, and 32 BCKs are limited to 16-bit right-justified

only. The audio data formats are selected by MC/SCL/FMT in hardware control mode and by the FMTDA[2:0]

bits in control register 17 (11h) in software control mode. All data must be in binary twos complement and MSB

first.

Table 4 summarizes the applicable formats and describes the relationships among them and the respective

restrictions with mode control. Figure 22 through Figure 26 show six audio interface data formats.

Table 4. Audio Data Interface Formats and Sampling Rate, Bit Clock, and System Clock Restrictions

MAX LRCK FREQUENCY

CONTROL MODE

Software control

Hardware control

FORMAT

I²S/Left-Justified

Right-Justified

DATA BITS

16/20/24/32⁽¹⁾

24, 16

(f_S)

SCKI RATE (xf_S)

128 to 1152⁽²⁾

128 to 768

BCK RATE (xf_S)

192 kHz

64, 48

64, 48, 32 (16 bit)⁽³⁾

64

I²S/Left-Justified DSP

I²S/Left-Justified

24

16/20/24/32⁽¹⁾

128 to 1152⁽²⁾

64, 48

(1) 32-bit data length is acceptable only for BCK = 64 f_Sand when using I²S or Left-Justified format.

(2) 1152 f_Sis acceptable only for f_S= 32 kHz, BCK = 64 f_S, and when using I²S, Left-Justified, or 24-bit Right-Justified format.

(3) BCK = 32 f_Sis supported only for 16-bit data length.

Right Channel

LRCK

BCK

DIN

Left Channel

N

M

L

2

1

0

N

M

L

2

1

0

LSB

MSB

LSB

Figure 22. Audio Data Format: 16-/20-/24-/32-Bit I²S

(N = 15/19/23/31, M = 14/18/22/30, and L = 13/17/21/29)

Right Channel

Left Channel

LRCK

BCK

DIN

N

M

L

2

1

0

N

M

L

2

1

0

N

LSB

MSB

Figure 23. Audio Data Format: 16-/20-/24-/32-Bit Left-Justified

(N = 15/19/23/31, M = 14/18/22/30, and L = 13/17/21/29)

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Right Channel

LRCK

BCK

DIN

Left Channel

23 22 21

MSB

2

1

0

23 22 21

MSB

2

1

0

LSB

Figure 24. Audio Data Format: 24-Bit Right-Justified

Right Channel

Left Channel

LRCK

BCK

DIN

0

15

14

13

2

1

0

15

14

13

2

1

0

MSB

LSB

MSB

LSB

Figure 25. Audio Data Format: 16-Bit Right-Justified

1/f_S(64 BCKs)

Left Channel

Right Channel

LRCK

BCK

Left-Justified Mode

DIN

23 22 21

2

1

2

0

1

23 22 21

2

1

2

0

1

23 22 21

I²S Mode

DIN

23 22 21

0

23 22 21

0

23 22

Figure 26. Audio Data Format: 24-Bit DSP Format

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AUDIO INTERFACE TIMING

Figure 27 and Table 5 describe the detailed audio interface timing specifications.

t_BCH

t_BCL

BCK

(Input)

1.4 V

t_BCY

t_LRS

t_LRH

LRCK

(Input)

t_LRW

t_DIS

t_DIH

DIN

(Input)

1.4 V

Figure 27. Audio Interface Timing Diagram for Left-Justified, Right-Justified, I²S, and DSP Data Formats

Table 5. Timing Requirements for Figure 27

SYMBOL

t_BCY

DESCRIPTION

MIN

75

TYP

MAX

UNIT

ns

BCK cycle time

t_BCH

BCK pulse width high

BCK pulse width low

35

ns

t_BCL

35

ns

LRCK pulse width high (LJ, RJ and I²S formats)

LRCK pulse width high (DSP format)

LRCK setup time to BCK rising edge

LRCK hold time to BCK rising edge

DIN setup time to BCK rising edge

DIN hold time to BCK rising edge

1/(2 × f_S)

t_BCY

10

1/(2 × f_S)

t_BCY

sec

ns

t_LRW

t_LRS

t_LRH

t_DIS

t_DIH

10

ns

10

ns

10

ns

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SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM

The PCM1789 operates under the system clock (SCKI) and the audio sampling rate (LRCK). Therefore, SCKI

and LRCK must have a specific relationship. The PCM1789 does not need a specific phase relationship between

the audio interface clocks (LRCK, BCK) and the system clock (SCKI), but does require a specific frequency

relationship (ratiometric) between LRCK, BCK, and SCKI.

If the relationship between SCKI and LRCK changes more than ±2 BCK clocks because of jitter, sampling

frequency change, etc., the DAC internal operation stops within 1/f_S, and the analog output is forced into VCOM

(0.5 VCC1) until re-synchronization among SCKI, LRCK, and BCK completes, and then either 38/f_S(single, dual

rate) or 29/f_S(quad rate) passes. In the event the change is less than ±2 BCKs, re-synchronization does not

occur, and this analog output control and discontinuity does not occur.

Figure 28 shows the DAC analog output during loss of synchronization. During undefined data periods, some

noise may be generated in the audio signal. Also, the transition of normal to undefined data and undefined (or

zero) data to normal data creates a discontinuity of data on the analog outputs, which may then generate some

noise in the audio signal.

The DAC outputs (VOUTx) hold the previous state if the system clock halts, but the asynchronous and

re-synchronization processes will occur after the system clock resumes.

State of

Synchronization

Synchronous

Within 1/f_S

Asynchronous

Synchronous

38/f_S(single, dual rate)

29/f_S(quad rate)

Undefined Data

Normal

VCOM

(0.5 VCC1)

DAC

VOUTx±

Normal

Figure 28. DAC Outputs During Loss of Synchronization

ZERO FLAG

The PCM1789 has two ZERO flag pins (ZERO1 and ZERO2) that can be assigned to the combinations shown in

Table 6. Zero flag combinations are selected through the AZRO bit in control register 22 (16h). If the input data

of all the assigned channels remain at '0' for 1024 sampling periods (LRCK clock periods), the ZERO1/2 bits are

set to a high level, logic '1' state. Furthermore, if the input data of any of the assigned channels read '1', the

ZERO1/2 are set to a low level, logic '0' state, immediately. Zero data detection is supported for 16-/20-/24-bit

data width, but is not supported for 32-bit data width.

The active polarity of the zero flag output can be inverted through the ZREV bit in control register 22 (16h). The

reset default is active high for zero detection.

In parallel hardware control mode, ZERO1 and ZERO2 are fixed with combination A, shown in Table 6.

Table 6. Zero Flag Outputs Combination

ZERO FLAG COMBINATION

ZERO1

Left channel

ZERO2

A

B

Right channel

Left channel or right channel

Left channel and right channel

Note that the ZERO2 pin is multiplexed with AMUTEO pin. Selection of ZERO2 or AMUTEO can be changed

through the MZSEL bit in control register 22 (16h). The default setting after reset is the selection of ZERO2.

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AMUTE CONTROL

The PCM1789 has an AMUTE control input, status output pins, and functionality. AMUTEI is the input control pin

of the internal analog mute circuit. An AMUTEI low input causes the DAC output to cut-off from the digital input

and forces it to the center level (0.5 VCC1). AMUTEO is the status output pin of the internal analog mute circuit.

AMUTEO low indicates the analog mute control circuit is active because of a programmed condition (such as an

SCKI halt, asynchronous detect, zero detect, or by the DAC disable command) that forces the DAC outputs to a

center level. Because AMUTEI is not terminated internally and AMUTEO is an open-drain output, pull-ups by the

appropriate resistors are required for proper operation.

Note that the AMUTEO pin is multiplexed with the ZERO2 pin. The desired pin is selected through the MZSEL bit

in control register 22 (16h). The default setting is the selection of the ZERO2 pin.

Additionally, because the AMUTEI pin control and power-down control in register (OPEDA when high, PSMDA

when low) do not function together, AMUTEI takes priority over power-down control. Therefore, power-down

control is ignored during AMUTEI low, and AMUTEI low forces the DAC output to a center level (0.5 VCC1) even

if power-down control is asserted.

MODE CONTROL

The PCM1789 includes three mode control interfaces with three oversampling configurations, depending on the

input state of the MODE pin, as shown in Table 7. The pull-up and pull-down resistors must be 220 kΩ ±5%.

Table 7. Interface Mode Control Selection

MODE

Tied to DGND

MODE CONTROL INTERFACE

Two-wire (I²C) serial control, selectable oversampling configuration

Pull-down resistor to DGND

Pull-up resistor to VDD

Tied to VDD

Two-wire parallel control, auto mode oversampling configuration

Three-wire (SPI) serial control, selectable oversampling configuration, ADR6 = '0'

Three-wire (SPI) serial control, selectable oversampling configuration, ADR6 = '1'

The input state of the MODE pin is sampled at the moment of power-on, or during a low-to-high transition of the

RST pin, with the system clock input. Therefore, input changes after reset are ignored until the next power-on or

reset. From the mode control selection described in Table 7, the functions of four pins are changed, as shown in

Table 8.

Table 8. Pin Functions for Interface Mode

PIN ASSIGNMENTS

21

22

23

24

SPI

I²C

H/W

MD (input)

MC (input)

MS (input)

ADR5 (input)

SDA (input/output)

SCL (input)

DEMP (input)

FMT (input)

ADR0 (input)

ADR1 (input)

RSV (input, low)

In serial mode control, the actual mode control is performed by register writes (and reads) through the SPI- or

I²C-compatible serial control port. In parallel mode control, two specific functions are controlled directly through

the high/low control of two specific pins, as described in the following section.

PARALLEL HARDWARE CONTROL

The functions shown in Table 9 and Table 10 are controlled by two pins, DEMP and FMT, in parallel hardware

control mode. The DEMP pin controls the 44.1-kHz digital de-emphasis function of both channels. The FMT pin

controls the audio interface format for both channels.

Table 9. DEMP Functionality

DEMP

Low

DESCRIPTION

De-emphasis off

High

44.1 kHz de-emphasis on

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Table 10. FMT Functionality

FMT

Low

High

DESCRIPTION

16-/20-/24-/32-bit I²S format

16-/20-/24-/32-bit left-justified format

THREE-WIRE (SPI) SERIAL CONTROL

The PCM1789 includes an SPI-compatible serial port that operates asynchronously with the audio serial

interface. The control interface consists of MD/SDA/DEMP, MC/SCL/FMT, and MS/ADR0/RSV. MD is the serial

data input used to program the mode control registers. MC is the serial bit clock that shifts the data into the

control port. MS is the select input used to enable the mode control port.

CONTROL DATA WORD FORMAT

All single write operations via the serial control port use 16-bit data words. Figure 29 shows the control data word

format. The first bit (fixed at '0') is for write operation. After the first bit are seven other bits, labeled ADR[6:0],

that set the register address for the write operation. ADR6 is determined by the status of the MODE pin. ADR5 is

determined by the state of the ADR5/ADR1/RSV pin. A maximum of four PCM1789s can be connected on the

same bus at any one time. Each PCM1789 responds when receiving its own register address. The eight least

significant bits (LSBs), D[7:0] on MD, contain the data to be written to the register address specified by ADR[6:0].

MSB

0

LSB

D0

ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

D7

D6

D5

D4

D3

D2

D1

Register Address

Register Data

Figure 29. Control Data Word Format for MD

REGISTER WRITE OPERATION

Figure 30 shows the functional timing diagram for single write operations on the serial control port. MS is held at

a high state until a register is to be written to. To start the register write cycle, MS is set to a low state. 16 clocks

are then provided on MC, corresponding to the 16 bits of the control data word on MD. After the 16th clock cycle

has been completed, MS is set high to latch the data into the indexed mode control register.

In addition to single write operations, the PCM1789 also supports multiple write operations, which can be

performed by sending the N-bytes (where N ≤ 9) of the 8-bit register data that follow after the first 16-bit register

address and register data, while keeping the MC clocks and MS at a low state. Ending a multiple write operation

can be accomplished by setting MS to a high state.

MS

MC

X⁽¹⁾

'0' ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 D7

D6

D5

D4

D3

D2

D1

D0

X

ADR6

MD

0

(1) X = don't care.

Figure 30. Register Write Operation

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TIMING REQUIREMENTS

Figure 31 shows a detailed timing diagram for the three-wire serial control interface. These timing parameters are

critical for proper control port operation.

t_MHH

MS

MC

1.4 V

t_MCH

t_MCL

t_MSH

t_MSS

t_MCY

t_MDS

t_MDH

D7

LSB (D0)

ADR0

MSB (R/W)

MD

1.4 V

Figure 31. Three-Wire Serial Control Interface Timing

Table 11. Timing Requirements for Figure 31

SYMBOL

t_MCY

PARAMETER

MIN

100

40

MAX

UNIT

ns

MC pulse cycle time

MC low-level time

MC high-level time

MS high-level time

t_MCL

t_MCH

t_MHH

t_MSS

t_MSH

t_MDH

t_MDS

ns

40

ns

t_MCY

30

ns

MS falling edge to MC rising edge

MS rising edge from MC rising edge for LSB

MD hold time

ns

15

ns

15

ns

MD setup time

15

ns

TWO-WIRE (I²C) SERIAL CONTROL

The PCM1789 supports an I²C-compatible serial bus and data transmission protocol for fast mode configured as

a slave device. This protocol is explained in the I²C specification 2.0.

The PCM1789 has a 7-bit slave address, as shown in Figure 32. The first five bits are the most significant bits

(MSBs) of the slave address and are factory-preset to '10011'. The next two bits of the address byte are

selectable bits that can be set by MS/ADR0/RSV and ADR5/ADR1/RSV. A maximum of four PCM1789s can be

connected on the same bus at any one time. Each PCM1789 responds when it receives its own slave address.

MSB

1

LSB

R/W

0

1

ADR1

ADR0

Figure 32. Slave Address

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PACKET PROTOCOL

A master device must control the packet protocol, which consists of a start condition, a slave address with the

read/write bit, data if a write operation is required, an acknowledgment if a read operation is required, and a stop

condition. The PCM1789 supports both slave receiver and transmitter functions. Details about DATA for both

write and read operations are described in Figure 33.

SDA

SCL

1 to 7

8

9

1 to 8

DATA⁽³⁾

9

1 to 8

DATA

9

St

Sp

Slave Address

R/W⁽¹⁾

ACK⁽²⁾

ACK

Start

Condition

Stop

Condition

(1) R/W: Read operation if '1'; write operation otherwise.

(2) ACK: Acknowledgment of a byte if '0', not Acknowledgment of a byte if '1'.

(3) DATA: Eight bits (byte); details are described in the Write Operation and Read Operation sections.

Figure 33. I²C Packet Control Protocol

WRITE OPERATION

The PCM1789 supports a receiver function. A master device can write to any PCM1789 register using single or

multiple accesses. The master sends a PCM1789 slave address with a write bit, a register address, and the

data. If multiple access is required, the address is that of the starting register, followed by the data to be

transferred. When valid data are received, the index register automatically increments by one. When the register

address reaches &h4F, the next value is &h40. When undefined registers are accessed, the PCM1789 does not

send an acknowledgment. Figure 34 illustrates a diagram of the write operation. The register address and write

data are in 8-bit, MSB-first format.

Transmitter

Data Type

M

S

M

S

M

S

M

S

M

Reg Address

Sp

St

Slave Address

ACK

Write Data 1

ACK

Write Data 2

ACK

W

NOTE: M = Master device, S = Slave device, St = Start condition, W = Write, ACK = Acknowledge, and Sp = Stop condition.

Figure 34. Framework for Write Operation

READ OPERATION

A master device can read the registers of the PCM1789. The value of the register address is stored in an indirect

index register in advance. The master sends the PCM1789 slave address with a read bit after storing the register

address. Then the PCM1789 transfers the data that the index register points to. Figure 35 shows a diagram of

the read operation.

Transmitter

Data Type

M

S

M

S

M

R

S

M

St

Slave Address

ACK

Sr

Slave Address⁽¹⁾

ACK

Read Data

NACK

Reg Address

Sp

W

(1) The slave address after the repeated start condition must be the same as the previous slave address.

NOTE: M = Master device, S = Slave device, St = Start condition, Sr = Repeated start condition, W = Write, R = Read, ACK = Acknowledge,

NACK = Not acknowledge, and Sp = Stop condition.

Figure 35. Framework for Read Operation

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TIMING REQUIREMENTS: SCL AND SDA

A detailed timing diagram for SCL and SDA is shown in Figure 36.

Repeated

START

STOP

START

t_D-HD

t_SDA-R

t_BUF

t_D-SU

t_P-SU

SDA

SCL

t_SDA-F

t_SCL-R

t_LOW

t_S-HD

t_SCL-F

t_S-HD

t_S-SU

t_HI

Figure 36. SCL and SDA Control Interface Timing

Table 12. Timing Requirements for Figure 36

STANDARD MODE

FAST MODE

SYMBOL

f_SCL

PARAMETER

MIN

MAX

MIN

MAX

UNIT

kHz

µs

SCL clock frequency

100

400

t_BUF

Bus free time between STOP and START condition

Low period of the SCL clock

High period of the SCL clock

Setup time for START/Repeated START condition

Hold time for START/Repeated START condition

Data setup time

4.7

4.0

4.7

4.0

250

0

1.3

t_LOW

t_HI

1.3

0.6

µs

t_S-SU

t_S-HD

t_D-SU

t_D-HD

t_SCL-R

t_SCL-F

t_SDA-R

t_SDA-F

t_P-SU

t_GW

0.6

µs

0.6

µs

100

ns

Data hold time

3450

1000

0

900

300

ns

Rise time of SCL signal

20 + 0.1 C_B

0.6

ns

Fall time of SCL signal

ns

Rise time of SDA signal

ns

Fall time of SDA signal

ns

Setup time for STOP condition

Allowable glitch width

4.0

µs

N/A

400

50

ns

C_B

Capacitive load for SDA and SCL line

100

pF

Noise margin at high level for each connected device

(including hysteresis)

V_NH

0.2 × VDD

V

Noise margin at low level for each connected device

(including hysteresis)

V_NL

0.1 × VDD

N/A

0.1 × VDD

V

V_HYS

Hysteresis of Schmitt trigger input

0.05 × VDD

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CONTROL REGISTER DEFINITIONS (SOFTWARE MODE ONLY)

The PCM1789 has many user-programmable functions that are accessed via control registers, and are

programmed through the SPI or I²C serial control port. Table 13 shows the available mode control functions

along with reset default conditions and associated register addresses. Table 14 lists the register map.

Table 13. User-Programmable Mode Control Functions

FUNCTION

RESET DEFAULT

Normal operation

Mute disabled

Auto

REGISTER⁽¹⁾

LABEL

MRST

Mode control register reset

System reset

16

17

18

19

20

21

22

SRST

Analog mute function control

Sampling mode selection

Power-save mode selection

AMUTE[3:0]

SRDA[1:0]

PSMDA

Power save

Audio interface format selection

Operation control

I²S

FMTDA[2:0]

OPEDA

Normal operation

Sharp roll-off

Digital filter roll-off control

Output phase selection

Soft mute control

FLT

Normal

REVDA[2:1]

MUTDA[2:1]

ZERO[2:1]

DAMS

Mute disabled

Not detected

Zero flag

Digital attenuation mode

Digital de-emphasis function control

AMUTEO/ZERO flag selection

0 dB to –63 dB, 0.5-dB step

Disabled

DEMP[1:0]

MZSEL

ZERO2

ZERO1: left-channel

ZERO2: right-channel

High for detection

0 dB, no attenuation

Zero flag function selection

22

AZRO

Zero flag polarity selection

22

ZREV

Digital attenuation level setting

24, 25

ATDAx[7:0]

(1) If ADR6 or ADR5 is high, the register address must be changed to the number shown + offset; offset is 32, 64 and 96 according to state

of ADR6, 5 (01, 10 and 11).

Table 14. Register Map

ADR[6:0]⁽¹⁾

DEC

DATA[7:0]

HEX

10

11

12

13

14

15

16

17

18

19

B7

B6

B5

B4

B3

B2

B1

B0

16

17

18

19

20

21

22

23

24

25

MRST

SRST

AMUTE3

RSV⁽²⁾

DEMP1

RSV⁽²⁾

ATDA15

ATDA25

AMUTE2

RSV⁽²⁾

AMUTE1

RSV⁽²⁾

MZSEL

RSV⁽²⁾

ATDA13

ATDA23

AMUTE0

FMTDA2

RSV⁽²⁾

ATDA12

ATDA22

SRDA1

FMTDA1

RSV⁽²⁾

SRDA0

FMTDA0

FLT

PSMDA

RSV⁽²⁾

DAMS

RSV⁽²⁾

ATDA17

ATDA27

RSV⁽²⁾

ATDA16

ATDA26

OPEDA

RSV⁽²⁾

REVDA2

MUTDA2

ZERO2

AZRO

REVDA1

MUTDA1

ZERO1

ZREV

RSV⁽²⁾

ATDA10

ATDA20

RSV⁽²⁾

DEMP0

RSV⁽²⁾

ATDA14

ATDA24

ATDA11

ATDA21

(1) If ADR6 or ADR5 is high, the register address must be changed to the number shown + offset; offset is 32, 64 and 96 according to state

of ADR6, 5 (01, 10 and 11).

(2) RSV must be set to '0'.

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REGISTER DEFINITIONS

DEC

HEX

B7

B6

B5

B4

B3

B2

B1

B0

16

10

MRST

SRST

AMUTE3

AMUTE2

AMUTE1

AMUTE0

SRDA1

SRDA0

MRST

Mode control register reset

This bit sets the mode control register reset to the default value. Pop noise may be generated.

Returning the MRST bit to '1' is unnecessary because it is automatically set to '1' after the mode

control register is reset.

Default value = 1.

MRST

Mode control register reset

Set default value

0

1

Normal operation (default)

SRST

System reset

This bit controls the system reset, which includes the resynchronization between the system

clock and sampling clock, and DAC operation restart. The mode control register is not reset and

the PCM1789 does not go into a power-down state. Returning the SRST bit to '1' is unnecessary;

it is automatically set to '1' after triggering a system reset.

Default value = 1.

SRST

System reset

0

1

Resynchronization

Normal operation (default)

AMUTE[3:0] Analog mute function control

These bits control the enabling/disabling of each source event that triggers the analog mute

control circuit.

Default value = 0000.

AMUTE

xxx0

xxx1

xx0x

xx1x

x0xx

x1xx

0xxx

1xxx

Analog mute function control

Disable analog mute control by SCKI halt

Enable analog mute control by SCKI halt

Disable analog mute control by asynchronous detect

Enable analog mute control by asynchronous detect

Disable analog mute control by ZERO1 and ZERO2 detect

Enable analog mute control by ZERO1 and ZERO2 detect

Disable analog mute control by DAC disable command

Enable analog mute control by DAC disable command

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SRDA[1:0] Sampling mode selection

These bits control the sampling mode of DAC operation. In Auto mode, the sampling mode is

automatically set according to multiples between the system clock and sampling clock: single rate

for 512 f_S, 768 f_S, and 1152 f_S, dual rate for 256 f_Sor 384 f_S, and quad rate for 128 f_Sand 192 f_S.

Default value = 00.

SRDA

00

Sampling mode selection

Auto (default)

Single rate

01

10

Dual rate

11

Quad rate

DEC

17

HEX

11

B7

B6

B5

B4

B3

B2

B1

B0

PSMDA

RSV

FMTDA2

FMTDA1

FMTDA0

PSMDA

Power-save mode selection

This bit selects the power-save mode for the OPEDA function. When PSMDA = 0, OPEDA

controls the power-save mode and normal operation. When PSMDA = 1, OPEDA functions

controls the DAC disable (not power-save mode) and normal operation.

Default value: 0.

PSMDA

Power-save mode selection

Power-save enable mode (default)

Power-save disable mode

0

1

RSV

Reserved

Reserved; do not use.

FMTDA[2:0] Audio interface format selection

These bits control the audio interface format for DAC operation. Details of the format and any

related restrictions with the system clock are described in the Audio Data Interface Formats and

Timing section.

Default value: 0000 (16-/20-/24-/32-bit I²S format).

FMTDA

000

Audio interface format selection

16-/20-/24-/32-bit I²S format (default)

16-/20-/24-/32-bit left-justified format

24-bit right-justified format

16-bit right-justified format

24-bit I²S mode DSP format

24-bit left-justified mode DSP format

Reserved

001

010

011

100

101

110

111

Reserved

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DEC

18

HEX

12

B7

B6

B5

B4

B3

B2

B1

B0

RSV

OPEDA

RSV

FLT

RSV

Reserved

Reserved; do not use.

OPEDA

Operation control

This bit controls the DAC operation mode. In operation disable mode, the DAC output is cut off

from DIN and the internal DAC data are reset. If PSMDA = 1, the DAC output is forced into

VCOM. If PSMDA = 0, the DAC output is forced into AGND and the DAC goes into a

power-down state. For normal operating mode, this bit must be '0'. The serial mode control is

effective during operation disable mode.

Default value: 0.

OPEDA

Operation control

0

1

Normal operation

Operation disable with or without power save

FLT

Digital filter roll-off control

This bit allows users to select the digital filter roll-off that is best suited to their applications. Sharp

and slow filter roll-off selections are available. The filter responses for these selections are shown

in the Typical Characteristics sections of this data sheet.

Default value: 0.

FLT

0

Digital filter roll-off control

Sharp roll-off

1

Slow roll-off

DEC

19

HEX

13

B7

B6

B5

B4

B3

B2

B1

B0

RSV

REVDA2

REVDA1

RSV

Reserved

Reserved; do not use.

REVDA[2:1] Output phase selection

These bits are used to control the phase of the DAC analog signal outputs.

Default value: 00.

REVDA

x0

Output phase selection

Left channel normal output

Left channel inverted output

Right channel normal output

Right channel inverted output

x1

0x

1x

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DEC

20

HEX

14

B7

B6

B5

B4

B3

B2

B1

B0

RSV

MUTDA2

MUTDA1

RSV

Reserved

Reserved; do not use.

MUTDA[2:1] Soft Mute control

These bits are used to enable or disable the Soft Mute function for the corresponding DAC

outputs, VOUTx. The Soft Mute function is incorporated into the digital attenuators. When mute is

disabled (MUTDA[2:1] = 0), the attenuator and DAC operate normally. When mute is enabled by

setting MUTDA[2:1] = 1, the digital attenuator for the corresponding output is decreased from the

current setting to infinite attenuation. By setting MUTDA[2:1] = 0, the attenuator is increased to

the last attenuation level in the same manner as it is for decreasing levels. This configuration

reduces pop and zipper noise during muting of the DAC output. This Soft Mute control uses the

same resource of digital attenuation level setting. Mute control has priority over the digital

attenuation level setting.

Default value: 00.

MUTDA

Soft Mute control

x0

x1

0x

1x

Left channel mute disabled

Left channel mute enabled

Right channel mute disabled

Right channel mute enabled

DEC

21

HEX

B7

B6

B5

B4

B3

B2

B1

B0

15

RSV

ZERO2

ZERO1

RSV

Reserved

Reserved; do not use.

ZERO[2:1]

Zero flag (read-only)

These bits indicate the present status of the zero detect circuit for each DAC channel; these bits

are read-only.

ZERO

x0

Zero flag

Left channel zero input not detected

Left channel zero input detected

Right channel zero input not detected

Right channel zero input detected

x1

0x

1x

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DEC

22

HEX

16

B7

B6

B5

B4

B3

B2

B1

B0

DAMS

RSV

DEMP1

DEMP0

MZSEL

RSV

AZRO

ZREV

DAMS

Digital attenuation mode

This bit selects the attenuation mode.

Default value: 0.

DAMS

Digital attenuation mode

0

1

Fine step: 0.5-dB step for 0 dB to –63 dB range (default)

Wide range: 1-dB step for 0 dB to –100 dB range

RSV

Reserved

Reserved; do not use.

DEMP[1:0] Digital de-emphasis function/sampling rate control

These bits are used to disable and enable the various sampling frequencies of the digital

de-emphasis function.

Default value: 00.

DEMP

00

Digital de-emphasis function/sampling rate control

Disable (default)

48 kHz enable

44.1 kHz enable

32 kHz enable

01

10

11

MZSEL

AMUTEO/ZERO flag selection

This bit is used to select the function of the ZERO2 pin.

Default value: 0.

MZSEL

AMUTEO/ZERO flag selection

0

1

The ZERO2 pin functions as ZERO2 (default).

The ZERO2 pin functions as AMUTEO.

AZRO

Zero flag channel combination selection

This bit is used to select the zero flag channel combination for ZERO1 and ZERO2.

Default value: 0.

AZRO

Zero flag combination selection

0

1

Combination A: ZERO1 = left channel, ZERO2 = right channel (default)

Combination B: ZERO1 = left channel or right channel, ZERO2 = left channel and

right channel

ZREV

Zero flag polarity selection

This bit controls the polarity of the zero flag pin.

Default value: 0.

ZREV

Zero flag polarity selection

High for zero detect (default)

Low for zero detect

0

1

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DEC

HEX

B7

B6

B5

B4

B3

B2

B1

B0

23

24

25

17

18

19

RSV

ATDA17

ATDA27

ATDA16

ATDA26

ATDA15

ATDA25

ATDA14

ATDA24

ATDA13

ATDA23

ATDA12

ATDA22

ATDA11

ATDA21

ATDA10

ATDA20

RSV

Reserved

Reserved; do not use.

ATDAx[7:0] Digital attenuation level setting

Where x = 1 to 2, corresponding to the DAC output (VOUTx).

Both DAC outputs (VOUTL and VOUTR) have a digital attenuation function. The attenuation level

can be set from 0 dB to R dB, in S-dB steps. Changes in attenuator levels are made by

incrementing or decrementing one step (S dB) for every 8/f_Stime interval until the programmed

attenuator setting is reached. Alternatively, the attenuation level can be set to infinite attenuation

(or mute). R (range) and S (step) is –63 and 0.5 for DAMS = 0, and –100 and 1.0 for DAMS = 1,

respectively. The DAMS bit is defined in register 22 (16h). Table 15 shows attenuation levels for

various settings.

The attenuation level for each channel can be set individually using the following formula:

Attenuation level (dB) = S × (ATDAx[7:0]_DEC– 255)

where ATDAx[7:0]_DEC= 0 through 255.

For ATDAx[7:0]_DEC= 0 through 128 with DAMS = 0, or 0 through 154 with DAMS = 1, attenuation

is set to infinite attenuation (mute).

Default value: 1111 1111.

Table 15. Attenuation Levels for Various Settings

ATDAx[7:0]

ATTENUATION LEVEL SETTING

BINARY

1111 1111

1111 1110

1111 1101

...

DECIMAL

255

254

253

...

DAMS = 0

DAMS = 1

0 dB, no attenuation (default)

–0.5 dB

–1.0 dB

...

–1 dB

–2 dB

...

1001 1100

1001 1011

1001 1010

...

156

155

154

...

–45.9 dB

–50.0 dB

–50.5 dB

...

–99 dB

–100 dB

Mute

...

1000 0010

1000 0001

0000 0000

...

130

129

128

...

–62.5 dB

–63.0 dB

Mute

...

0000 0000

0

Mute

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APPLICATION INFORMATION

CONNECTION DIAGRAMS

A basic connection diagram is shown in Figure 37, with the necessary power-supply bypassing and decoupling

components. Texas Instruments’ PLL170X is used to generate the system clock input at SCKI, as well as to

generate the clock for the audio signal processor. The use of series resistors (22 Ω to 100 Ω) are recommended

for SCKI, LRCK, BCK, and DIN for electromagnetic interference (EMI) reduction.

R₁

ADR5/ADR1/RSV

MS/ADR0/RSV

MC/SCL/FMT

MD/SDA/DEMP

MODE

1

2

3

4

5

6

7

8

9

LRCK

BCK

24

23

22

21

20

19

18

17

16

15

14

13

R₂

Audio DSP

or

Decoder

R₃

DIN

Microcontroller

or

Microprocessor

RST

See Termination

Circuit Options Below

SCKI

VDD

PLL170x

PCM1789

ZERO1

ZERO2/AMUTEO

AMUTEI

C₁

DGND

VCC1

VCOM

R₅

C₂

VCC2

+

C₄

C₃

AGND2

10 AGND1

11 VOUTL-

12 VOUTL+

VOUTR-

VOUTR+

+3.3 V

+5 V

0 V

+

C₆

+

C₅

LPF and Buffer

Termination Circuit Options (select one)

20

3.3 V

20

3.3 V

R₆

20

0 V

NOTE: C₁through C₃are 1-µF ceramic capacitors. C₄through C₆are 10-µF electrolytic capacitors. R₁through R₄are 22-Ω to 100-Ω

resistors. R₅is a resistor appropriate for pull-up. R₆is a 220-kΩ resistor, ±5%. An appropriate resistor is required for pull-up, if

ZERO2/AMUTEO pin is used as AMUTEO.

Figure 37. Basic Connection Diagram

POWER SUPPLY AND GROUNDING

The PCM1789 requires +5 V for the analog supply and +3.3 V for the digital supply. The +5-V supply is used to

power the DAC analog and output filter circuitry, and the +3.3-V supply is used to power the digital filter and

serial interface circuitry. For best performance, it is recommended to use a linear regulator (such as the

REG101-5/33, REG102-5/33, or REG103-5/33) with the +5-V and +3.3-V supplies.

Five capacitors are required for supply bypassing, as shown in Figure 37. These capacitors should be located as

close as possible to the PCM1789 package. The 10-µF capacitors are aluminum electrolytic, while the three 1-µF

capacitors are ceramic.

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LOW-PASS FILTER AND DIFFERENTIAL-TO-SINGLE-ENDED CONVERTER FOR DAC OUTPUTS

ΔΣ DACs use noise-shaping techniques to improve in-band signal-to-noise ratio (SNR) performance at the

expense of generating increased out-of-band noise above the Nyquist frequency, or f_S/2. The out-of-band noise

must be low-pass filtered in order to provide optimal converter performance. This filtering is accomplished by a

combination of on-chip and external low-pass filters.

Figure 38 and Figure 39 show the recommended external differential-to-single-ended converter with low-pass

active filter circuits for ac-coupled and dc-coupled applications. These circuits are second-order Butterworth

filters using a multiple feedback (MFB) circuit arrangement that reduces sensitivity to passive component

variations over frequency and temperature. For more information regarding MFB active filter designs, please

refer to Applications Bulletin SBAA055, Dynamic Performance Testing of Digital Audio D/A Converters, available

from the TI web site (www.ti.com) or your local Texas Instruments' sales office.

Because the overall system performance is defined by the quality of the DACs and the associated analog output

circuitry, high-quality audio op amps are recommended for the active filters. Texas Instruments’ OPA2134,

OPA2353, and NE5532A dual op amps are shown in Figure 38 and Figure 39, and are recommended for use

with the PCM1789.

R₂

C₂

R₁

R₃

10 mF

VOUTx+

(4 V_PP

47W

)

Analog Output

(2 V_RMS

C₁

)

VOUTx-

(4 V_PP

)

R₁

R₃

R₂

C₂

NOTE: Amplifier is an NE5532A x 1/2 or OPA2134 x1/2; R₁= 7.5 kΩ; R₂= 5.6 kΩ; R₃= 360 Ω; C₁= 3300 pF; C₂= 680 pF; Gain = 0.747;

f_{–3 dB}= 53 kHz.

Figure 38. AC-Coupled, Post-LPF and Differential to Single-Ended Buffer

R₂

C₂

R₃

R₁

VOUTx+

(4 V_PP

47W

)

Analog Output

(2 V_RMS

C₁

)

VOUTx-

(4 V_PP

)

R₁

R₃

R₂

C₂

NOTE: Amplifier is an NE5532A x 1/2 or OPA2134 x1/2; R₁= 15 kΩ; R₂= 11 kΩ; R₃= 820 Ω; C₁= 1500 pF; C₂= 330 pF; Gain = 0.733;

f_{–3 dB}= 54 kHz.

Figure 39. DC-Coupled, Post-LPF and Differential to Single-Ended Buffer

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PCB LAYOUT GUIDELINES

A typical printed circuit board (PCB) layout for the PCM1789 is shown in Figure 40. A ground plane is

recommended, with the analog and digital sections being isolated from one another using a split or cut in the

circuit board. The PCM1789 should be oriented with the digital I/O pins facing the ground plane split/cut to allow

for short, direct connections to the digital audio interface and control signals originating from the digital section of

the board.

Separate power supplies are recommended for the digital and analog sections of the board. This configuration

prevents the switching noise present on the digital supply from contaminating the analog power supply and

degrading the dynamic performance of the PCM1789.

Digital Power

Analog Power

AGND +5 V_A+V_S-V_S

+3.3 V_DDGND

VDD VCC

Digital Logic

and

Audio

Output

DGND

Circuits

Processor

PCM1789

AGND

Digital

Ground

Analog

Ground

Digital Section

Analog Section

Return Path for 3.3 V_Dand Digital Signals

Figure 40. Recommended PCB Layout

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PACKAGE OPTION ADDENDUM

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13-Nov-2008

PACKAGING INFORMATION

Orderable Device

PCM1789PW

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TSSOP

PW

24

60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

PCM1789PWG4

PCM1789PWR

PCM1789PWRG4

TSSOP

PW

60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

21-Nov-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

PCM1789PWR

TSSOP

PW

24

2000

330.0

16.4

6.95

8.3

1.6

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

21-Nov-2008

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TSSOP PW 24

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 29.0

PCM1789PWR

2000

Pack Materials-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

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Products

Applications

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Medical

Amplifiers

Data Converters

DSP

Clocks and Timers

Interface

amplifier.ti.com

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dsp.ti.com

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/audio

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www.ti.com/military

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Military

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www.ti.com/video

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

型号:	PCM1789PWR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP24,.25
针数：	24
Reach Compliance Code：	compliant
Factory Lead Time：	1 week
风险等级：	1.72
最大模拟输出电压：	8 V
最小模拟输出电压：
转换器类型：	D/A CONVERTER
输入位码：	2'S COMPLEMENT BINARY
输入格式：	SERIAL
JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e4
长度：	7.8 mm
湿度敏感等级：	2
位数：	24
功能数量：	1
端子数量：	24
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP24,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
电源：	3.3,5 V
认证状态：	Not Qualified
座面最大高度：	1.2 mm
子类别：	Other Converters
最大压摆率：	30 mA
标称供电电压：	5 V
表面贴装：	YES
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4.4 mm
Base Number Matches：	1

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