PCM1794现货热卖使用介绍供应商报价哪里找芯片批发报价-中国IC网-芯三七

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

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D

Dual-Supply Operation:

− 5-V Analog, 3.3-V Digital

FEATURES

D

24-Bit Resolution

Analog Performance:

− Dynamic Range: 132 dB (9 V RMS, Mono)

129 dB (4.5 V RMS, Stereo)

127 dB (2 V RMS, Stereo)

D

5-V Tolerant Digital Inputs

D

Small 28-Lead SSOP Package, Lead-Free

Product

APPLICATIONS

− THD+N: 0.0004%

D

A/V Receivers

D

Differential Current Output: 7.8 mA p-p

DVD Players

8× Oversampling Digital Filter:

− Stop-Band Attenuation: –130 dB

− Pass-Band Ripple: 0.00001 dB

Musical Instruments

HDTV Receivers

Car Audio Systems

D

Sampling Frequency: 10 kHz to 200 kHz

System Clock: 128, 192, 256, 384, 512, or

Digital Multitrack Recorders

Other Applications Requiring 24-Bit Audio

768 f With Autodetect

S

D

Accepts 16- and 24-Bit Audio Data

DESCRIPTION

2

D

PCM Data Formats: Standard, I S, and

Left-Justified

The PCM1794 is a monolithic CMOS integrated circuit that

includes stereo digital-to-analog converters and support

circuitry in a small 28-lead SSOP package. The data

converters use TI’s advanced segment DAC architecture

to achieve excellent dynamic performance and improved

tolerance to clock jitter. The PCM1794 provides balanced

current outputs, allowing the user to optimize analog

performance externally. Sampling rates up to 200 kHz are

supported.

D

Optional Interface Available to External

Digital Filter or DSP

D

Digital De-Emphasis

Digital Filter Rolloff: Sharp or Slow

Soft Mute

Zero Flag

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate

precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to

damage because very small parametric changes could cause the device not to meet its published specifications.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

ꢀꢚ ꢙ ꢕꢘ ꢁ ꢋꢊ ꢙꢓ ꢕ ꢑꢋꢑ ꢩꢟ ꢤꢝ ꢜ ꢥꢨ ꢢꢩꢝꢟ ꢩꢣ ꢡꢛ ꢜ ꢜ ꢦꢟꢢ ꢨꢣ ꢝꢤ ꢪꢛꢫ ꢬꢩꢡ ꢨꢢꢩ ꢝꢟ ꢠꢨ ꢢꢦꢭ ꢀꢜ ꢝꢠꢛ ꢡꢢꢣ

ꢡ ꢝꢟ ꢤꢝꢜ ꢥ ꢢꢝ ꢣ ꢪꢦ ꢡ ꢩ ꢤꢩ ꢡ ꢨ ꢢꢩ ꢝꢟꢣ ꢪ ꢦꢜ ꢢꢮꢦ ꢢꢦ ꢜ ꢥꢣ ꢝꢤ ꢋꢦꢧ ꢨꢣ ꢊꢟꢣ ꢢꢜ ꢛꢥ ꢦꢟꢢ ꢣ ꢣꢢ ꢨꢟꢠ ꢨꢜ ꢠ ꢞ ꢨꢜ ꢜ ꢨ ꢟꢢꢯꢭ

ꢀꢜ ꢝ ꢠꢛꢡ ꢢ ꢩꢝ ꢟ ꢪꢜ ꢝ ꢡ ꢦ ꢣ ꢣ ꢩꢟ ꢰ ꢠꢝ ꢦ ꢣ ꢟꢝꢢ ꢟꢦ ꢡꢦ ꢣꢣ ꢨꢜ ꢩꢬ ꢯ ꢩꢟꢡ ꢬꢛꢠ ꢦ ꢢꢦ ꢣꢢꢩ ꢟꢰ ꢝꢤ ꢨꢬ ꢬ ꢪꢨ ꢜ ꢨꢥ ꢦꢢꢦ ꢜ ꢣꢭ

Copyright  2003, Texas Instruments Incorporated

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www.ti.com

SLES080B – MAY 2003 – REVISED NOVEMBER 2003

ORDERING INFORMATION

OPERATION

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA

PRODUCT

PACKAGE

PACKAGE CODE

PCM1794DB

Tube

PCM1794DB

28-lead SSOP

28DB

–25°C to 85°C

PCM1794

PCM1794DBR

Tape and reel

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range unless otherwise noted

PCM1794

V

1, V 2L, V 2R

CC CC

–0.3 V to 6.5 V

–0.3 V to 4 V

0.1 V

CC

DD

Supply voltage

Supply voltage differences: V 1, V 2L, V 2R

CC CC CC

Ground voltage differences: AGND1, AGND2, AGND3L, AGND3R, DGND

0.1 V

LRCK, DATA, BCK, SCK, FMT1, FMT0, MONO, CHSL, DEM, MUTE, RST,

ZERO

–0.3 V to 6.5 V

Digital input voltage

Analog input voltage

–0.3 V to (V

+ 0.3 V) < 4 V

DD

–0.3 V to (V

+ 0.3 V) < 6.5 V

CC

Input current (any pins except supplies)

Ambient temperature under bias

Storage temperature

10 mA

–40°C to 125°C

–55°C to 150°C

150°C

Junction temperature

Lead temperature (soldering)

Package temperature (IR reflow, peak)

260°C, 5 s

250°C

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

all specifications at T = 25°C, V 1 = V 2L = V 2R = 5 V, V

= 3.3 V, f = 44.1 kHz, system clock = 256 f , and 24-bit data, unless

A

CC

DD

S

otherwise noted

PCM1794DB

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

RESOLUTION

DATA FORMAT

24

Bits

2

Audio data interface format

Audio data bit length

Audio data format

Standard, I S, left justified

16-, 24-bit selectable

MSB first, 2s complement

f

S

Sampling frequency

System clock frequency

10

200

kHz

128, 192, 256, 384, 512, 768 f

S

DIGITAL INPUT/OUTPUT

Logic family

TTL compatible

V

2

IH

IL

Input logic level

Input logic current

Output logic level

VDC

µA

0.8

10

I

IH

I

IL

V

= V

DD

= 0 V

IN

–10

2.4

0.4

V

I

= –2 mA

= 2 mA

OH

OL

OH

OL

VDC

V

I

2

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www.ti.com

SLES080B – MAY 2003 – REVISED NOVEMBER 2003

ELECTRICAL CHARACTERISTICS (Continued)

all specifications at T = 25°C, V 1 = V 2L = V 2R = 5 V, V

= 3.3 V, f = 44.1 kHz, system clock = 256 f , and 24-bit data, unless

A

CC

DD

S

otherwise noted

PCM1794DB

TYP

PARAMETER

DYNAMIC PERFORMANCE (2-V RMS OUTPUT)

TEST CONDITIONS

UNIT

MIN

MAX

(1)(2)

f

= 44.1 kHz

0.0004% 0.0008%

S

= 96 kHz

0.0008%

0.0015%

127

THD+N at V

OUT

= 0 dB

= 192 kHz

EIAJ, A-weighted, f = 44.1 kHz

S

EIAJ, A-weighted, f = 96 kHz

S

123

120

127

Dynamic range

dB

EIAJ, A-weighted, f = 192 kHz

127

S

EIAJ, A-weighted, f = 44.1 kHz

S

EIAJ, A-weighted, f = 96 kHz

S

127

Signal-to-noise ratio

Channel separation

EIAJ, A-weighted, f = 192 kHz

127

S

f

S

f

S

f

S

= 44.1 kHz

= 96 kHz

123

122

dB

= 192 kHz

120

Level linearity error

V

OUT

= –120 dB

1

(1)(3)

DYNAMIC PERFORMANCE (4.5-V RMS Output)

f

= 44.1 kHz

= 96 kHz

0.0004%

0.0008%

0.0015%

129

S

THD+N at V

OUT

= 0 dB

= 192 kHz

EIAJ, A-weighted, f = 44.1 kHz

S

EIAJ, A-weighted, f = 96 kHz

S

129

Dynamic range

dB

EIAJ, A-weighted, f = 192 kHz

129

S

EIAJ, A-weighted, f = 44.1 kHz

S

EIAJ, A-weighted, f = 96 kHz

S

129

Signal-to-noise ratio

EIAJ, A-weighted, f = 192 kHz

129

S

f

S

f

S

f

S

= 44.1 kHz

= 96 kHz

124

123

Channel separation

= 192 kHz

121

(1)(3)

DYNAMIC PERFORMANCE (MONO MODE)

f

= 44.1 kHz

= 96 kHz

0.0004%

0.0008%

0.0015%

132

S

THD+N at V

OUT

= 0 dB

= 192 kHz

EIAJ, A-weighted, f = 44.1 kHz

S

EIAJ, A-weighted, f = 96 kHz

S

132

Dynamic range

dB

EIAJ, A-weighted, f = 192 kHz

132

S

EIAJ, A-weighted, f = 44.1 kHz

S

EIAJ, A-weighted, f = 96 kHz

S

132

Signal-to-noise ratio

EIAJ, A-weighted, f = 192 kHz

132

S

(1)

Filter condition:

THD+N: 20-Hz HPF, 20-kHz apogee LPF

Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted

Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted

Channel separation: 20-Hz HPF, 20-kHz AES17 LPF

Analog performance specifications are measured using the System Twot Cascade audio measurement system by Audio Precision in the

averagingmode.

(2)

(3)

Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 24.

Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 25.

Audio Precision and System Two are trademarks of Audio Precision, Inc.

Other trademarks are the property of their respective owners.

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

ELECTRICAL CHARACTERISTICS (Continued)

all specifications at T = 25°C, V 1 = V 2L = V 2R = 5 V, V

= 3.3 V, f = 44.1 kHz, system clock = 256 f , and 24-bit data, unless

A

CC

DD

S

otherwise noted

PCM1794DB

TYP

PARAMETER

TEST CONDITIONS

UNIT

MIN

MAX

ANALOG OUTPUT

Gain error

–6

–3

–2

2

0.5

7.8

–6.2

6

3

2

% of FSR

mA p-p

mA

Gain mismatch, channel-to-channel

Bipolar zero error

At BPZ

Output current

Full scale (0 dB)

At BPZ

Center current

DIGITAL FILTER PERFORMANCE

De-emphasis error

0.004

dB

FILTER CHARACTERISTICS-1: SHARP ROLLOFF

0.00001 dB

–3 dB

0.454 f

S

Pass band

0.49 f

S

Stop band

0.546 f

–130

S

Pass-band ripple

0.00001

dB

s

Stop-band attenuation

Delay time

Stop band = 0.546 f

S

55/f

S

FILTER CHARACTERISTICS-2: SLOW ROLLOFF

0.04 dB

–3 dB

0.254 f

S

Pass band

0.46 f

S

Stop band

Pass-band ripple

0.732 f

–100

S

0.001

dB

s

Stop-band attenuation

Delay time

Stop band = 0.732 f

S

18/f

S

POWER SUPPLY REQUIREMENTS

V

3

3.3

5

3.6

VDC

DD

CC

1

Voltage range

Supply current

2L

4.75

5.25

15

V

CC

2R

f

S

f

S

f

S

f

S

f

S

f

S

f

S

f

S

f

S

= 44.1 kHz

= 96 kHz

12

23

I

mA

mW

DD

CC

= 192 kHz

= 44.1 kHz

= 96 kHz

45

(1)

33

40

35

I

= 192 kHz

= 44.1 kHz

= 96 kHz

37

205

250

335

250

(1)

Power dissipation

TEMPERATURE RANGE

= 192 kHz

Operation temperature

Thermal resistance

–25

85

°C

θ

JA

28-pin SSOP

100

°C/W

(1)

Input is BPZ data.

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

PIN ASSIGNMENTS

PCM1794

(TOP VIEW)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

MONO

CHSL

DEM

LRCK

DATA

BCK

V

2L

CC

2

AGND3L

3

I

L–

L+

OUT

4

OUT

5

AGND2

6

V

1

CC

7

SCK

DGND

L

R

COM

REF

8

9

V

I

DD

MUTE

FMT0

FMT1

ZERO

RST

10

11

12

13

14

AGND1

I

R–

R+

OUT

AGND3R

2R

V

CC

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

Terminal Functions

TERMINAL

I/O

DESCRIPTIONS

NAME

AGND1

AGND2

AGND3L

AGND3R

BCK

19

24

27

16

6

–

I

Analog ground (internal bias)

Analog ground (L-channel DACFF)

Analog ground (R-channel DACFF)

(1)

Bit clock input

L-, R-channel select

Serial audio data input

(1)

CHSL

2

I

DATA

5

I

DEM

3

I

De-emphasis enable

Digital ground

DGND

FMT0

8

–

I

(1)

11

12

25

26

17

18

20

4

Audio data format select

FMT1

I

L+

L–

R+

R–

O

–

I

L-channel analog current output +

L-channel analog current output –

R-channel analog current output +

R-channel analog current output –

Output current reference bias pin

OUT

REF

(1)

Left and right clock (f ) input

S

LRCK

MONO

MUTE

RST

(1)

1

I

Monaural mode enable

(1)

10

14

7

I

Mute control

(1)

I

Reset

System clock input

Analog power supply, 5 V

(1)

SCK

I

V

1

23

28

15

22

21

9

–

O

CC

2L

2R

Analog power supply (L-channel DACFF), 5 V

Analog power supply (R-cahnnel DACFF), 5 V

L-channel internal bias decoupling pin

R-channel internal bias decoupling pin

Digital power supply, 3.3 V

L

COM

DD

R

ZERO

13

Zero flag

(1)

Schmitt-trigger input, 5-V tolerant

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

FUNCTIONAL BLOCK DIAGRAM

I

L–

L+

OUT

LRCK

Audio

BCK

Current

Segment

DAC

V

OUT

L

Data Input

DATA

I/F

OUT

I/V and Filter

8

Oversampling

Digital

Filter

and

Function

Control

V

I

L

COM

MUTE

FMT1

FMT0

MONO

CHSL

Advanced

Segment

DAC

Bias

and

Vref

REF

V

COM

R

Modulator

Function

Control

I/F

I

R–

OUT

Current

Segment

DAC

V R

OUT

DEM

RST

I

R+

I/V and Filter

System

Clock

Manager

ZERO

Zero

Detect

Power Supply

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

TYPICAL PERFORMANCE CURVES

DIGITAL FILTER

Digital Filter Response

AMPLITUDE

vs

FREQUENCY

0

−50

2

0.00002

1

0.00001

−100

−150

−200

0

−1

–0.00001

−2

–0.00002

0

1

2

3

4

0.0

0.1

0.2

0.3

0.4

0.5

Frequency[× f ]

S

Figure 1. Frequency Response, Sharp Rolloff

Figure 2. Pass-Band Ripple, Sharp Rolloff

AMPLITUDE

vs

AMPLITUDE

vs

FREQUENCY

0

−50

0

−2

−4

−6

−8

−100

−150

−200

−10

−12

−14

−16

−18

−20

0

1

2

3

4

0.0

0.1

0.2

0.3

0.4

0.5

0.6

Frequency[× f ]

S

Figure 3. Frequency Response, Slow Rolloff

Figure 4. Transition Characteristics, Slow Rolloff

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

De-Emphasis Filter

DE-EMPHASIS LEVEL

DE-EMPHASIS ERROR

vs

FREQUENCY

0

−2

0.020

f

S

= 44.1 kHz

f = 44.1 kHz

S

15

0.015

10

0.010

5

0.005

−4

0

−6

−5

–0.005

−10

–0.010

−8

−15

–0.015

−10

−

–0.020

0

2

4

6

8

10 12 14 16 18 20

0

2

4

6

8

10 12 14 16 18 20

f – Frequency – kHz

Figure 5

Figure 6

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

ANALOG DYNAMIC PERFORMANCE

Supply Voltage Characteristics

TOTAL HARMONIC DISTORTION + NOISE

DYNAMIC RANGE

vs

SUPPLY VOLTAGE

132

130

128

126

124

122

0.01

f

S

= 96 kHz

f

S

= 48 kHz

f

S

= 192 kHz

f

= 192 kHz

S

0.001

f

S

= 96 kHz

f

S

= 48 kHz

5.00

0.0001

4.50

4.75

5.25

5.50

4.50

4.75

5.00

5.25

5.50

V

CC

– Supply Voltage – V

V

CC

– Supply Voltage – V

Figure 7

Figure 8

SIGNAL-to-NOISE RATIO

vs

CHANNEL SEPARATION

vs

SUPPLY VOLTAGE

132

130

128

126

124

122

130

128

126

124

122

120

f

= 96 kHz

S

f

= 96 kHz

S

f

S

= 192 kHz

f

S

= 48 kHz

f

= 48 kHz

S

f

S

= 192 kHz

4.50

4.75

5.00

5.25

5.50

4.50

4.75

5.00

5.25

5.50

V

CC

– Supply Voltage – V

V

CC

– Supply Voltage – V

Figure 10

Figure 9

NOTE: T = 25°C, V

= 3.3 V, measurement circuit is Figure 25 (V = 4.5 V rms).

OUT

A

DD

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

Temperature Characteristics

TOTAL HARMONIC DISTORTION + NOISE

DYNAMIC RANGE

vs

FREE-AIR TEMPERATURE

132

130

128

126

124

122

0.01

f

= 96 kHz

S

f

= 48 kHz

S

f

S

= 192 kHz

f

S

= 192 kHz

0.001

f

= 96 kHz

S

f

= 48 kHz

S

0.0001

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

T

A

– Free-Air Temperature – °C

T

A

– Free-Air Temperature – °C

Figure 11

Figure 12

SIGNAL-to-NOISE RATIO

vs

CHANNEL SEPARATION

vs

FREE-AIR TEMPERATURE

132

130

128

126

124

122

130

128

126

124

122

120

f

= 96 kHz

S

f

S

= 192 kHz

f = 48 kHz

S

f

S

= 48 kHz

f

S

= 192 kHz

f

= 96 kHz

S

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

T

A

– Free-Air Temperature – °C

T

A

– Free-Air Temperature – °C

Figure 13

Figure 14

NOTE: V

DD

= 3.3 V, V

= 5 V, measurement circuit is Figure 25 (V = 4.5 V rms).

OUT

CC

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

AMPLITUDE

vs

AMPLITUDE

vs

FREQUENCY

0

−20

−40

−60

−80

−100

−120

−140

−160

−180

−100

−120

−140

−160

0

2

4

6

8

10 12 14 16 18 20

0

10 20 30 40 50 60 70 80 90 100

f – Frequency – kHz

NOTE: f = 48 kHz, 32768 point 8 average, T = 25°C, V

= 3.3 V,

NOTE: f = 48 kHz, 32768 point 8 average, T = 25°C, V

= 3.3 V,

S

A

DD

S

A

DD

V

CC

= 5 V, measurement circuit is Figure 25.

V

CC

= 5 V, measurement circuit is Figure 25.

Figure 15. –60-db Output Spectrum, BW = 20 kHz

Figure 16. –60-db Output Spectrum, BW = 100 kHz

TOTAL HARMONIC DISTORTION + NOISE

vs

INPUT LEVEL

10

1

0.1

0.01

0.001

0.0001

−100

−80

−60

−40

−20

0

Input Level – dBFS

NOTE: f = 48 kHz, T = 25°C, V

DD

= 3.3 V, V

CC

= 5 V,

S

A

measurement circuit is Figure 25.

Figure 17. THD+N vs Input Level

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

SYSTEM CLOCK AND RESET FUNCTIONS

System Clock Input

The PCM1794 requires a system clock for operating the digital interpolation filters and advanced segment DAC

modulators. The system clock is applied at the SCK input (pin 7). The PCM1794 has a system clock detection circuit

that automatically senses the frequency at which the system clock is operating. Table 1 shows examples of system

clock frequencies for common audio sampling rates.

Figure 18 shows the timing requirements for the system clock input. For optimal performance, it is important to use

a clock source with low phase jitter and noise. One of the Texas Instruments PLL1700 family of multiclock generators

is an excellent choice for providing the PCM1794 system clock.

Table 1. System Clock Rates for Common Audio Sampling Frequencies

SYSTEM CLOCK FREQUENCY (F

) (MHz)

512 f

SCK

SAMPLING FREQUENCY

128 f

192 f

256 f

384 f

768 f

S

32 kHz

44.1 kHz

48 kHz

4.096

5.6488

6.144

8.4672

9.216

8.192

11.2896

12.288

24.576

49.152

12.288

16.9344

18.432

36.864

73.728

16.384

22.5792

24.576

33.8688

36.864

96 kHz

12.288

24.576

18.432

36.864

49.152

(1)

73.728

(1)

192 kHz

(1)

This system clock rate is not supported for the given sampling frequency.

t

(SCKH)

H

2.0 V

0.8 V

System Clock (SCK)

L

t

(SCKL)

t

(SCY)

PARAMETERS

MIN

13

(SCY)

0.4t

MAX UNITS

t

System clock pulse cycle time

ns

(SCY)

t

System clock pulse duration, HIGH

System clock pulse duration, LOW

0.4t

(SCY)

(SCKH)

t

(SCKL)

Figure 18. System Clock Input Timing

Power-On and External Reset Functions

The PCM1794 includes a power-on reset function. Figure 19 shows the operation of this function. With V

> 2 V,

DD

the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time

> 2 V.

V

DD

The PCM1794 also includes an external reset capability using the RST input (pin 14). This allows an external

controller or master reset circuit to force the PCM1794 to initialize to its default reset state.

Figure 20 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The

RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock

periods. The external reset is especially useful in applications where there is a delay between the PCM1794 power

up and system clock activation.

13

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

V

DD

2.4 V (Max)

2.0 V (Typ)

1.6 V (Min)

Reset

Reset Removal

Internal Reset

System Clock

1024 System Clocks

Figure 19. Power-On Reset Timing

RST (Pin 14)

50 % of V

DD

t

(RST)

Reset

Reset Removal

Internal Reset

System Clock

1024 System Clocks

PARAMETERS

Reset pulse duration, LOW

MIN

20

MAX UNITS

t

ns

(RST)

Figure 20. External Reset Timing

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

AUDIO DATA INTERFACE

Audio Serial Interface

The audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the

serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio

interface. Serial data is clocked into the PCM1794 on the rising edge of BCK. LRCK is the serial audio left/right word

clock.

The PCM1794 requires the synchronization of LRCK and the system clock, but does not need a specific phase

relation between LRCK and the system clock.

If the relationship between LRCK and the system clock changes more than 6 BCK, internal operation is initialized

within 1/f and the analog outputs are forced to the bipolar zero level until resynchronization between LRCK and the

S

system clock is completed.

PCM Audio Data Formats and Timing

2

The PCM1794 supports industry-standard audio data formats, including standard right-justified, I S, and

left-justified. The data formats are shown in Figure 22. Data formats are selected using the format bits,

FMT1 (pin 12), and FMT0 (pin 11) as shown in Table 2. All formats require binary twos-complement, MSB-first audio

data. Figure 21 shows a detailed timing diagram for the serial audio interface.

50% of V

LRCK

DD

t

(BCL)

t

(BCH)

(LB)

BCK

t

(BCY)

(BL)

DATA

t

(DS)

(DH)

PARAMETERS

MIN MAX UNITS

t

BCK pulse cycle time

BCK pulse duration, LOW

BCK pulse duration, HIGH

BCK rising edge to LRCK edge

LRCK edge to BCK rising edge

DATA setup time

70

30

10

ns

(BCY)

(BCL)

(BCH)

(BL)

(LB)

(DS)

DATA hold time

(DH)

—

LRCK clock duty

50% 2 bit clocks

Figure 21. Timing of Audio Interface

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

(1) Standard Data Format (Right Justified); L-Channel = HIGH, R-Channel = LOW

1/f

S

LRCK

R-Channel

L-Channel

BCK

Audio Data Word = 16-Bit

14 15 16

1

2

15 16

LSB

1

2

15 16

DATA

MSB

Audio Data Word = 24-Bit

22 23 24

1

2

23 24

LSB

1

2

23 24

DATA

MSB

(2) Left Justified Data Format; L-Channel = HIGH, R-Channel = LOW

1/f

S

LRCK

BCK

R-Channel

L-Channel

Audio Data Word = 24-Bit

DATA

1

2

23 24

LSB

1

2

23 24

1

2

MSB

2

(3) I S Data Format; L-Channel = LOW, R-Channel = HIGH

1/f

S

LRCK

BCK

L-Channel

R-Channel

Audio Data Word = 24-Bit

DATA

1

2

23 24

LSB

1

2

23 24

1

2

MSB

Figure 22. Audio Data Input Formats

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

FUNCTION DESCRIPTIONS

Audio data format

Audio format is selected using FMT0 (pin 11) and FMT1 (pin 12). The PCM1794 also supports monaural mode and DF

bypass mode using MONO (pin 1) and CHSL (pin 2). The PCM1794 can select the DF rolloff characteristics.

Table 2. Audio Data Format Select

MONO

CHSL

FMT1

FMT0

FORMAT

STEREO/MONO

Stereo

DF ROLLOFF

Sharp

Slow

2

I S

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Left-justified format

Standard, 16-bit

Standard, 24-bit

Stereo

2

I S

Stereo

Left-justified format

Standard, 16-bit

Stereo

Slow

Stereo

Slow

Digital filter bypass

Mono

–

2

I S

Mono, L-channel

Mono, R-channel

Sharp

Left-justified format

Standard, 16-bit

Standard, 24-bit

2

I S

Left-justified format

Standard, 16-bit

Standard, 24-bit

Soft Mute

The PCM1794 supports mute operation. When MUTE (pin 10) is set to HIGH, both analog outputs are transitioned

to the bipolar zero level in –0.5-dB steps with a transition speed of 1/f per step. This system provides pop-free muting

S

of the DAC output.

De-Emphasis

The PCM1794 has a de-emphasis filters for the sampling frequency of 44.1 kHz. The de-emphasis filter is controlled

using DEM (pin 3).

Zero Detect

When the PCM1794 detects that the audio input data in the L-channel and the R-channel is continuously zero for

1024 f , the PCM1794 sets ZERO (pin 13)to HIGH.

S

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

TYPICAL CONNECTION DIAGRAM

C

f

5 V

R

f

0.1 µF

MONO

CHSL

DEM

V

2L

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

10 µF

CC

+

–

+

Controller

AGND3L

Differential

to

Single

Converter

With

Low-Pass

Filter

I L–

OUT

3

C

f

V

OUT

L-Channel

LRCK

DATA

BCK

I

L+

4

OUT

f

5 V

PCM

Audio Data

Source

AGND2

5

–

+

V

1

CC

6

47 µF

+

SCK

V L

COM

7

C

f

+

10 µF

PCM1794

DGND

V

COM

R

8

R

0.1 µF

f

47 µF

10 kΩ

V

DD

I

REF

9

–

+

MUTE

FMT0

FMT1

ZERO

RST

AGND1

10

11

12

13

14

Differential

to

Single

Converter

With

Low-Pass

Filter

I

R–

R+

C

OUT

f

V

OUT

R-Channel

Controller

I

OUT

f

0.1 µF

5 V

AGND3R

–

+

V

CC

2R

10 µF

+

3.3 V

+

10 µF

Figure 23. Typical Application Circuit

18

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

APPLICATION INFORMATION

APPLICATION CIRCUIT

The design of the application circuit is very important in order to actually realize the high S/N ratio of which the

PCM1794 is capable. This is because noise and distortion that are generated in an application circuit are not

negligible.

In the circuit of Figure 24, the output level is 2 V RMS, and 127 dB S/N is achieved. The circuit of Figure 25 can realize

the highest performance. In this case the output level is set to 4.5 V RMS and 129 dB S/N is achieved (stereo mode).

In monaural mode, if the output of the L-channel and R-channel is used as a balanced output, 132 dB S/N is achieved

(see Figure 26).

I/V Section

The current of the PCM1794 on each of the output pins (I

L+, I

L–, I

R+, I

R–) is 7.8 mA p-p at 0 dB (full

OUT

scale). The voltage output level of the I/V converter (Vi) is given by following equation:

Vi = 7.8 mA p–p × R (R : feedback resistance of I/V converter)

f

An NE5534 op amp is recommended for the I/V circuit to obtain the specified performance. Dynamic performance

such as the gain bandwidth, settling time, and slew rate of the op amp affects the audio dynamic performance of the

I/V section.

Differential Section

The PCM1794 voltage outputs are followed by differential amplifier stages, which sum the differential signals for each

channel, creating a single-ended I/V op-amp output. In addition, the differential amplifiers provide a low-pass filter

function.

The op amp recommended for the differential circuit is the Linear Technology LT1028, because its input noise is low.

19

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

C

1

2200 pF

R

1

750 Ω

V

CC

V

CC

C

3

C

11

0.1 µF

2700 pF

R

270 Ω

5

C

15

0.1 µF

C

22 pF

17

C

33 pF

19

7

5

R

560 Ω

7

2

3

8

6

3

–

+

I –

OUT

5

R

7

100 Ω

2

3

–

+

6

U

1

NE5534

U

4

3

LT1028

4

R

4

C

12

0.1 µF

560 Ω

R

6

270 Ω

C

16

0.1 µF

C

4

V

EE

2700 pF

V

EE

C

2

2200 pF

R

2

750 Ω

V

CC

C

13

0.1 µF

V

= 15 V

CC

= –15 V

EE

C

18

f

C

= 217 kHz

22 pF

7

5

2

3

8

6

–

+

I +

OUT

U

2

NE5534

4

C

14

0.1 µF

V

EE

Figure 24. Measurement Circuit, V

= 2 V RMS

OUT

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

C

1

2200 pF

R

1

820 Ω

V

CC

V

CC

C

3

C

11

0.1 µF

2700 pF

R

360 Ω

5

C

15

0.1 µF

C

22 pF

17

C

33 pF

19

7

5

R

360 Ω

7

2

3

8

6

3

–

+

I –

OUT

5

R

100 Ω

2

3

7

–

+

6

U

1

NE5534

U

4

3

LT1028

4

R

4

C

12

0.1 µF

360 Ω

R

6

360 Ω

C

16

0.1 µF

C

4

V

EE

2700 pF

V

EE

C

2

2200 pF

R

2

820 Ω

V

CC

V

= 15 V

CC

C

13

0.1 µF

= –15 V

EE

f

C

= 162 kHz

C

22 pF

18

7

5

2

3

8

6

–

+

I +

OUT

U

2

NE5534

4

C

14

0.1 µF

V

EE

Figure 25. Measurement Circuit, V

= 4.5 V RMS

OUT

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

I

L– (Pin 26)

L+ (Pin 25)

I

–

+

OUT

OUT+

Figure 25

Circuit

I

OUT

3

2

1

I

R– (Pin 18)

R+ (Pin 17)

I

–

+

OUT

OUT–

Figure 25

Circuit

Balanced Out

I

OUT

Figure 26. Measurement Circuit for Monaural Mode

APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE

V

DD

MONO

CHSL

DEM

V

2L

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

CC

External

Filter

Device

AGND3L

I

L–

L+

3

OUT

WDCK

LRCK

DATA

BCK

4

OUT

DATA

BCK

SCK

AGND2

5

V

1

CC

6

Analog

Output Stage

(See Figure 23)

SCK

V L

COM

7

PCM1794

DGND

V

COM

R

8

V

DD

I

REF

9

MUTE

FMT0

FMT1

ZERO

RST

AGND1

10

11

12

13

14

I

R–

R+

OUT

I

OUT

AGND3R

V

CC

2R

Figure 27. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

Application for Interfacing With an External Digital Filter

For some applications, it may be desirable to use a programmable digital signal processor as an external digital filter

to perform the interpolation function. The following pin settings enable the external digital filter application mode.

D

MONO (pin 1) = LOW

CHSL (Pin 2) = HIGH

FMT0 (Pin 11) = HIGH

FMT1 (pin 12) = HIGH

The pins used to provide the serial interface for the external digital filter are shown in the connection diagram of

Figure 27. The word clock (WDCK) must be operated at 8× or 4× the desired sampling frequency, f .

S

System Clock (SCK) and Interface Timing

The PCM1794 in an application using an external digital filter requires the synchronization of WDCK and the system

clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK, and DATA is

shown in Figure 29.

Audio Format

The PCM1794 in the external digital filter interface mode supports right-justified audio formats including 24-bit audio

data, as shown in Figure 28.

1/4 f or 1/8 f

S

WDCK

BCK

Audio Data Word = 24-Bit

23 24

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

LSB

DATA

MSB

Figure 28. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

WDCK

50% of V

DD

t

(LB)

(BCH)

(BCL)

50% of V

BCK

t

(BCY)

(BL)

DATA

t

(DS)

(DH)

PARAMETER

MIN

20

7

MAX UNITS

t

BCK pulse cycle time

ns

(BCY)

(BCL)

(BCH)

(BL)

BCK pulse duration, LOW

BCK pulse duration, HIGH

7

BCK rising edge to WDCK falling edge

WDCK falling edge to BCK rising edge

DATA setup time

5

(LB)

5

(DS)

DATA hold time

5

(DH)

Figure 29. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application

THEORY OF OPERATION

Upper

0–62

6 Bits

Level

ICOB

Decoder

0–66

Current

Segment

DAC

Advanced

DWA

Digital Input

Analog Output

24 Bits

8 f

rd

3 -Order

S

5-Level

Sigma-Delta

0–4

Level

MSB

and

Lower 18 Bits

Figure 30. Advanced Segment DAC

The PCM1794 uses TI’s advanced segment DAC architecture to achieve excellent dynamic performance and

improved tolerance to clock jitter. The PCM1794 provides balanced current outputs.

Digital input data via the digital filter is separated into 6 upper bits and 18 lower bits. The 6 upper bits are converted

to inverted complementary offset binary (ICOB) code. The lower 18 bits, associated with the MSB, are processed

by a five-level third-order delta-sigma modulator operated at 64 f by default. The 1 level of the modulator is equivalent

S

to the 1 LSB of the ICOB code converter. The data groups processed in the ICOB converter and third-order

delta-sigma modulator are summed together to create an up-to-66-level digital code, and then processed by

data-weighted averaging (DWA) to reduce the noise produced by element mismatch. The data of up to 66 levels from

the DWA is converted to an analog output in the differential-current segment section.

This architecture has overcome the various drawbacks of conventional multibit processing and also achieves

excellent dynamic performance.

24

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SLES080B – MAY 2003 – REVISED NOVEMBER 2003

Analog output

The following table and Figure 31 show the relationship between the digital input code and analog output.

800000 (–FS)

–2.3

000000 (BPZ)

7FFFFF (+FS)

I

N [mA]

P [mA]

–6.2

–4.65

0

–10.1

OUT

I

–10.1

–2.3

–7.575

OUT

V

N [V]

P [V]

–1.725

–7.575

–2.821

OUT

V

–1.725

OUT

V

[V]

2.821

OUT

NOTE: V

N is the output of U1, V

measurementcircuit of Figure 24.

P is the output of U2, and V

OUT

is the output of U3 in the

OUT

OUTPUT CURRENT

vs

INPUT CODE

0

−2

I N

OUT

−4

−6

−8

I P

OUT

−10

−12

800000(–FS)

000000(BPZ)

7FFFFF(+FS)

Input Code – Hex

Figure 31. The Relationship Between Digital Input and Analog Output

25

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

28

M

0,15

15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

1

14

0,25

A

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

14

16

20

24

28

30

38

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

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solutions:

Products

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Amplifiers

amplifier.ti.com

www.ti.com/audio

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Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

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Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

型号:	PCM1794ADB
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	SSOP
包装说明：	SSOP-28
针数：	28
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风险等级：	0.81
Samacsys Confidence：	3
Samacsys Status：	Released
Samacsys PartID：	280002
Samacsys Pin Count：	28
Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Small Outline Packages
Samacsys Footprint Name：	ssop 28 pin
Samacsys Released Date：	2017-01-12 12:59:53
Is Samacsys：	N
转换器类型：	D/A CONVERTER
输入位码：	2'S COMPLEMENT BINARY
输入格式：	SERIAL
JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e4
长度：	10.2 mm
湿度敏感等级：	1
位数：	24
功能数量：	1
端子数量：	28
最高工作温度：	85 °C
最低工作温度：	-25 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP
封装等效代码：	SSOP28,.3
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
电源：	3.3,5 V
认证状态：	Not Qualified
座面最大高度：	2 mm
子类别：	Other Converters
最大压摆率：	40 mA
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	OTHER
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	5.3 mm
Base Number Matches：	1

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