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产品型号PI6C180BVE的Datasheet PDF文件预览

PI6C180B  
Precision 1-18 Clock Buffer  
Product Features  
Description  
The PI6C180B, a high-speed low-noise 1-18 noninverting buffer  
designed for 140 MHz SDRAM clock buffer applications.  
High-speed, to 140 MHz  
Low-noisenon-inverting1-18buffer  
Supports up to four SDRAM DIMMs  
Low skew (< 250ps) between any two output clocks  
2
At power up all SDRAM output are enabled and active. The I C  
Serial control may be used to individually activate/deactivate any  
of the 18 output drivers.  
2
The output enable (OE) pin may be pulled low to put all outputs in a  
Hi-Z state.  
I CSerialConfigurationinterface  
Multiple V , V pins for noise reduction  
DD SS  
Note:  
3.3V power supply voltage  
Separate Hi-Z pin for testing  
48-pinSSOPpackage(V)  
2
Purchase of I C components from Pericom conveys a license to  
2
use them in an I C system as defined by Philips.  
Logic Block Diagram  
Product Pin Configuration  
48-Pin  
V
PS8468  
05/03/00  
1
PI6C180B  
Precision 1-18 Clock Buffer  
Product Pin Description  
Pin  
4,5,8,9  
Symbol  
SDRAM[0-3]  
SDRAM[4-7]  
SDRAM[8-11]  
SDRAM[12-15]  
SDRAM[16-17]  
BUF_IN  
Type  
O
Qty  
4
Description  
SDRAM Byte 0 clock output  
SDRAM Byte 1 clock output  
SDRAM Byte 2 clock output  
SDRAM Byte 3 clock output  
13,14,17,18  
31,32,35,36  
40,41,44,45  
21,28  
O
4
O
4
O
4
O
4
SDRAM clock outputs usable for feedback  
Input for 1-18 buffer  
11  
I
1
Hi-Z all outputs when held LOW. Has a >100kinternal  
pull-up resistor  
38  
OE  
I
1
2
24  
25  
SDATA  
I/O  
I/O  
1
1
Data pin for I C circuitry. Has a >100kinternal pull-up resistor  
2
SCLOCK  
Clock pin I C circuitry. Has a >100kinternal pull-up resistor  
3,7,12,16,20,  
29,33,37,42,46  
V
]
Power  
10  
10  
3.3V power supply for SDRAM buffers  
Ground for SDRAM buffers  
DD[0-9  
6,10,15,19,22,  
27,30,34,39,43  
V
SS[0-9  
]
Ground  
2
23  
V
Power  
Ground  
Reserved  
1
1
4
3.3V power supply for I C circuitry  
DDIIC  
2
26  
V
SSIIC  
Ground for I C circuitry  
1,2,47,48  
NC  
Reserved for future modification. No connects  
OE Functionality  
PI6C180BSerialConfigurationMap  
OE  
SDRAM[0-17] Note  
Byte0:SDRAMActive/InactiveRegister  
(1 = enable, 0 = disable)  
0
Hi-Z  
1
2
1
BUF_IN  
Bit Pin #  
Description  
Notes:  
SDRAM7  
(Active/Inactive)  
1. Used for test purposes only  
2. Buffers are non-inverting  
Bit 7  
18  
17  
14  
13  
9
SDRAM6  
(Active/Inactive)  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
2
PI6C180 I C Address Assignment  
SDRAM5  
(Active/Inactive)  
A6 A5 A4 A3 A2  
A1 A0 R/W  
SDRAM4  
(Active/Inactive)  
1
1
0
1
0
0
1
0
SDRAM3  
(Active/Inactive)  
SDRAM2  
(Active/Inactive)  
8
SDRAM1  
(Active/Inactive)  
5
Note:  
Inactive means outputs are  
held LOW and are disabled  
from switching.  
SDRAM0  
(Active/Inactive)  
4
PS8468  
05/03/00  
2
PI6C180B  
Precision 1-18 Clock Buffer  
2
2-Wire I C Control  
2
The I C interface permits individual enable/disable of each clock  
Each data transfer is initiated with a start condition and ended with  
a stop condition. The first byte after a start condition is always a  
7-bit address byte followed by a read/write bit. (HIGH = read from  
addresseddevice,LOW=writetoaddresseddevice).Ifthedevice’s  
own address is detected, PI6C180B generates an acknowledge by  
pulling SDATA line LOW during ninth clock pulse, then accepts  
the following data bytes until another start or stop condition is  
detected.  
output and test mode enable.  
ThePI6C180Bisaslavereceiverdevice. Itcannotbereadback. Sub  
addressing is not supported. All preceding bytes must be sent in  
order to change one of the control bytes.  
Every bite put on the SDATA line must be 8-bits long (MSB first),  
followed by an acknowledge bit generated by the receiving device.  
DuringnormaldatatransfersSDATAchangesonlywhenSCLOCK  
isLOW. Exceptions: AHIGHtoLOWtransitiononSDATAwhile  
SCLOCK is HIGH indicates a “start” condition. A LOW to HIGH  
transitiononSDATAwhileSCLOCKisHIGHisa“stop”condition  
and indicates the end of a data transfer cycle.  
Following acknowledgement of the address byte (D2), two more  
bytes must be sent:  
1. “Command Code” byte, and  
2. “Byte Count” byte.  
Although the data bits on these two bytes are “don’t care,” they  
must be sent and acknowledged.  
Byte2: Optional Register for Possible Future  
Requirements (1 = enable, 0 = disable)  
Byte1: SDRAM Active/Inactive Register  
(1 = enable, 0 = disable)  
Bit Pin #  
Description  
SDRAM17 (Active/Inactive)  
SDRAM16 (Active/Inactive)  
(Reserved)  
Bit  
Pin #  
45  
Description  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
SDRAM15 (Active/Inactive)  
SDRAM14 (Active/Inactive)  
SDRAM13 (Active/Inactive)  
SDRAM12 (Active/Inactive)  
SDRAM11 (Active/Inactive)  
SDRAM10 (Active/Inactive)  
SDRAM9 (Active/Inactive)  
SDRAM8 (Active/Inactive)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
28  
21  
44  
41  
40  
(Reserved)  
36  
(Reserved)  
35  
(Reserved)  
32  
(Reserved)  
31  
(Reserved)  
Maximum Ratings  
(Above which the useful life may be impaired. For user guidelines, not tested.)  
Note:  
Stresses greater than those listed under MAXIMUM  
RATINGS may cause permanent damage to the  
device. This is a stress rating only and functional  
operation of the device at these or any other conditions  
above those indicated in the operational  
sections of this specification is not implied. Exposure  
to absolute maximum rating conditions for extended  
periods may affect reliability.  
Storage Temperature .............................................................65°C to +150°C  
Ambient Temperature with Power Applied .............................. –0°C to +70°C  
3.3V Supply Voltage to Ground Potential .............................. –0.5V to +4.6V  
DC Input Voltage .................................................................... –0.5V to +4.6V  
Supply Current (V = +3.465V, C  
= Max.)  
LOAD  
DD  
Symbol  
Parameter  
Supply Current  
Supply Current  
Supply Current  
Test Condition  
BUF_IN = 0 MHz  
Min. Typ. Max.  
Units  
I
3
DD  
I
BUF_IN = 66.66 MHz  
BUF_IN = 100.0 MHz  
230  
360  
mA  
DD  
I
DD  
PS8468  
05/03/00  
3
PI6C180B  
Precision 1-18 Clock Buffer  
DC Operating Specifications (V = +3.3V ±5%, T = 0°C –70°C)  
DD  
A
Symbol  
Parameter  
Test Condition  
Min.  
Max.  
Units  
Input Voltage  
V
Input high voltage  
Input low voltage  
Input leakage current  
V
2.0  
V
DD  
+0.3  
IH  
DD  
V
V
V
-0.3  
0.8  
IL  
SS  
I
IL  
0 < V < V  
DD  
–5  
+5  
mA  
IN  
V [0-9] = 3.3V ±5%  
DD  
V
Output high voltage  
I
= –1mA  
2.4  
OH  
OH  
V
V
Output low voltage  
Output pin capacitance  
Input pin capacitance  
Pin Inductance  
I
= 1mA  
0.4  
6
OL  
OL  
C
OUT  
pF  
C
5
IN  
L
PIN  
7
nH  
°C  
T
Ambient Temperature  
No Airflow  
0
70  
A
SDRAM Clock Buffer Operating Specification  
Symbol  
Parameter  
Pull-up current  
Test Conditions Min. Typ. Max. Units  
I
V
= 2.0V  
= 3.135V  
= 1.0V  
= 0.4V  
–40  
40  
OHMIN  
OUT  
I
Pull-up current  
V
OUT  
36  
OHMAX  
mA  
I
Pull-down current  
Pull-down current  
V
OUT  
OLMIN  
I
V
OUT  
38  
4
OLMAX  
Output rise edge rate  
SDRAM only  
3.3V ±5%  
@04V-2.4V  
t
SDRAM  
RH  
1.5  
1.5  
V/ns  
Output fall edge rate  
SDRAM only  
3.3V ±5%  
@2.4V-0.4V  
t
SDRAM  
TH  
4
AC Timing  
66 MHz  
100 MHz  
133 MHz  
Symbol  
Parameter  
Units  
ns  
Min. Max. Min. Max. Min. Max.  
t
SDRAM CLK period  
15.0  
5.6  
5.3  
1.5  
1.5  
1.0  
1.0  
1.0  
1.0  
45  
15.5  
10.0 10.5  
7.5  
1.0  
1.0  
1.5  
1.5  
1.0  
1.0  
1.0  
1.0  
45  
7.8  
SDKP  
t
SDRAM CLK high time  
SDRAM CLK low time  
3.3  
3.1  
SDKH  
t
SDKL  
t
SDRAM CLK rise time  
4.0  
4.0  
5.5  
5.5  
8.0  
8.0  
55  
1.5  
1.5  
1.0  
1.0  
1.0  
1.0  
45  
4.0  
4.0  
5.5  
5.5  
8.0  
8.0  
55  
4.0  
4.0  
5.5  
5.5  
8.0  
8.0  
55  
SDRISE  
V/ns  
t
SDRAM CLK fall time  
SDFALL  
t
SDRAM Buffer LH prop delay  
SDRAM Buffer HL prop delay  
SDRAM Buffer Enable delay  
SDRAM Buffer Disable delay  
PLH  
t
PHL  
ns  
t
,t  
PZL PZH  
t
,t  
PLZ PHZ  
Duty Cycle Measured at 1.5V  
SDRAM Output to Output Skew  
%
ps  
t
250  
250  
250  
SDSKW  
PS8468  
05/03/00  
4
PI6C180B  
Precision 1-18 Clock Buffer  
Figure 1. Clock Waveforms  
Minimum and Maximum Expected Capacitive Loads  
Clock  
Min. Load Max. Load Units  
15 20 pF  
Notes  
SDRAM  
SDRAM DIMM Specification  
Notes:  
1. Maximum rise/fall times are guaranteed at maximum specified load.  
2. Minimum rise/fall times are guaranteed at minimum specified load.  
3. Rise/fall times are specified with pure capacitive load as shown.  
Testing is done with an additional 500resistor in parallel.  
Design Guidelines to Reduce EMI  
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value  
for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall  
time are still within the specified values.  
2. Minimize the number of “vias” of the clock traces.  
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing  
clock traces from plane to plane (refer to rule #2).  
4. Position clock signals away from signals that go to any cables or any external connectors.  
PS8468  
05/03/00  
5
PI6C180B  
Precision 1-18 Clock Buffer  
PCB Layout Suggestion  
Note:  
This is only a suggested layout. There may be alternate solutions  
depending on actual PCB design and layout.  
As a general rule, C1-C11 should be placed as close as possible  
Recommended capacitor values:  
C1-C11 .............. 0.1µF,ceramic  
C12 ................. 22µF  
to their respective V  
.
DD  
PS8468  
05/03/00  
6
PI6C180B  
Precision 1-18 Clock Buffer  
Figure 2. Design Guidelines  
48-Pin SSOP (V Package)  
48  
.395  
.420  
10.03  
10.67  
.291  
.299  
7.39  
7.59  
Gauge Plane  
.010  
0.25  
.02  
.04  
0.51  
1.01  
1
0.381  
0.635  
.015  
.025  
x 45˚  
.008  
0.20  
Nom.  
.620  
.630  
15.75  
16.00  
.110 2.79 Max  
.008 0.20  
.016 0.40  
0-8˚  
.008 0.20  
.0135 0.34  
.025 BSC  
0.635  
X.XX  
X.XX  
DENOTES DIMENSIONS  
IN MILLIMETERS  
Table of Dimensions  
Body  
E (Width) D (Length) A (Height) e (Pin-to-Pin pitch)  
48 pins  
Min.  
0.291  
0.299  
0.620  
0.630  
0.095  
0.110  
0.025  
-
(300 mil)  
Max.  
Ordering Information  
P/N  
Description  
48-pin SSOP Package  
PI6C180BV  
Pericom Semiconductor Corporation  
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com  
PS8468  
05/03/00  
7
配单直通车
PI6C180BVE产品参数
型号:PI6C180BVE
是否无铅:不含铅
是否Rohs认证:符合
生命周期:Obsolete
IHS 制造商:PERICOM SEMICONDUCTOR CORP
零件包装代码:SSOP
包装说明:SSOP, SSOP48,.4
针数:48
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
风险等级:5.35
Is Samacsys:N
系列:6C
输入调节:STANDARD
JESD-30 代码:R-PDSO-G48
JESD-609代码:e3
长度:15.875 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.001 A
湿度敏感等级:1
功能数量:1
反相输出次数:
端子数量:48
实输出次数:18
最高工作温度:70 °C
最低工作温度:
输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY
封装代码:SSOP
封装等效代码:SSOP48,.4
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260
电源:3.3 V
传播延迟(tpd):5.5 ns
认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns
座面最大高度:2.79 mm
子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V
表面贴装:YES
温度等级:COMMERCIAL
端子面层:MATTE TIN
端子形式:GULL WING
端子节距:0.635 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:40
宽度:7.49 mm
最小 fmax:140 MHz
Base Number Matches:1
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