QL8X12B-XPL68C全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

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产品型号QL8X12B-XPL68C的概述

芯片QL8X12B-XPL68C概述 QL8X12B-XPL68C 是一种集成电路芯片，主要用于高性能的数据处理和存储应用。此芯片结合了高级的逻辑结构和灵活的功能扩展能力，广泛应用于数字信号处理、嵌入式系统以及自动化设备。芯片QL8X12B-XPL68C的详细参数芯片的技术参数是其使用和应用的基础。QL8X12B-XPL68C 的主要参数如下： - 工作电压：2.7V 至 5.5V，适用于不同的电源要求 - 包装类型：TQFP（Thin Quad Flat Package），封装紧凑且适合高频应用 - 引脚数量：68 个引脚，提供丰富的输入输出接口 - 工作温度范围：-40℃ 至 +125℃，适合在恶劣环境中工作 - 时钟频率：最高可达 200 MHz，保证高速数据处理能力 - 存储容量：可选配置的存储单元，支持数据缓存和临时存储 - 逻辑密度：具备高达 10 万个逻辑门，支持复杂...

产品型号QL8X12B-XPL68C的Datasheet PDF文件预览

QL8X12B

pASIC^®1 Family

Very-High-Speed CMOS FPGA

Rev B

pASIC

HIGHLIGHTS

Very High Speed – ViaLink metal-to-metal programmable–via

antifuse technology, allows counter speeds over 150 MHz and logic

cell delays of under 2 ns.

High Usable Density – An 8-by-12 array of 96 logic cells provides

1,000 usable ASIC gates (2,000 PLD gates) in 44-pin and 68-pin

PLCC, and 100-pin TQFP packages.

…1,000

usable ASIC gates,

64 I/O pins

Low-Power, High-Output Drive – Standby current typically 2 mA.

A 16-bit counter operating at 100 MHz consumes less than 50 mA.

Minimum IOL of 12 mA and IOH of 8 mA

Low-Cost, Easy-to-Use Design Tools – Designs entered and

simulated using QuickLogic's new QuickWorks development

environment, or with third-party CAE tools including Viewlogic,

Synopsys, Mentor, Cadence and Veribest. Fast, fully automatic place

and route on PC and workstation platforms using QuickLogic

software.

QL8x12B

Block Diagram

96 Logic Cells

Up to 56 prog. I/O cells, 6 Input high-drive cells, 2 Input/Clk (high-drive) cells

4-5

QL8X12B

The QL8x12B is a member of the pASIC 1 Family of very-high-speed

CMOS user-programmable ASIC devices. The 96 logic cell field-

programmable gate array (FPGA) offers 1,000 usable “gate array” gates

(equivalent to 2,000 usable PLD gates) of high-performance general-

purpose logic in 44-pin and 68-pin PLCC packages and 100-pin TQFP

packages.

PRODUCT

SUMMARY

Low-impedance, metal-to-metal, ViaLink interconnect technology

provides nonvolatile custom logic capable of operating above 150 MHz.

Logic cell delays under 2 ns, combined with input delays of under 1.5 ns

and output delays under 3 ns, permit high-density programmable devices

to be used with today’s fastest microprocessors and DSPs.

Designs can be entered using QuickLogic’s QuickWorks Toolkit or most

populart third-party CAE tools. QuickWorks combines Verilog/VHDL

design entry and simulation tools with device-specific place & route and

programming software. Ample on-chip routing channels allow fast, fully

automatic place and route of designs using up to 100% of the logic and

I/O cells, while maintaining fixed pin-outs.

FEATURES

Total of 64 I/O pins

– 56 Bidirectional Input/Output pins

– 6 Dedicated Input/High-Drive pins

– 2 Clock/Dedicated input pins with fanout-independent, low-skew

clock networks

Input + logic cell + output delays under 6 ns

Chip-to-chip operating frequencies up to 110 MHz

Internal state machine frequencies up to 150 MHz

Clock skew < 0.5 ns

Input hysteresis provides high noise immunity

Built-in scan path permits 100% factory testing of logic and I/O cells

and functional testing with Automatic Test Vector Generation

(ATVG) software after programming

Available packages are 44- and 68-pin PLCC, and a 100-pin TQFP

68-pin PLCC compatible with QL12x16B

100-pin TQFP compatible with QL12x16B and QL16x24B

0.65µ CMOS process with ViaLink programming technology

4-6

QL8X12B

Pinout

Diagram

44-pin PLCC

Pinout

Diagram

68-pin PLCC

Pins identified I/SCLK, SM, SO and SI are used during scan path testing operation.

4-7

QL8X12B

Pinout Diagram

100-pin TQFP

4-8

QL8X12B

ABSOLUTE MAXIMUM RATINGS

Supply Voltage..................................–0.5 to 7.0V

Input Voltage .......................–0.5 to VCC +0.5V

ESD Pad Protection................................... ±2000V

DC Input Current ...................................... ±20 mA

Latch-up Immunity ................................ ±200 mA

Storage Temperature....... –65°C to + 150°C

Lead Temperature................................... 300°C

OPERATING RANGE

Symbol

Parameter

Military

Industrial

Commercial Unit

Min

4.5

-55

Max

5.5

Min

4.5

-40

Max

5.5

Min

4.75

Max

5.25

VCC

Supply Voltage

Ambient Temperature

Case Temperature

°C

125

-X Speed Grade

0.4

2.75

1.67

1.43

1.35

0.46

2.55

1.55

1.33

1.25

Delay Factor

-0 Speed Grade

-1 Speed Grade

-2 Speed Grade

0.39

1.82

1.56

DC CHARACTERISTICS over operating range

Symbol

Parameter

Conditions

Min

Max Unit

VIH

VIL

Input HIGH Voltage

Input LOW Voltage

2.0

0.8

IOH = -4 mA

IOH = -8 mA

IOH = -10 µA

IOL = 12 mA*

IOL = 10 µA

3.7

2.4

VCC-0.1

VOH

VOL

Output HIGH Voltage

Output LOW Voltage

0.4

0.1

IOZ

Input Leakage Current

3-State Output Leakage Current

Input Capacitance [1]

VI = VCC or GND

-10

µA

IOS

Output Short Circuit Current [2]

VO = GND

VO = VCC

VI, VIO = VCC or GND

-10

-80

140

ICC

D.C. Supply Current [3]

*IOL = 12 mA for commercial range only. IOL = 8 mA for the industrial and military ranges.

Notes:

[1] Capacitance is sample tested only. CI = 20 pF max on I/(SI).

[2] Only one output at a time. Duration should not exceed 30 seconds.

[3] Commercial temperature grade only. Maximum Icc for industrial grade is 15mA and for military grade is

20 mA. For AC conditions use the formula described in the Section 9 — Power vs Operating Frequency.

[4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25°C.

Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified

in the Operating Range.

[5] These limits are derived from a representative selection of the slowest paths through the pASIC logic cell

including net delays. Worst case delay values for specific paths should be determined from timing analysis

of your particular design .

4-9

QL8X12B

AC CHARACTERISTICS at VCC = 5V, TA = 25°C (K = 1.00)

Logic Cell

Propagation Delays (ns)

Symbol

Parameter

Fanout

tPD

tSU

tCLK

tCWHI

tCWLO

tSET

tRESET

tSW

Combinatorial Delay [5]

Setup Time [5]

Hold Time

Clock to Q Delay

Clock High Time

Clock Low Time

Set Delay

Reset Delay

Set Width

1.7

2.1

0.0

1.0

2.0

1.7

1.5

1.9

1.8

2.1

0.0

1.5

2.0

2.1

1.8

1.9

1.8

2.6

2.1

0.0

1.9

2.0

2.6

2.2

1.9

1.8

3.0

2.1

0.0

2.3

2.0

3.0

2.5

1.9

1.8

4.8

2.1

0.0

4.2

2.0

4.8

3.9

1.9

1.8

tRW

Reset Width

Input Cells

Symbol

Propagation Delays (ns) [4]

Parameter

tIN

High Drive Input Delay [6]

High Drive Input, Inverting Delay [6]

Input Delay (bidirectional pad)

Clock Buffer Delay [7]

2.1

1.4

2.7

2.0

2.2

1.8

2.7

2.0

2.3

2.2

2.8

2.0

2.4

2.5

2.6

2.9

2.0

2.6

2.8

3.4

3.0

2.0

2.9

tINI

3.1

4.2

tIO

tGCK

tGCKHI

tGCKLO

Clock Buffer Min High [7]

Clock Buffer Min Low [7]

Output Cell

Symbol

Propagation Delays (ns) [4]

Output Load Capacitance (pF)

Parameter

3.4

3.7

4.9

4.2

4.7

6.1

5.0

100

5.0

5.6

7.3

5.8

150

tOUTLH

tOUTHL

tPZH

tPZL

tPHZ

Output Delay Low to High

Output Delay High to Low

Output Delay Tri-state to High

Output Delay Tri-state to Low

Output Delay High to Tri-state [8]

Output Delay Low to Tri-state [8]

2.7

2.8

4.0

3.6

2.9

3.3

6.7

7.6

9.7

7.3

tPLZ

Notes:

[6] See High Drive Buffer Table for more information.

[7] Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half

columns used does not affect clock buffer delay.

[8] The following loads are used for tPXZ:

tPHZ

1KΩ

5 pF

1KΩ

tPLZ

5 pF

4-10

QL8X12B

High Drive Buffer

Symbol

Clock Drivers

Wired Together

Propagation Delays (ns) [4]

Parameter

Fanout

4.0

4.9

3.5

tIN

High Drive Input Delay

5.0

4.0

4.8

4.1

5.6

4.8

4.2

5.1

3.7

tINI

High Drive Input,

Inverting Delay

5.2

4.2

5.0

4.3

5.8

5.0

AC Performance

Propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature,

and process variation. The AC Characteristics are a design guide to provide initial timing estimates at

nominal conditions. Worst case estimates are obtained when nominal propagation delays are multiplied

by the appropriate Delay Factor, K, as specified in the Delay Factor table (Operating Range). The

effects of voltage and temperature variation are illustrated in the graphs on page 4-47, K Factor versus

Voltage and Temperature. The pASIC Development Tools incorporate data sheet AC Characteristics

into the QDIF database for pre-place-and-route timing analysis. The SpDE Delay Modeler extracts

specific timing parameters for precise path analysis or simulation results following place and route.

QL 8x12B - 1 PL68 C

ORDERING

INFORMATION

QuickLogic

pASIC device

Operating Range

C = Commercial

I = Industrial

M = Military

pASIC device part number

B = 0.65 micron CMOS

Package Code

PL44 = 44-pin PLCC

PL68 = 68-pin PLCC

PF100 = 100-pin TQFP

Speed Grade

X = quick

0 = fast

1 = faster

2 = fastest

4-11

QL8X12B

4-12

QL8X12B-XPL68C相关文章

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QL8X12B-XPL68C产品参数

型号:	QL8X12B-XPL68C
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	QUICKLOGIC CORP
零件包装代码：	LCC
包装说明：	QCCJ, LDCC68,1.0SQ
针数：	68
Reach Compliance Code：	unknown
风险等级：	5.84
Is Samacsys：	N
其他特性：	MAX 56 I/OS
最大时钟频率：	126.5 MHz
CLB-Max的组合延迟：	12.24 ns
JESD-30 代码：	S-PQCC-J68
JESD-609代码：	e0
长度：	24.1808 mm
湿度敏感等级：	3
可配置逻辑块数量：	96
等效关口数量：	1000
输入次数：	64
逻辑单元数量：	96
输出次数：	56
端子数量：	68
最高工作温度：	70 °C
最低工作温度：
组织：	96 CLBS, 1000 GATES
封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ
封装等效代码：	LDCC68,1.0SQ
封装形状：	SQUARE
封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified
座面最大高度：	4.57 mm
子类别：	Field Programmable Gate Arrays
最大供电电压：	5.25 V
最小供电电压：	4.75 V
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	J BEND
端子节距：	1.27 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	24.1808 mm
Base Number Matches：	1

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产品型号QL8X12B-XPL68C的概述

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