REF19x Series
Stacking Reference ICs for Arbitrary Outputs
A Negative Precision Reference without Precision Resistors
In many current-output CMOS DAC applications, where the
output signal voltage must be of the same polarity as the
reference voltage, it is often required to reconfigure a cur-
rent-switching DAC into a voltage-switching DAC through the
use of a 1.25 V reference, an op amp and a pair of resistors.
Using a current-switching DAC directly requires an additional
operational amplifier at the output to reinvert the signal. A
negative voltage reference is then desirable from the point that
an additional operational amplifier is not required for either
reinversion (current-switching mode) or amplification (voltage
switching mode) of the DAC output voltage. In general, any
positive voltage reference can be converted into a negative volt-
age reference through the use of an operational amplifier and a
pair of matched resistors in an inverting configuration. The
disadvantage to that approach is that the largest single source of
error in the circuit is the relative matching of the resistors used.
Some applications may require two reference voltage sources
that are a combined sum of standard outputs. The circuit of
Figure 19 shows how this “stacked output” reference can be
implemented.
OUTPUT TABLE
U1/U2
V
(V)
V
(V)
OUT1
OUT2
REF192/REF192
REF192/REF194
REF192/REF195
2.5
2.5
2.5
5.0
7.0
7.5
+V
OUT2
S
V
S
> V
+0.15V
C1
0.1F
U2
+V
REF19x
OUT2
(SEE TABLE)
C2
V
O
(U2)
1F
C3
0.1F
U1
+V
OUT1
REF19x
R1
3.9k⍀
(SEE TEXT)
(SEE TABLE)
C4
1F
The circuit illustrated in Figure 18 avoids the need for tightly
matched resistors with the use of an active integrator circuit. In
this circuit, the output of the voltage reference provides the
input drive for the integrator. The integrator, to maintain cir-
cuit equilibrium, adjusts its output to establish the proper rela-
tionship between the reference’s VOUT and GND. Thus, any
desired negative output voltage can be chosen by simply sub-
stituting for the appropriate reference IC. The sleep feature is
maintained in the circuit with the simple addition of a PNP
transistor and a 10 kΩ resistor. One caveat with this approach
should be mentioned: although rail-to-rail output amplifiers
work best in the application, these operational amplifiers require
a finite amount (mV) of headroom when required to provide
any load current. The choice for the circuit’s negative supply
should take this issue into account.
V
O
(U1)
V
V
IN
OUT
COMMON
COMMON
Figure 19. Stacking Voltage References with the REF19x
Two reference ICs are used, fed from a common unregulated
input, VS. The outputs of the individual ICs are simply con-
nected in series as shown, which provides two output voltages,
VOUT1 and VOUT2. VOUT1 is the terminal voltage of U1, while
VOUT2 is the sum of this voltage and the terminal voltage of U2.
U1 and U2 are simply chosen for the two voltages that supply
the required outputs (see table). If, for example, both U1 and
U2 are REF192s, the two outputs are 2.5 V and 5.0 V.
While this concept is simple, some cautions are in order. Since
the lower reference circuit must sink a small bias current from
U2 (50 µA–100 µA), plus the base current from the series PNP
output transistor in U2, either the external load of U1 or R1
must provide a path for this current. If the U1 minimum load is
not well defined, resistor R1 should be used, set to a value that
will conservatively pass 600 µA of current with the applicable
VOUT1 across it. Note that the two U1 and U2 reference circuits
are locally treated as macrocells, each having its own bypasses at
input and output for best stability. Both U1 and U2 in this
circuit can source dc currents up to their full rating. The mini-
mum input voltage, VS, is determined by the sum of the out-
puts, VOUT2, plus the dropout voltage of U2.
V
IN
10k⍀
SLEEP
TTL/CMOS
2N3906
V
IN
1F
+5V
1k⍀
1F
V
SLEEP
REF
REF19x
GND
100⍀
A1
–V
REF
10k⍀
100k⍀
–5V
A1 = 1/2 OP295,
1/2 OP291
A related variation on stacking two three-terminal references is
shown in Figure 19, where U1, a REF192, is stacked with a
two-terminal reference diode such as the AD589. Like the
three-terminal stacked reference above, this circuit provides two
outputs, VOUT1 and VOUT2, which are the individual terminal
voltages of D1 and U1 respectively. Here this is 1.235 and 2.5,
which provides a VOUT2 of 3.735 V. When using two-terminal
reference diodes such as D1, the rated minimum and maximum
device currents must be observed and the maximum load cur-
rent from VOUT1 can be no greater than the current set up by R1
and VO(U1). In the case with VO(U1) equal to 2.5 V, R1 provides
a 500 µA bias to D1, so the maximum load current available at
VOUT1 is 450 µA or less.
Figure 18. A Negative Precision Voltage Reference
Uses No Precision Resistors
REV. D
–19–