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产品型号SC1185ACSW的概述

芯片SC1185ACSW概述 SC1185ACSW是一款集成电路（IC），广泛应用于电源管理系统中。作为一种高效的电压调节器，它提供精准的输出电压，能够高效地为多种电子设备供电。SC1185ACSW常用于手机、平板电脑、笔记本电脑等设备中，满足它们对高稳定性和高效能的电源要求。芯片SC1185ACSW的详细参数 SC1185ACSW具有多项关键参数，使其在市场中具有竞争力。其工作电压范围为2.5V至5.5V，能够支持不同的输入源。输出电压可以根据需求进行调节，输出电流能力达到500mA，适用于各种需要中等功耗的应用场合。芯片具有高达90%的效率，在负载变化时仍能保持良好的电源稳定性。此外，SC1185ACSW配备了热保护、过流保护等安全特性，确保设备在多种工作条件下安全运行。芯片SC1185ACSW的厂家、包装与封装 SC1185ACSW由专业的半导体制造商设计和生产。这款芯片不...

产品型号SC1185ACSW的Datasheet PDF文件预览

PROGRAMMABLE SYNCHRONOUS DC/DC

CONVERTER, DUAL LOW DROPOUT

REGULATOR CONTROLLER

SC1185

SC1185A

PRELIMINARY - January 6, 1999

TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com

DESCRIPTION

FEATURES

The SC1185 combines a synchronous voltage mode

controller with two low-dropout linear regulators

providing most of the circuitry necessary to

•

Synchronous design, enables no heatsink solution

95% efficiency (switching section)

5 bit DAC for output programmability

On chip power good function

implement three DC/DC converters for powering

advanced microprocessors such as Pentium^®II .

Designed for Intel Pentium^®ll requirements

1.5V, 2.5V @ 1% for linear section

1.265V ± 1.5% Reference available

The SC1185 switching section features an integrated

5 bit D/A converter, pulse by pulse current limiting,

integrated power good signaling, and logic compatible

shutdown. The SC1185 switching section operates at

a fixed frequency of 140kHz, providing an optimum

compromise between size, efficiency and cost in the

intended application areas. The integrated D/A con-

verter provides programmability of output voltage

from 2.0V to 3.5V in 100mV increments and 1.30V to

2.05V in 50mV increments with no external compo-

nents.

APPLICATIONS

•

Pentium^®ll microprocessor supplies

Flexible motherboards

1.3V to 3.5V microprocessor supplies

Programmable triple power supplies

ORDERING INFORMATION

Linear

Voltage

Temp.

Range (T_J)

Part Number⁽¹⁾

Package

The SC1185 linear sections are low dropout regula-

tors supplying 1.5V for GTL bus and 2.5V for non-

GTL I/O. The Reference voltage is made available for

external linear regulators.

SC1185CSW

SC1185ACSW⁽²⁾SO-24 1.5V/2.5V 0° to 125°C

SO-24 1.5V/2.5V 0° to 125°C

Note:

(1) Add suffix ‘TR’ for tape and reel.

(2) SC1185A provides improved output tolerance. See

Output Voltage Table.

PIN CONFIGURATION

BLOCK DIAGRAM

VCC

CS- CS+

BSTH

REF.

D/A

Top View

VID4

VID3

VID2

VID1

VID0

AGND

GATE2

LDOV

VID0

VID1

VID2

GATE1

LDOS1

LDOS2

PGNDH

VCC

REF

PWRGOOD

CS-

VID3

VID4

VOSENSE

BSTH

BSTL

CS+

PGNDH

PWRGOOD

BSTL

PGNDL

(24 Pin SOIC)

PGNDL

LDOS1

GATE1

FET

CONTROLLER

2.5V/ADJ.

FET

CONTROLLER

1.5V/ADJ.

1.265V

REF.

LDOV

REF

GATE2 LDOS2

AGND

Pentium is a registered trademark of Intel Corporation

652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC

CONVERTER, DUAL LOW DROPOUT

REGULATOR CONTROLLER

SC1185

SC1185A

PRELIMINARY - January 6, 1999

ABSOLUTE MAXIMUM RATINGS

Parameter

VCC to GND

Symbol

Maximum

-0.3 to +7

Units

V_IN

PGND to GND

± 1

BST to GND

Operating Temperature Range

Junction Temperature Range

-0.3 to +15

0 to +70

0 to +125

°C

T_A

T_J

Storage Temperature Range

Lead Temperature (Soldering) 10 seconds

Thermal Impedance Junction to Ambient

T_STG

T_L

-65 to +150

°C

°C/W

300

θ_JA

Thermal Impedance Junction to Case

°C/W

θ_JC

ELECTRICAL CHARACTERISTICS

Unless specified: V_CC= 4.75V to 5.25V; GND = P_GND= 0V; V_OSENSE= V_O; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; T_A= 0 to 70°C

PARAMETER

CONDITIONS

MIN TYP MAX UNITS

Switching Section

Output Voltage

I_O= 2A in Application Circuit

VCC

See Output Voltage Table

Supply Voltage

4.5

Supply Current

VCC = 5.0V

Load Regulation

I_O= 0.8A to 15A

Line Regulation

±0.15

Current Limit Voltage

Oscillator Frequency

Oscillator Max Duty Cycle

Peak DH Sink/Source Current

125

kHz

140

160

BSTH-DH = 4.5V, DH-PGNDH = 3.1V

DH-PGNDH = 1.5V 100

Peak DL Sink/Source Current

BSTL-DL = 4.5V, DL-PGNDL = 3.1V

DL-PGNDL = 1.5V 100

Gain (A_OL)

VOSENSE to V_O

µA

VID Source Current

VID Leakage

VIDx ≤ 2.4V

VIDx = 5V

Power good threshold voltage

Dead time

112

100

Linear Sections

Quiescent current

Output Voltage LDO1

Output Voltage LDO2

Reference Voltage

Gain (A_OL)

LDOV = 12V

2.469 2.500 2.531

1.481 1.500 1.519

1.246 1.265 1.284

Iref ≤ 100µA

LDOS (1,2) to GATE (1,2)

I_O= 0 to 8A

Load Regulation

0.3

Line Regulation

Output Impedance

Gate Pulldown Impedance

VOSENSE Impedance

_GATE= 6.5V

1.5

kΩ

GATE(1,2)-AGND;VCC=LDOV=0V

300

750

652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC

CONVERTER, DUAL LOW DROPOUT

REGULATOR CONTROLLER

SC1185

SC1185A

PRELIMINARY - January 6, 1999

PIN DESCRIPTION

Pin Pin Name

Pin Function

Small Signal Analog and Digital Ground

Gate Drive Output LDO1

Sense Input for LDO1

Sense Input for LDO2

Input Voltage

AGND

GATE1

LDOS1

LDOS2

VCC

Top View

REF

Buffered Reference Voltage output

Open collector logic output, high if V_O

AGND

GATE2

LDOV

VID0

VID1

VID2

GATE1

LDOS1

LDOS2

PWRGOOD⁽¹⁾within 10% of setpoint

CS-

Current Sense Input (negative)

VCC

REF

PWRGOOD

CS-

VID3

VID4

CS+

Current Sense Input (positive)

Power Ground for High Side Switch

High Side Driver Output

10 PGNDH

11 DH

VOSENSE

BSTH

BSTL

CS+

PGNDH

PGNDL

12 PGNDL

13 DL

Power Ground for Low Side Switch

Low Side Driver Output

14 BSTL

15 BSTH

16 EN⁽¹⁾

Supply for Low Side Driver

Supply for High Side Driver

Logic low shuts down the converter;

High or open for normal operation.

Top end of internal feedback chain

(24 Pin SOIC)

17 VOSENSE

VID4⁽¹⁾

Programming Input (MSB)

Programming Input

VID3⁽¹⁾

VID2⁽¹⁾

VID1⁽¹⁾

Programming Input

VID0⁽¹⁾

Programming Input (LSB)

+12V for LDO section

Gate Drive Output LDO2

Note:

23 LDOV

24 GATE2

(1) All logic level inputs and outputs are open

collector TTL compatible.

652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC

CONVERTER, DUAL LOW DROPOUT

REGULATOR CONTROLLER

SC1185

SC1185A

PRELIMINARY - January 6, 1999

OUTPUT VOLTAGE

Unless specified: 4.75V < VCC < 5.25V; GND = PGND = 0V; VOSENSE = V_O; 0mV < (CS+-CS-) < 60mV; = 0°C < T_j< 85°C

Standard

TYP

“A” Version

TYP

PARAMETER

VID

43210

MIN

MAX

MIN

MAX

UNITS

Output Voltage

01111

01110

01101

01100

01011

01010

01001

01000

00111

00110

00101

00100

00011

00010

00001

00000

11111

11110

11101

11100

11011

11010

11001

11000

10111

10110

10101

10100

10011

10010

10001

10000

1.277

1.326

1.375

1.424

1.478

1.527

1.576

1.625

1.675

1.724

1.782

1.832

1.881

1.931

1.980

2.030

1.970

2.069

2.167

2.266

2.364

2.463

2.561

2.660

2.758

2.842

2.940

3.038

3.136

3.234

3.332

3.430

1.300

1.350

1.400

1.450

1.500

1.550

1.600

1.650

1.700

1.750

1.800

1.850

1.900

1.950

2.000

2.050

2.000

2.100

2.200

2.300

2.400

2.500

2.600

2.700

2.800

2.900

3.000

3.100

3.200

3.300

3.400

3.500

1.323

1.374

1.425

1.476

1.523

1.573

1.624

1.675

1.726

1.776

1.818

1.869

1.919

1.970

2.020

2.071

2.030

2.132

2.233

2.335

2.436

2.538

2.639

2.741

2.842

2.958

3.060

3.162

3.264

3.366

3.468

3.570

1.287

1.337

1.386

1.436

1.485

1.535

1.584

1.634

1.683

1.733

1.782

1.832

1.881

1.931

1.980

2.030

1.970

2.069

2.167

2.266

2.364

2.463

2.561

2.660

2.758

2.842

2.940

3.038

3.136

3.234

3.332

3.430

1.300

1.350

1.400

1.450

1.500

1.550

1.600

1.650

1.700

1.750

1.800

1.850

1.900

1.950

2.000

2.050

2.000

2.100

2.200

2.300

2.400

2.500

2.600

2.700

2.800

2.900

3.000

3.100

3.200

3.300

3.400

3.500

1.313

1.364

1.414

1.465

1.515

1.566

1.616

1.667

1.717

1.768

1.818

1.869

1.919

1.970

2.020

2.071

2.030

2.132

2.233

2.335

2.436

2.538

2.639

2.741

2.842

2.958

3.060

3.162

3.264

3.366

3.468

3.570

652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC

CONVERTER, DUAL LOW DROPOUT

REGULATOR CONTROLLER

SC1185

SC1185A

PRELIMINARY - January 6, 1999

APPLICATION CIRCUIT

652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC

CONVERTER, DUAL LOW DROPOUT

REGULATOR CONTROLLER

SC1185

SC1185A

PRELIMINARY - January 6, 1999

MATERIALS LIST

Qty. Reference

Part/Description

C1,C5,C13,C18 0.1µF Ceramic

C2,C3,C14-C17 1500µF/6.3V

Vendor

Various

SANYO

Notes

MV-GX or equiv. Low ESR

1000µF

330µF/6.3V

4µH

C11,C21

Various

8 Turns 16AWG on MICROMETALS T50-52D core

Q1,Q2

See notes

See notes FET selection requires trade-off between efficiency and

cost. Absolute maximum R_DS(ON)= 22 mΩ for Q1,Q2

IRLML2803

IRFZ14S

.25Ω 30V SOT23 (or equavilent)

Or equivalent

IRC

OAR-1 Series

5mΩ

Various

SEMTECH

2.32kΩ, 1%, 1/8W

1kΩ, 1%, 1/8W

10Ω, 5%, 1/8W

SC1185CSW

652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC

CONVERTER, DUAL LOW DROPOUT

REGULATOR CONTROLLER

SC1185

SC1185A

PRELIMINARY - January 6, 1999

95%

90%

85%

80%

95%

90%

85%

80%

2.8V Std

3.5V Std

2.8V Sync

3.5V Sync

2.8V Sync Lo Rds

75%

3.5V Sync Lo Rds

75%

70%

Io (Amps)

Typical Efficiency at Vo=3.5V

Typical Efficiency at Vo=2.8V

95%

90%

85%

90%

85%

80%

2.0V Std

2.0V Sync

2.5V Std

2.5V Sync

2.0V Sync Lo Rds

75%

2.5V Sync Lo Rds

75%

70%

Io (Amps)

Typical Efficiency at Vo=2.5V

Typical Efficiency at Vo=2.0V

Typical Ripple, Vo=2.8V, Io=10A

Transient Response Vo=2.8V, Io=300mA to 10A

652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC

CONVERTER, DUAL LOW DROPOUT

REGULATOR CONTROLLER

SC1185

SC1185A

PRELIMINARY - January 6, 1999

as small as possible. This loop contains all the high cur-

rent, fast transition switching. Connections should be as

wide and as short as possible to minimize loop induc-

tance. Minimizing this loop area will a) reduce EMI, b)

lower ground injection currents, resulting in electrically

“cleaner” grounds for the rest of the system and c) mini-

mize source ringing, resulting in more reliable gate

switching signals.

LAYOUT GUIDELINES

Careful attention to layout requirements are necessary

for successful implementation of the SC1185 PWM

controller. High currents switching at 140kHz are pre-

sent in the application and their effect on ground plane

voltage differentials must be understood and mini-

mized.

1). The high power parts of the circuit should be laid out

first. A ground plane should be used, the number and

position of ground plane interruptions should be such

as to not unnecessarily compromise ground plane in-

tegrity. Isolated or semi-isolated areas of the ground

plane may be deliberately introduced to constrain

ground currents to particular areas, for example the in-

put capacitor and bottom FET ground.

3). The connection between the junction of Q1, Q2 and

the output inductor should be a wide trace or copper

region. It should be as short as practical. Since this

connection has fast voltage transitions, keeping this

connection short will minimize EMI. The connection be-

tween the output inductor and the sense resistor should

be a wide trace or copper area, there are no fast volt-

age or current transitions in this connection and length

is not so important, however adding unnecessary

impedance will reduce efficiency.

2). The loop formed by the Input Capacitor(s) (Cin), the

Top FET (Q1) and the Bottom FET (Q2) must be kept

12V IN

AGND

GATE1

LDOS1

LDOS2

VCC

GATE2

LDVO

VID0

2.32k

Cin

1.00k

VID1

0.1uF

5mOhm

VID2

Vout

REF

VID3

4uH

PWRGOOD

CS-

VID4

Cout

VOSENSE

CS+

PGNDH

BSTH

BSTL

PGNDL

SC1185

Heavy lines indicate

high current paths.

3.3V

Vo Lin1

Cout Lin1

Cin Lin

Vo Lin2

Cout Lin2

Layout diagram for the SC1185

652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC

CONVERTER, DUAL LOW DROPOUT

REGULATOR CONTROLLER

SC1185

SC1185A

PRELIMINARY - January 6, 1999

4) The Output Capacitor(s) (Cout) should be located

as close to the load as possible, fast transient load

currents are supplied by Cout only, and connections

between Cout and the load must be short, wide cop-

per areas to minimize inductance and resistance.

supply through a 10Ω resistor, the Vcc pin should be

decoupled directly to AGND by a 0.1µF ceramic ca-

pacitor, trace lengths should be as short as possible.

7) The Current Sense resistor and the divider across

it should form as small a loop as possible, the traces

running back to CS+ and CS- on the SC1185 should

run parallel and close to each other. The 0.1µF ca-

pacitor should be mounted as close to the CS+ and

CS- pins as possible.

5) The SC1185 is best placed over a quiet ground

plane area, avoid pulse currents in the Cin, Q1, Q2

loop flowing in this area. PGNDH and PGNDL should

be returned to the ground plane close to the package.

The AGND pin should be connected to the ground

side of (one of) the output capacitor(s). If this is not

possible, the AGND pin may be connected to the

ground path between the Output Capacitor(s) and the

Cin, Q1, Q2 loop. Under no circumstances should

AGND be returned to a ground inside the Cin, Q1, Q2

loop.

8) Ideally, the grounds for the two LDO sections

should be returned to the ground side of (one of) the

output capacitor(s).

6) Vcc for the SC1185 should be supplied from the 5V

Vout

Currents in various parts of the power section

652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC

CONVERTER, DUAL LOW DROPOUT

REGULATOR CONTROLLER

SC1185

SC1185A

PRELIMINARY - January 6, 1999

fast enough to reduce the voltage dropped across the

COMPONENT SELECTION

ESR at a faster rate than the capacitor sags, hence en-

suring a good recovery from transient with no additional

excursions.

We must also be concerned with ripple current in the

output inductor and a general rule of thumb has been to

allow 10% of maximum output current as ripple current.

Note that most of the output voltage ripple is produced

by the inductor ripple current flowing in the output capac-

itor ESR. Ripple current can be calculated from:

SWITCHING SECTION

OUTPUT CAPACITORS - Selection begins with the

most critical component. Because of fast transient load

current requirements in modern microprocessor core

supplies, the output capacitors must supply all transient

load current requirements until the current in the output

inductor ramps up to the new level. Output capacitor

ESR is therefore one of the most important criteria. The

maximum ESR can be simply calculated from:

I_L

V_t

RIPPLE

4 L f_OSC

R_ESR

≤

I_t

Ripple current allowance will define the minimum permit-

ted inductor value.

Where

V_t= Maximum transient voltage excursion

I_t= Transient current step

POWER FETS - The FETs are chosen based on several

criteria with probably the most important being power

dissipation and power handling capability.

TOP FET - The power dissipation in the top FET is a

combination of conduction losses, switching losses and

bottom FET body diode recovery losses.

For example, to meet a 100mV transient limit with a

10A load step, the output capacitor ESR must be less

than 10mΩ. To meet this kind of ESR level, there are

three available capacitor technologies.

a) Conduction losses are simply calculated as:

P_COND= I_O²R_DS(on)

Each Capacitor

Total

where

Technology

ESR Qty.

ESR

(mΩ)

(µF)

Rqd. (µF)

(mΩ)

V_O

δ = duty cycle ≈

Low ESR Tantalum

OS-CON

330

2000

990

8.3

8.8

330

b) Switching losses can be estimated by assuming a

switching time, if we assume 100ns then:

Low ESR Aluminum

1500

7500

P_SW= I_OV_IN10 ⁻²

The choice of which to use is simply a cost/perfor-

mance issue, with Low ESR Aluminum being the

cheapest, but taking up the most space.

or more generally,

INDUCTOR - Having decided on a suitable type and

value of output capacitor, the maximum allowable

value of inductor can be calculated. Too large an in-

ductor will produce a slow current ramp rate and will

cause the output capacitor to supply more of the tran-

sient load current for longer - leading to an output volt-

age sag below the ESR excursion calculated above.

The maximum inductor value may be calculated from:

I_OV_IN(t_r+ t_f) f_OSC

P_SW

c) Body diode recovery losses are more difficult to esti-

mate, but to a first approximation, it is reasonable to as-

sume that the stored charge on the bottom FET body

diode will be moved through the top FET as it starts to

turn on. The resulting power dissipation in the top FET

will be:

R_ESR

I_t

L ≤

(

V_IN− V_O

)

P_RR= Q_RRV_INf_OSC

The calculated maximum inductor value assumes 100% To a first order approximation, it is convenient to only

duty cycle, so some allowance must be made. Choosing consider conduction losses to determine FET suitability.

an inductor value of 50 to 75% of the calculated maxi-

mum will guarantee that the inductor current will ramp

For a 5V in; 2.8V out at 14.2A requirement, typical FET

losses would be:

652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC

CONVERTER, DUAL LOW DROPOUT

REGULATOR CONTROLLER

SC1185

SC1185A

PRELIMINARY - January 6, 1999

Using 1.5X Room temp R_DS(ON)to allow for temperature

rise.

INPUT CAPACITORS - since the RMS ripple current in

the input capacitors may be as high as 50% of the out-

put current, suitable capacitors must be chosen ac-

cordingly. Also, during fast load transients, there may

be restrictions on input di/dt. These restrictions require

useable energy storage within the converter circuitry,

either as extra output capacitance or, more usually,

additional input capacitors. Choosing low ESR input

capacitors will help maximize ripple rating for a given

size.

FET type

P_D(W) Package

_DS(on)(mΩ)

IRL34025 15

1.69

1.19

2.26

D²PAK

SO-8

IRL2203

Si4410

10.5

BOTTOM FET - Bottom FET losses are almost entirely

due to conduction. The body diode is forced into conduc-

tion at the beginning and end of the bottom switch con-

duction period, so when the FET turns on and off, there

is very little voltage across it, resulting in low switching

losses. Conduction losses for the FET can be deter-

mined by:

_COND=I_O²R_DS(on)(1−δ)

For the example above:

FET type

P_D(W) Package

_DS(on)(mΩ)

IRL34025 15

1.33

0.93

1.77

D²PAK

SO-8

IRL2203

Si4410

10.5

Each of the package types has a characteristic thermal

impedance, for the TO-220 package, thermal impedance

is mostly determined by the heatsink used. For the sur-

face mount packages on double sided FR4, 2 oz printed

circuit board material, thermal impedances of 40^oC/W

for the D²PAK and 80^oC/W for the SO-8 are readily

achievable. The corresponding temperature rise is de-

tailed below:

Temperature rise (^oC)

FET type Top FET

IRL34025 67.6

Bottom FET

53.2

37.2

141.6

IRL2203

Si4410

47.6

180.8

It is apparent that single SO-8 Si4410 are not adequate for

this application, but by using parallel pairs in each posi-

tion, power dissipation will be approximately halved and

temperature rise reduced by a factor of 4.

652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC

CONVERTER, DUAL LOW DROPOUT

REGULATOR CONTROLLER

SC1185

SC1185A

PRELIMINARY - January 6, 1999

OUTLINE DRAWING

JEDEC MS-013AD

B17104B

652 MITCHELL ROAD NEWBURY PARK CA 91320

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