SN74LVT240APWR全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

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产品型号SN74LVT240APWR的概述

芯片SN74LVT240APWR的概述 SN74LVT240APWR是一款由德州仪器（Texas Instruments）生产的高性能八路缓冲器/驱动器，属于74LVT系列逻辑器件。这款芯片在广泛的电子应用中占有重要地位，尤其是在需要数据缓冲和信号驱动的复杂电路中。SN74LVT240APWR能够在高频条件下稳定工作，提供优良的信号完整性和低功耗是其主要优势之一。 SN74LVT240APWR的主要特点包括双向缓冲能力、TTL兼容的输入和输出电平、工作电压范围的灵活性等。它的应用场合涵盖了数据总线的缓冲、高速通信设备、数字信号处理器（DSP）的接入等。由于这些特点，这款芯片经常在各种电子设备和系统中得到应用。芯片SN74LVT240APWR的详细参数 SN74LVT240APWR的详细技术参数如下： - 工作电压范围: 3.0V至3.6V - 输入电压范围: 0V至5.5V - 输出...

产品型号SN74LVT240APWR的Datasheet PDF文件预览

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ꢊ ꢋꢊ ꢌꢅ ꢉꢍꢆ ꢎ ꢏꢆꢉꢄ ꢍꢐꢑ ꢑ ꢒꢓ ꢔꢕ ꢓꢖ ꢅ ꢒ ꢓ

ꢗ ꢖꢆ ꢘ ꢊ ꢌꢀꢆꢉꢆ ꢒ ꢎ ꢐꢆ ꢙ ꢐꢆꢀ

SCBS134K − SEPTEMBER 1992 − REVISED JANUARY 2004

DB, DGV, DW, NS, OR PW PACKAGE

(TOP VIEW)

Supports Mixed-Mode Signal Operation

(5-V Input and Output Voltages With 3.3-V

)

1OE

1A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1

GND

Supports Unregulated Battery Operation

Down To 2.7 V

2OE

1Y1

2A4

1Y2

2A3

1Y3

Typical V

<0.8 V at V

(Output Ground Bounce)

OLP

= 3.3 V, T = 25°C

and Power-Up 3-State Support Hot

off

Insertion

13 2A2

12 1Y4

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

2A1

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

This octal buffer and line driver is designed specifically for low-voltage (3.3-V) V

capability to provide a TTL interface to a 5-V system environment.

operation, but with the

The SN74LVT240A is organized as two 4-bit buffer/line drivers with separate output-enable (OE) inputs. When

OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the

high-impedance state.

When V

is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 1.5 V, OE should be tied to V

the minimum value of the resistor is determined by the current-sinking capability of the driver.

through a pullup resistor;

This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry

off

disables the outputs, preventing damaging current backflow through the device when it is powered down. The

power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,

which prevents driver conflict.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

Tube

SN74LVT240ADW

SN74LVT240ADWR

SN74LVT240ANSR

SN74LVT240ADBR

SN74LVT240APW

SN74LVT240APWR

SN74LVT240ADGVR

SOIC − DW

LVT240A

Tape and reel

Tube

SOP − NS

LVT240A

LX240A

SSOP − DB

−40°C to 85°C

TSSOP − PW

TVSOP − DGV

LX240A

Tape and reel

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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ꢥ

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢊꢋ ꢊꢌꢅ ꢉ ꢍ ꢆ ꢎꢏ ꢆꢉꢄ ꢍꢐ ꢑꢑ ꢒꢓ ꢔꢕ ꢓꢖ ꢅ ꢒꢓ

ꢗꢖ ꢆ ꢘ ꢊ ꢌꢀꢆꢉꢆ ꢒ ꢎꢐꢆ ꢙꢐ ꢆꢀ

SCBS134K − SEPTEMBER 1992 − REVISED JANUARY 2004

FUNCTION TABLE

(each 4-bit buffer)

INPUTS

OUTPUT

logic diagram (positive logic)

1OE

2OE

2A1

1Y1

1Y2

1Y3

1Y4

2Y1

2Y2

2Y3

2Y4

1A1

1A2

2A2

2A3

2A4

1A3

1A4

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Voltage range applied to any output in the high-impedance

or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V

+ 0.5 V

Current into any output in the low state, I

Current into any output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

Output clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W

DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W

DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W

NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W

PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and V > V

3. The package thermal impedance is calculated in accordance with JESD 51-7.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢗ ꢖꢆ ꢘ ꢊ ꢌꢀꢆꢉꢆ ꢒ ꢎ ꢐꢆ ꢙ ꢐꢆꢀ

SCBS134K − SEPTEMBER 1992 − REVISED JANUARY 2004

recommended operating conditions (see Note 4)

MIN

2.7

MAX

UNIT

Supply voltage

3.6

High-level input voltage

Low-level input voltage

Input voltage

0.8

5.5

−32

High-level output current

Low-level output current

Input transition rise or fall rate

Power-up ramp rate

ns/V

µs/V

°C

∆t/∆v

∆t/∆V

Outputs enabled

200

−40

Operating free-air temperature

NOTE 4: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

†

TYP

PARAMETER

TEST CONDITIONS

I = −18 mA

MIN

MAX

UNIT

= 2.7 V,

−1.2

= 2.7 V to 3.6 V,

= 2.7 V,

= −100 µA

= − 8 mA

= −32 mA

= 100 µA

= 24 mA

= 16 mA

= 32 mA

= 64 mA

−0.2

2.4

= 3 V,

0.2

0.5

0.4

0.5

0.55

= 2.7 V

= 3 V

= 0 or 3.6 V,

V = 5.5 V

V = V

or GND

Control inputs

Data inputs

µA

V = V

= 3.6 V

V = 0

−5

100

= 0,

V or V = 0 to 4.5 V

µA

off

= 3.6 V,

= 0 to 1.5 V,

= 3 V

OZH

OZL

OZPU

= 0.5 V

−5

100

= 0.5 V to 3 V,

OE = don’t care

100

0.19

µA

= 1.5 V to 0,

OE = don’t care

Outputs high

OZPD

= 3.6 V,

= 0,

Outputs low

‡

V = V

or GND

Outputs disabled

0.19

0.2

= 3 V to 3.6 V, One input at V

− 0.6 V, Other inputs at V

or GND

∆I

V = 3 V or 0

= 3 V or 0

†

‡

All typical values are at V

= 3.3 V, T = 25°C.

This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V

or GND.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢃ ꢈꢉ

ꢊꢋ ꢊꢌꢅ ꢉ ꢍ ꢆ ꢎꢏ ꢆꢉꢄ ꢍꢐ ꢑꢑ ꢒꢓ ꢔꢕ ꢓꢖ ꢅ ꢒꢓ

ꢗꢖ ꢆ ꢘ ꢊ ꢌꢀꢆꢉꢆ ꢒ ꢎꢐꢆ ꢙꢐ ꢆꢀ

SCBS134K − SEPTEMBER 1992 − REVISED JANUARY 2004

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, C = 50 pF (unless otherwise noted) (see Figure 1)

= 3.3 V

0.3 V

= 2.7 V

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

†

MIN TYP

MAX

3.8

MIN

MAX

4.6

4.2

5.6

1.1

1.3

1.1

1.4

2.2

2.6

2.7

2.9

PLH

PHL

PZH

PZL

PHZ

PLZ

4.6

4.4

4.3

4.6

4.3

1.8

†

All typical values are at V

= 3.3 V, T = 25°C.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢗ ꢖꢆ ꢘ ꢊ ꢌꢀꢆꢉꢆ ꢒ ꢎ ꢐꢆ ꢙ ꢐꢆꢀ

SCBS134K − SEPTEMBER 1992 − REVISED JANUARY 2004

PARAMETER MEASUREMENT INFORMATION

6 V

Open

GND

TEST

500 Ω

From Output

Under Test

Open

6 V

PLH PHL

PLZ PZL

= 50 pF

GND

PHZ PZH

500 Ω

(see Note A)

2.7 V

0 V

LOAD CIRCUIT

Timing Input

Data Input

1.5 V

2.7 V

0 V

Input

1.5 V

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

2.7 V

0 V

2.7 V

0 V

Output

Control

1.5 V

Input

PLZ

PZL

PHL

PLH

PHL

Output

Waveform 1

S1 at 6 V

3 V

1.5 V

Output

+ 0.3 V

(see Note B)

PZH

PHZ

PLH

Output

Waveform 2

S1 at GND

− 0.3 V

1.5 V

Output

≈0 V

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A. includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

13-Sep-2005

PACKAGING INFORMATION

Orderable Device

SN74LVT240ADBG4

SN74LVT240ADBR

SN74LVT240ADBRE4

SN74LVT240ADBRG4

SN74LVT240ADGVR

SN74LVT240ADGVRE4

SN74LVT240ADW

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SSOP

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SSOP

TVSOP

SOIC

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

DGV

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LVT240ADWE4

SN74LVT240ADWR

SN74LVT240ADWRE4

SN74LVT240ANSR

SN74LVT240ANSRE4

SN74LVT240APW

SOIC

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LVT240APWE4

SN74LVT240APWR

SN74LVT240APWRE4

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

no Sb/Br)

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

13-Sep-2005

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23

0,13

0,07

0,40

0,16 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–ā8°

0,75

0,50

Seating Plane

0,08

0,15

0,05

1,20 MAX

PINS **

DIM

A MAX

A MIN

3,70

3,50

3,70

3,50

5,10

4,90

5,10

4,90

7,90

7,70

9,80

9,60

11,40

11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.

D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

0,15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

0,25

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

0,10

0,65

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–8°

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

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SN74LVT240APWR产品参数

型号:	SN74LVT240APWR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	TSSOP
包装说明：	TSSOP-20
针数：	20
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	1.08
Samacsys Confidence：	3
Samacsys Status：	Released
Samacsys PartID：	744858
Samacsys Pin Count：	20
Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Small Outline Packages
Samacsys Footprint Name：	pw(r-pdso-g20)
Samacsys Released Date：	2020-03-09 10:22:26
Is Samacsys：	N
控制类型：	ENABLE LOW
计数方向：	UNIDIRECTIONAL
系列：	LVT
JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e4
长度：	6.5 mm
负载电容（CL）：	50 pF
逻辑集成电路类型：	BUS DRIVER
最大I（ol）：	0.064 A
湿度敏感等级：	1
位数：	4
功能数量：	2
端口数量：	2
端子数量：	20
最高工作温度：	85 °C
最低工作温度：	-40 °C
输出特性：	3-STATE
输出极性：	INVERTED
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP20,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：	TR
峰值回流温度（摄氏度）：	260
电源：	3.3 V
最大电源电流（ICC）：	0.005 mA
Prop。Delay @ Nom-Sup：	4 ns
传播延迟（tpd）：	4.6 ns
认证状态：	Not Qualified
座面最大高度：	1.2 mm
子类别：	Bus Driver/Transceivers
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	2.7 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
翻译：	N/A
宽度：	4.4 mm
Base Number Matches：	1

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