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产品型号SP3203的Datasheet PDF文件预览

®
SP3203  
3V RS-232 Serial Transceiver with Logic Selector  
3 Driver/ 2 Receiver Architecture  
Logic selector function (VL) sets TTL  
input/output levels for mixed logic  
systems  
Meets true EIA/TIA-232-F Standards  
from a +3.0V to +5.5V power supply  
Interoperable with EIA/TIA-232 and  
adheres to EIA/TIA-562 down to a  
+2.7V power source  
Minimum 250Kbps data rate under load  
Regulated Charge Pump Yields Stable  
RS-232 Outputs Regardless of VCC  
Variations  
ESD Specifications:  
+2kV Human Body Model  
Applications  
Palmtops  
Cell phone Data Cables  
PDA's  
DESCRIPTION  
The SP3203 provides a RS-232 transceiver solution for portable and hand-held applications  
such as palmtops, PDA's and cell phones. The SP3203 uses an internal high-efficiency,  
charge-pump that requires only 0.1µF capacitors during 3.3V operation. This charge pump  
and Sipex's driver architecture allow the SP3203 to deliver compliant RS-232 performance  
from a single power supply ranging from +3.0V to +5.5V.  
The SP3203 is a 3-driver/2-receiver device, with a unique VL pin to program the TTL input  
and output logic levels to allow interoperation in mixed-logic voltage systems such as PDA's  
and cell phones. Receiver outputs will not exceed VL for VOH and transmitter input logic levels  
are scaled by the magnitude of the VL input.  
Rev. 6/25/03  
SP3203  
© Copyright 2003 Sipex Corporation  
1
ABSOLUTE MAXIMUM RATINGS  
Output Voltages  
Thesearestressratingsonlyandfunctionaloperationofthe  
device at these ratings or any other above those indicated  
in the operation sections of the specifications below is not  
implied. Exposure to absolute maximum rating conditions  
for extended periods of time may affect reliability and cause  
permanent damage to the device.  
TxOUT.............................................................+13.2V  
RxOUT..............................................-0.3Vto(VL +0.3V)  
Short-Circuit Duration  
TxOUT................................................................Continuous  
Storage Temperature...............................-65°C to +150°C  
Power Dissipation per Packages  
VCC..................................................................-0.3V to +6.0V  
20-Pin TSSOP  
(derate 7.0mW/°C above+70°C)............................560mW  
V+ (NOTE 1)..................................................-0.3V to +7.0V  
V- (NOTE 1)...................................................+0.3V to -7.0V  
V+ + |V-|(NOTE1).........................................................+13V  
ICC (DC VCC or current)...........................................+100mA  
Input Voltages  
TxIN, SHUTDOWN = GND..........................-0.3V to +6.0V  
RxIN...............................................................................+25V  
NOTE 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V.  
SPECIFICATIONS  
(VCC = VL = +3V to +5.5V, C1-C4 = 0.1µF, tested at +3.3V +10%, C1 = 0.047µF, C2-C4 = 0.33µF, tested at +5.0V +10%, TA = TMIN to TMAX, unless  
otherwise noted. Typical values are at VCC = VL +3.3V, TA = +25°C.)  
PARAMETER  
MIN.  
TYP.  
MAX.  
UNITS  
CONDITIONS  
DC CHARACTERISTICS (VCC = +3.3V or +5V, TA = +25oC)  
Supply Current  
0.3  
1
1
mA  
Shutdown = VCC, no load  
Shutdown = GND  
µA  
Shutdown Supply Current  
LOGIC INPUTS  
10  
0.8  
0.6  
VL = 3.3V or 5.0V  
Input Logic Threshold Low  
V
V
TxIN, Shutdown  
TxIN, Shutdown  
VL = 2.5V  
VL = 5.0V  
2.4  
2.0  
1.4  
VL = 3.3V  
VL = 2.5V  
VL = 1.8V  
Input Logic Threshold High  
0.9  
0.5  
Transmitter Input Hystersis  
Input Leakage Current  
RECEIVER OUTPUTS  
Output Leakage Currents  
Output Voltage Low  
V
µA  
±0.01  
±1  
TxIN, Shutdown  
µA  
±0.05  
±10  
0.4  
RxOUT, receivers disabled  
IOUT = 1.6mA  
V
VL -  
0.6  
VL -  
0.1  
Output Voltage High  
V
IOUT = -1mA  
Rev. 6/25/03  
SP3203  
© Copyright 2003 Sipex Corporation  
2
SPECIFICATIONS (continued)  
(VCC = VL = +3V to +5.5V, C1-C4 = 0.1µF, tested at +3.3V +10%, C1 = 0.047µF, C2-C4 = 0.33µF, tested at +5.0V +10%, TA = TMIN to TMAX, unless  
otherwise noted. Typical values are at VCC = VL +3.3V, TA = +25°C.)  
PARAMETER  
MIN.  
TYP.  
MAX. UNITS CONDITIONS  
RECEIVER INPUTS  
Input Voltage Range  
Input Threshold Low  
-25  
0.8  
0.6  
+25  
V
V
1.5  
1.2  
1.8  
1.5  
0.5  
5
VL = 5.0V  
TA = +25OC  
TA = +25OC  
VL = 2.5V or 3.3V  
VL = 5.0V  
2.4  
2.4  
Input Threshold High  
V
VL = 2.5V or 3.3V  
Input Hysteresis  
V
Input Resistance  
3
7
k  
TA = +25OC  
TRANSMITTER OUTPUTS  
Output Voltage Swing  
Output Resistance  
±5  
±5.4  
10M  
V
All transmitter outputs loaded with 3kto TA = 25OC  
300  
V
V
V
CC = V+ = V- = 0, transmitter output = ±2V  
TxOUT = 0  
Output Short-Circuit Current  
Output Leakage Current  
±60  
±25  
mA  
µA  
TxOUT = ±12, transmitter disabled;  
VCC = 0 or 3.0V to 5.5V  
PARAMETER  
MIN.  
TYP.  
MAX. UNITS CONDITIONS  
kbps RL = 3k, CL = 1000pF,  
Maximum Data Rate  
250  
one transmitter switching  
tPHL  
tPLH  
0.15  
0.15  
200  
200  
100  
100  
µs  
Receiver Propagation Delay  
Receiver input to receiver output  
CL = 150pF  
Receiver Output Enable Time  
Receiver Output Disable Time  
Time to Exit Shutdown  
ns  
ns  
µs  
ns  
normal operation  
normal operation  
IVTxOUTI > 3.7V  
(Note 2)  
Transmitter Skew  
Receiver Skew  
I
tPHL -tPLH  
I
50  
ns  
I
tPHL -tPLH  
I
VCC = 3.3V  
6
4
30  
30  
CL = 150pF to 1000pF  
CL = 150pF to 2500pF  
TA = +25oC  
RL = 3kto 7k,  
measured from +3V  
to -3V or -3V to +3V  
Transition-Region Slew Rate  
V/µs  
Note 2. Transmitter skew is measured at the transmitter zero crosspoint.  
Rev. 6/25/03  
SP3203  
© Copyright 2003 Sipex Corporation  
3
PIN  
NUMBER  
NAME  
FUNCTION  
SP3203  
1
C1+  
V+  
Positive terminal of the symmetrical charge-pump capacitor, C1.  
Regulated +5.5V output generated by the charge pump.  
Negative terminal of the symmetrical charge-pump capacitor, C1.  
Positive terminal of the symmetrical charge-pump capacitor, C2.  
Negative terminal of the symmetrical charge-pump capacitor, C2.  
Regulated -5.5V output generated by the charge pump.  
RS-232 receiver input.  
2
C1-  
3
C2+  
4
C2-  
5
V-  
6
R1IN  
R2IN  
R1OUT  
R2OUT  
T1IN  
14  
13  
11  
10  
7
RS-232 receiver input.  
TTL/CMOS receiver output.  
TTL/CMOS receiver output.  
TTL/CMOS driver input.  
T2IN  
TTL/CMOS driver input.  
8
T3IN  
TTL/CMOS driver input.  
9
T1OUT  
T2OUT  
T3OUT  
GND  
VCC  
RS-232 driver output.  
17  
16  
15  
18  
19  
20  
12  
RS-232 driver output.  
RS-232 driver output.  
Ground.  
+3.0V to +5.5V supply voltage.  
SHUTDOWN Apply logic LOW to shut down drivers and charge pump.  
VL Logic-Level Supply Voltage Selection  
Rev. 6/25/03  
SP3203  
© Copyright 2003 Sipex Corporation  
4
20  
19  
18  
17  
16  
15  
1
2
3
4
5
6
7
SHUTDOWN  
C1+  
V+  
V
CC  
-
C1  
GND  
+
C2  
T1OUT  
T2OUT  
T3OUT  
-
C2  
SP3203  
V-  
14  
13  
12  
11  
R1IN  
R2IN  
VL  
T1IN  
T2IN  
8
9
T3IN  
10  
R2OUT  
R1OUT  
Figure 7. SP3203 Pinout Configuration  
Rev. 6/25/03  
SP3203  
© Copyright 2003 Sipex Corporation  
5
+3V to +5.5V  
12  
20  
19  
+
+
0.1µF  
0.1µF  
C5  
C1  
Shutdown  
C1+  
VL  
V
CC  
2
6
1
V+  
V-  
+
+
0.1µF  
0.1µF  
C3  
C4  
C1-  
3
4
C2+  
SP3203  
+
C2  
0.1µF  
C2-  
5
7
17  
16  
T1IN  
T1OUT  
T2OUT  
RS-232  
OUTPUTS  
TTL/CMOS  
INPUTS  
8
T2IN  
9
T3IN  
T3OUT  
R1IN  
15  
14  
R1OUT  
11  
5K  
RS-232  
INPUTS  
TTL/CMOS  
OUTPUTS  
R2OUT  
10  
R2IN  
5KΩ  
13  
GND  
18  
Figure 8. SP3203 Typical Operating Circuit  
Rev. 6/25/03  
SP3203  
© Copyright 2003 Sipex Corporation  
6
DESCRIPTION  
The slew rate of the driver output is internally  
limited to a maximum of 30V/µs in order to  
meet the EIA standards (EIA RS-232D 2.1.7,  
Paragraph 5). The transition of the loaded  
output from HIGH to LOW also meets the  
monotonicity requirements of the standard.  
The SP3203 is a 3-driver/2-receiver device that  
can be operated as a full duplex, RS-232 serial  
transceiverwiththe3rddriveractingasacontrol  
line allowing a Ring Indicator (RI) signal to alert  
the UART on the PC.  
This transceivermeettheEIA/TIA-232andITU-  
T V.28/V.24 communication protocols and can  
beimplementedinbattery-powered, portable, or  
hand-held applications such as notebook or  
palmtop computers, PDA's and cell phones. The  
SP3203 devices feature Sipex's proprietary and  
patented(U.S.#5,306,954)on-boardchargepump  
circuitry that generates ±5.5V RS-232 voltage  
levels from a single +3.0V to +5.5V power  
supply. The SP3203 devices can operate at a  
minimumdatarangeof250kbps,drivingasingle  
driver. The SP3203 is a 3-driver/2-receiver  
device.  
The SP3203 driver can maintain high data rates  
up to 250Kbps with a single driver loaded. Fig-  
ure 9 shows a loopback test circuit used to test  
the RS-232 Drivers. Figure 10 shows the test  
results of the loopback circuit with all three  
drivers active at 120Kbps with typical RS-232  
loads in parallel with 1000pF capacitors. Figure  
11 shows the test results where one driver was  
active at 250Kbps and all three drivers loaded  
withanRS-232receiverinparallelwitha1000pF  
capacitor. The transmitter inputs do not have  
pull-up resistors. Connect unused inputs to  
ground or VL  
THEORY OF OPERATION  
Receivers  
The SP3203 contains four basic circuit blocks:  
1. drivers, 2. receivers, 3. a Sipex proprietary  
charge pump and 4. VL circuitry.  
The receivers convert ±5.0V EIA/TIA-232  
levels to TTL or CMOS logic output levels.  
Receivers are disabled when in shutdown. The  
truth table logic of the SP3203 driver and re-  
ceiver outputs can be found in Table 1.  
Drivers  
The drivers are inverting level transmitters that  
convert TTL or CMOS logic levels to 5.0V EIA/  
TIA-232 levels with an inverted sense relative to  
the input logic levels. Typically, the RS-232  
output voltage swing is +5.4V with no load and  
+5V minimum fully loaded. The driver outputs  
are protected against infinite short-circuits to  
ground without degradation in reliability. These  
drivers comply with the EIA-TIA-232F and all  
previous RS-232 versions. The driver output  
stagesareturnedoff(HighImpedance)whenthe  
device is in shutdown mode.  
Since receiver input is usually from a transmis-  
sion line where long cable lengths and system  
interference can degrade the signal, the inputs  
haveatypicalhysteresismarginof500mV. This  
ensures that the receiver is immune to noisy  
transmission lines. Should an input be left un-  
connected, an internal 5Kpulldown resistor to  
ground will commit the output of the receiver to  
a HIGH state.  
Charge Pump  
The charge pump is a Sipex–patented design  
(U.S. #5,306,954) and uses a unique approach  
compared to older less–efficient designs. The  
charge pump still requires four external  
capacitors, but uses a four–phase voltage  
shifting technique to attain symmetrical 5.5V  
power supplies. The internal power supply  
The drivers typically can operate at a data rate  
of 250Kbps. The drivers can guarantee a data  
rate of 120Kbps fully loaded with 3Kin  
parallel with 1000pF, ensuring compatibility  
with PC-to-PC communication software.  
Rev. 6/25/03  
SP3203  
© Copyright 2003 Sipex Corporation  
7
DEVICE: SP3203  
+3V to +5V  
19  
SHUTDOWN  
TXOUT  
RXOUT  
Charge  
Pump  
+
+
0.1µF  
0.1µF  
C5  
C1  
V
CC  
1
2
6
C1+  
V+  
V-  
+
+
C3  
C4  
0.1µF  
0.1µF  
0
1
High-Z  
Active  
High-Z  
Active  
Inactive  
Active  
3
4
C1-  
C2+  
SP3203  
+
C2  
0.1µF  
5
C2-  
T1OUT  
T1IN  
Table 1. SHUTDOWN Truth Table.  
(Note: When device in shutdown, the SP3203's charge pump is turned off  
and V+ decays to VCC. V- is pulled to ground and the transmitter outputs  
are disabled as High Impendance).  
TTL/CMOS  
INPUTS  
TXIN  
T
XOUT  
R1IN  
R1OUT  
TTL/CMOS  
OUTPUTS  
5K  
R
XOUT  
RXIN  
consists of a regulated dual charge pump that  
provides output voltages of 5.5V regardless of  
the input voltage (VCC) over the +3.0V to +5.5V  
range. This is important to maintain compliant  
RS-232 levels regardless of power supply  
fluctuations.  
5KΩ  
1000pF  
1000pF  
V
CC  
20  
SHUTDOWN  
12  
V
L
+3V to +5.5V  
GND  
18  
Figure 9. Loopback Test Circuit for RS-232 Driver Data  
Transmission Rates  
The charge pump operates in a discontinuous  
mode using an internal oscillator. If the output  
voltages are less than a of 5.5V, the charge  
pump is enabled. If the output voltages exceed  
a of 5.5V, the charge pump is disabled. This  
oscillator controls the four phases of the voltage  
shifting(Figure12). Adescriptionofeachphase  
follows.  
VSS Transfer-Phase 2 (Figure 14)  
Phase two of the clock connects the negative  
terminal of C2 to the VSS storage capacitor and  
the positive terminal of C2 to GND. This  
transfers a negative generated voltage to C3.  
This generated voltage is  
regulated to a minimum voltage of -5.5V.  
Simultaneous with the transfer of the voltage  
to C3, the positive side of capacitor C1 is  
switched to VCC and the negative side is  
connected to GND.  
VSS Charge Storage-Phase 1(Figure 13)  
Duringthisphaseoftheclockcycle, thepositive  
side of capacitors C1 and C2 are initially charged  
+
to VCC. Cl is then switched to GND and the  
+
charge in C1 is transferred to C2 . Since C2 is  
VDD Charge Storage-Phase 3 (Figure 15)  
The third phase of the clock is identical to the  
first phase — the charge transferred in C1 pro-  
connected to VCC, the voltage potential across  
capacitor C2 is now 2 times VCC  
.
[
T
T
]
[
T
T
]
T1 IN  
1
T1 IN  
1
T1 OUT 2  
T1 OUT 2  
T
T
T
T
R1 OUT  
3
R1 OUT  
3
Ch2  
5.00V  
Ch3 5.00V  
5.00V M 5.00µs Ch1  
0V  
Ch1  
Ch2  
5.00V  
Ch3 5.00V  
5.00V M 2.50µs Ch1  
0V  
Ch1  
Figure 10. Loopback Test Circuit Result at 120Kbps  
(All Drivers Fully Loaded)  
Figure 11. Loopback Test Circuit result at 250Kbps  
(All Drivers Fully Loaded)  
Rev. 6/25/03  
SP3203  
© Copyright 2003 Sipex Corporation  
8
ducesVCC inthenegativeterminalofC1, which  
is applied to the negative side of capacitor C2.  
+
Since C2 is at VCC, the voltage potential across  
C2 is 2 times VCC  
.
VDD Transfer-Phase 4 (Figure 16)  
The fourth phase of the clock connects the nega-  
tive terminal of C2 to GND, and transfers this  
positive generated voltage across C2 to C4, the  
V
DD storage capacitor. This voltage is regulated  
to +5.5V. At this voltage, the internal oscillator  
isdisabled. Simultaneouswiththetransferofthe  
voltage to C4, positive side of capacitor C1 is  
switched to VCC and the negative side is con-  
nected to GND, allowing the charge pump cycle  
to begin again. The charge pump cycle will  
continueaslongastheoperationalconditionsfor  
the internal oscillator are present.  
+
Since both V and V are separately generated  
+
fromVCC, inano–loadcondition, V andV will  
be symmetrical. Older charge pump approaches  
that generate V from V will show a decrease in  
the magnitude of V compared to V due to the  
inherent ineffiencies in the design.  
+
+
The clock rate for the charge pump is typically  
operates at 250kHz. The external capacitors are  
usually 0.1µF with a 16V breakdown voltage  
rating.  
VL Supply Level  
Current RS-232 serial tranceivers are designed  
withfixed5Vor3.3VTTLinput/outputvoltages  
levels. TheVL functionintheSP3203allowsthe  
end user to set the TTL input/output voltage  
levels independent of VCC. By connecting VL to  
the main logic bus of system, the TTL input/  
output limits and threshold are reset to interface  
with the on board low voltage logic circuity.  
Capacitor Selection Table:  
V
CC (V)  
C1 (µF)  
0.1  
C2-C4(µF)  
3.0 to 3.6  
4.5 to 5.5  
3.0 to 5.5  
0.1  
0.33  
1
0.047  
0.22  
Rev. 6/25/03  
SP3203  
© Copyright 2003 Sipex Corporation  
9
[
T
]
+6V  
a) C2+  
T
T
0V  
0V  
1
2
2
b) C2-  
-6V  
Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 1.96V  
Figure 12. Charge Pump Waveforms  
Figure 13. Charge Pump — Phase 4 - VSS Charge Storage  
Figure 14. Charge Pump — Phase 3 - VSS Charge Transfer  
Figure 15. Charge Pump — Phase 2 - VDD Charge Storage  
Figure 16. Charge Pump — Phase 1 - VDD Charge Transfer  
Rev. 6/25/03  
SP3203  
© Copyright 2003 Sipex Corporation  
10  
+
+
20  
Shutdown  
C1+  
19  
12  
0.1µF  
0.1µF  
C5  
C1  
V
L
V
CC  
1
2
6
V+  
+
+
C3  
C4  
0.1µF  
0.1µF  
3
4
C1-  
SP3203  
C2+  
V-  
+
C2  
0.1µF  
5
7
C2-  
T1OUT  
T2OUT  
T3OUT  
T1IN  
17  
16  
15  
T2IN  
T3IN  
8
9
R1IN  
R2IN  
R OUT  
1
14  
13  
11  
10  
R2OUT  
DB-9  
Connector  
1
2
3
4
5
6
GND  
18  
7
8
9
DB-9 Connector Pins:  
1. Received Line Signal Detector  
2. Received Data  
6. DCE Ready  
7. Request to Send  
8. Clear to Send  
9. Ring Indicator  
3. Transmitted Data  
4. Data Terminal Ready  
5. Signal Ground (Common)  
Figure 17. Circuit for the connectivity of the SP3203 with a DB-9 connector  
Rev. 6/25/03  
SP3203  
© Copyright 2003 Sipex Corporation  
11  
ESD TOLERANCE  
discharge it to an integrated circuit. The  
simulation is performed by using a test model as  
shown in Figure 18. This method will test the  
IC’s capability to withstand an ESD transient  
duringnormalhandlingsuchasinmanufacturing  
areaswheretheICstendtobehandledfrequently.  
FortheHumanBodyModel, thecurrentlimiting  
resistor (RS) and the source capacitor (CS ) are  
15kand 100pF, respectively.  
The SP3203 incorporates ruggedized ESD cells  
on all driver output and receiver input pins.  
The Human Body Model has been the generally  
acceptedESDtestingmethodforsemiconductors.  
This method is also specified in MIL-STD-883,  
Method 3015.7 for ESD testing. The premise of  
this ESD test is to simulate the human body’s  
potential to store electro-static energy and  
R
R
S
S
R
R
C
C
SW2  
SW2  
SW1  
SW1  
Device  
Under  
Test  
DC Power  
Source  
C
C
S
S
Figure 18. ESD Test Circuit for Human Body Model  
Rev. 6/25/03  
SP3203  
© Copyright 2003 Sipex Corporation  
12  
PACKAGE: PLASTIC THIN SMALL OUTLINE (TSSOP)  
e
DIMENSIONS  
in inches (mm)  
Minimum/Maximum  
0.126 BSC (3.2 BSC)  
0.252 BSC (6.4 BSC)  
1.0 OIA  
Symbol  
20 Lead  
0.252/0.260  
(6.40/6.60)  
0.169 (4.30)  
0.177 (4.50)  
D
0.039 (1.0)  
e
0.026 BSC  
(0.65 BSC)  
0’-8’ 12’REF  
e/2  
0.039 (1.0)  
0.043 (1.10) Max  
D
0.033 (0.85)  
0.037 (0.95)  
0.007 (0.19)  
0.012 (0.30)  
0.002 (0.05)  
0.006 (0.15)  
(θ2)  
0.008 (0.20)  
0.004 (0.09) Min  
0.004 (0.09) Min  
Gage  
Plane  
(θ3)  
0.020 (0.50)  
0.026 (0.75)  
(θ1)  
0.010 (0.25)  
1.0 REF  
Rev. 6/25/03  
SP3203  
© Copyright 2003 Sipex Corporation  
13  
ORDERING INFORMATION  
Model  
SP3203CY  
SP3203EY  
Temperature Range  
0°C to +70°C  
Package Types  
20-pin TSSOP  
20-pin TSSOP  
-40°C to +85°C  
Please consult the factory for pricing and availability on a Tape-On-Reel option.  
Co rp o ra tio n  
ANALOG EXCELLENCE  
Sipex Corporation  
Headquarters and  
Sales Office  
233 South Hillview Drive  
Milpitas, CA 95035  
TEL: (408) 934-7500  
FAX: (408) 935-7600  
Sales Office  
22 Linnell Circle  
Billerica, MA 01821  
TEL: (978) 667-8700  
FAX: (978) 670-9001  
e-mail: sales@sipex.com  
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the  
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.  
Rev. 6/25/03  
SP3203  
© Copyright 2003 Sipex Corporation  
14  
配单直通车
SP3203CY产品参数
型号:SP3203CY
是否Rohs认证:不符合
生命周期:Transferred
IHS 制造商:SIPEX CORP
包装说明:MO-153AC, TSSOP-20
Reach Compliance Code:unknown
风险等级:5.7
Is Samacsys:N
差分输出:NO
驱动器位数:3
输入特性:SCHMITT TRIGGER
接口集成电路类型:LINE TRANSCEIVER
接口标准:EIA-232-F; TIA-232-F; V.24; V.28; EIA-562; TIA-562
JESD-30 代码:R-PDSO-G20
JESD-609代码:e0
长度:6.5 mm
湿度敏感等级:1
功能数量:2
端子数量:20
最高工作温度:70 °C
最低工作温度:
最小输出摆幅:10 V
最大输出低电流:0.0016 A
封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP
封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240
电源:3.3/5 V
认证状态:Not Qualified
最大接收延迟:
接收器位数:2
座面最大高度:1.2 mm
子类别:Line Driver or Receivers
最大压摆率:1 mA
最大供电电压:5.5 V
最小供电电压:3 V
标称供电电压:3.3 V
电源电压1-最大:5.5 V
电源电压1-分钟:3 V
电源电压1-Nom:3.3 V
表面贴装:YES
温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING
端子节距:0.65 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:30
宽度:4.4 mm
Base Number Matches:1
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