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TCS3471

COLOR LIGHT-TO-DIGITAL CONVERTER

r

TAOS115 − MARCH 2011

PACKAGE FN

DUAL FLAT NO-LEAD

(TOP VIEW)

Features

D Color Light Sensing

− Programmable Analog Gain, Integration

Time, and Interrupt Function with Upper

and Lower Thresholds

6 SDA

5 INT

4 NC

V_DD

1

SCL 2

GND 3

− Resolution Up to 16 Bits

− Very High Sensitivity — Ideally Suited for

Operation Behind Dark Glass

− Up to 1,000,000:1 Dynamic Range

Package Drawing Not to Scale

D Low Power Wait State

− 65 mA Typical Current

Applications

− Wait Timer is Programmable from 2.4 ms

to > 7 Seconds

D Color Temperature Sensing

2

D I C Interface Compatible

D RGB LED Backlight Control

2

− Up to 400 kHz (I C Fast Mode)

D Color Display Closed-Loop Feedback

D Dedicated Interrupt Pin

Control

D Pin and Register Set Compatible with the

D Ambient Light Sensing for Display

TCS3x7x Family of Devices

Brightness Control

D Small 2 mm ꢀ 2.4 mm Dual Flat No-Lead

D Sleep Mode — 2.5 mA Typical Current

D Industrial Process Control

Package

D Medical Diagnostics

End Products and Market Segments

D HDTVs, Mobile Handsets, Tablets, Laptops,

Monitors, PMP (Portable Media Payers)

D Medical Instrumentation

D Consumer Toys

D Industrial/Commercial Lighting

Description

The TCS3471 family of devices provides red, green, blue, and clear light sensing (RGBC) that detects light

intensity under a variety of lighting conditions and through a variety of attenuation materials. An internal state

machine provides the ability to put the device into a low power mode in between RGBC measurements providing

very low average power consumption.

The TCS3471 is directly useful in lighting conditions containing minimal IR content such as LED RGB backlight

control, reflected LED color sampler, or fluorescent light color temperature detector. With the addition of an IR

blocking filter, the device is an excellent ambient light sensor, color temperature monitor, and general purpose

color sensor.

Copyright E 2011, TAOS Inc.

The LUMENOLOGY r Company

Texas Adva^rnced Optoelectronic Solutions Inc.

1001 Klein Road S Suite 300 S Plano, TX 75074 S (972) 673-0759

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TCS3471

COLOR LIGHT-TO-DIGITAL CONVERTER

TAOS115 − MARCH 2011

Functional Block Diagram

Interrupt

INT

Wait Control

V

DD

Upper Limit

Lower Limit

RGBC Control

SCL

Clear ADC

Red ADC

Clear Data

Red Data

Clear

Red

Green ADC Green Data

Blue ADC Blue Data

Green

Blue

SDA

GND

Detailed Description

The TCS3471 light-to-digital device contains a 4 × 4 photodiode array, integrating amplifiers, ADCs,

2

accumulators, clocks, buffers, comparators, a state machine, and an I C interface. The 4 × 4 photodiode array

is composed of red-filtered, green-filtered, blue-filtered, and clear photodiodes — four of each type. Four

integrating ADCs simultaneously convert the amplified photodiode currents to a digital value providing up to 16

bits of resolution. Upon completion of the conversion cycle, the conversion result is transferred to the data

registers. The transfers are double-buffered to ensure that the integrity of the data is maintained.

2

Communication to the device is accomplished through a fast (up to 400 kHz), two-wire I C serial bus for easy

connection to a microcontroller or embedded controller.

The TCS3471 provides a separate pin for level-style interrupts. When interrupts are enabled and a pre-set value

is exceeded, the interrupt pin is asserted and remains asserted until cleared by the controlling firmware. The

interrupt feature simplifies and improves system efficiency by eliminating the need to poll a sensor for a light

intensity value. An interrupt is generated when the value of an RGBC conversion exceeds either an upper or

lower threshold. In addition, a programmable interrupt persistence feature allows the user to determine how

many consecutive exceeded thresholds are necessary to trigger an interrupt.

Terminal Functions

TERMINAL

TYPE

DESCRIPTION

Power supply ground. All voltages are referenced to GND.

NAME

GND

INT

NO.

3

5

O

Interrupt — open drain.

NC

4

Do not connect

2

SCL

SDA

2

I

I C serial clock input terminal — clock signal for I C serial data.

2

6

I/O

I C serial data I/O terminal — serial data I/O for I C .

Supply voltage.

V

1

DD

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TCS3471

COLOR LIGHT-TO-DIGITAL CONVERTER

TAOS115 − MARCH 2011

Available Options

DEVICE

ADDRESS

PACKAGE − LEADS

INTERFACE DESCRIPTION

ORDERING NUMBER

TCS34711FN

†

2

TCS34711

0x39

0x29

FN−6

I C Vbus = V Interface

DD

2

TCS34713

TCS34715

I C Vbus = 1.8 V Interface

TCS34713FN

†

2

I C Vbus = V Interface

TCS34715FN

DD

2

TCS34717

I C Vbus = 1.8 V Interface

TCS34717FN

†

Contact TAOS for availability.

Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)^†

Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 V

DD

Digital output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.8 V

O

Digital output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1 mA to 20 mA

O

Storage temperature range, T

ESD tolerance, human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages are with respect to GND.

Recommended Operating Conditions

MIN NOM

MAX

3.3

UNIT

V

Supply voltage, V

2.7

3

DD

Operating free-air temperature, T

−30

70

°C

A

Operating Characteristics, V_DD= 3 V, T_A= 25ꢁ C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

235

65

MAX

UNIT

Active

Wait mode

330

I

Supply current

μA

DD

2

Sleep mode — no I C activity

3 mA sink current

2.5

10

0.4

0.6

5

0

V

I

INT, SDA output low voltage

V

OL

6 mA sink current

Leakage current, SDA, SCL, INT pins

Leakage current, LDR pin

−5

−1

μA

LEAK

I

+10

TCS34711 & TCS34715

TCS34713 & TCS34717

TCS34711 & TCS34715

TCS34713 & TCS34717

0.7 V

DD

V

SCL, SDA input high voltage

SCL, SDA input low voltage

V

IH

IL

1.25

0.3 V

DD

0.54

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TCS3471

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Optical Characteristics, V_DD= 3 V, T_A= 25ꢁ C, GAIN = 16, ATIME = 0xF6 (unless otherwise noted) (see

Note 1)

Red Channel

Green Channel

Blue Channel

Clear Channel

TEST

CONDITIONS

PARAMETER

UNIT

MIN TYP MAX

λ

= 465 nm

See Note 2

D

0%

8%

15% 10%

25% 60%

110% 0%

42% 65%

88% 19.2

24

28

34

28.8

33.6

40.8

(counts/

λ

= 525 nm

Irradiance

responsivity

D

85%

15%

9%

5%

35% 22.4

25% 27.2

R

e

μW/

See Note 3

2

cm )

λ

= 625 nm

D

85%

See Note 4

NOTES: 1. The percentage shown represents the ratio of the respective red, green, or blue channel value to the clear channel value.

2. The 465 nm input irradiance is supplied by an InGaN light-emitting diode with the following characteristics:

dominant wavelength λ = 465 nm, spectral halfwidth Δλ½ = 22 nm, and luminous efficacy = 75 lm/W.

D

3. The 525 nm input irradiance is supplied by an InGaN light-emitting diode with the following characteristics:

dominant wavelength λ = 525 nm, spectral halfwidth Δλ½ = 35 nm, and luminous efficacy = 520 lm/W.

D

4. The 625 nm input irradiance is supplied by a AlInGaP light-emitting diode with the following characteristics:

dominant wavelength λ = 625 nm, spectral halfwidth Δλ½ = 9 nm, and luminous efficacy = 155 lm/W.

D

RGBC Characteristics, V_DD= 3 V, T_A= 25ꢁ C, AGAIN = 16, AEN = 1 (unless otherwise noted)

PARAMETER

Dark ADC count value

ADC integration time step size

ADC number of integration steps

ADC counts per step

TEST CONDITIONS

MIN

0

TYP

1

MAX

5

UNIT

counts

ms

E = 0, AGAIN = 60×, ATIME = 0xD6 (100 ms)

e

ATIME = 0xFF

2.27

1

2.4

2.56

256

steps

0

1024 counts

65535 counts

4.2

ADC count value

ATIME = 0xC0 (153.6 ms)

0

4×

16×

60×

3.8

4

Gain scaling, relative to 1× gain

15

58

16

60

16.8

63

%

setting

Wait Characteristics, V_DD= 3 V, T_A= 25ꢁ C, Gain = 16, WEN = 1 (unless otherwise noted)

PARAMETER

Wait step size

TEST CONDITIONS

WTIME = 0xFF

CHANNEL

MIN

2.27

1

TYP

MAX

2.56

256

UNIT

ms

2.4

Wait number of steps

steps

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AC Electrical Characteristics, V_DD= 3 V, T_A= 25ꢁ C (unless otherwise noted)

†

PARAMETER

TEST CONDITIONS

MIN

0

TYP

MAX

UNIT

kHz

μs

2

f

t

Clock frequency (I C only)

400

(SCL)

(BUF)

Bus free time between start and stop condition

1.3

Hold time after (repeated) start condition. After

this period, the first clock is generated.

t

0.6

μs

(HDSTA)

t

Repeated start condition setup time

Stop condition setup time

Data hold time

0.6

0

μs

ns

μs

ns

pF

(SUSTA)

(SUSTO)

(HDDAT)

(SUDAT)

(LOW)

(HIGH)

F

Data setup time

100

1.3

0.6

SCL clock low period

SCL clock high period

Clock/data fall time

300

10

Clock/data rise time

Input pin capacitance

R

C

i

†

Specified by design and characterization; not production tested.

PARAMETER MEASUREMENT INFORMATION

t

(R)

t

(F)

(LOW)

V

IH

SCL

SDA

V

IL

t

(HDSTA)

(HIGH)

(SUSTA)

t

(SUSTO)

t

(BUF)

(HDDAT)

(SUDAT)

V

IH

IL

P

S

P

Stop

Condition

Start

Condition

Start

Stop

t

(LOWSEXT)

SCL

ACK

t

(LOWMEXT)

SCL

SDA

Figure 1. Timing Diagrams

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TYPICAL CHARACTERISTICS

NORMALIZED I_DD

vs.

PHOTODIODE SPECTRAL RESPONSIVITY

V_DDand TEMPERATURE

1

110%

108%

106%

104%

102%

Normalized to

Clear

0.9

@ 755 nm

75ꢁC

0.8

0.7

Clear

T

A

= 25°C

Red

50ꢁC

25ꢁC

0.6

0.5

0.4

0.3

100%

98%

96%

94%

92%

0ꢁC

Blue

0.2

0.1

0

Green

2.7

2.8

2.9

3

3.1

3.2

3.3

300

500

700

900

1100

λ − Wavelength − nm

V

— V

DD

Figure 2

Figure 3

NORMALIZED RESPONSIVITY

vs.

ANGULAR DISPLACEMENT

RESPONSIVITY TEMPERATURE

COEFFICIENT

10,000

1.0

0.8

0.6

0.4

1000

0.2

0

-Q

−30

+Q

30

100

90

−90

−60

0

60

600

700

800

900

1000

400

500

Q − Angular Displacement − °

λ − Wavelength − nm

Figure 4

Figure 5

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PRINCIPLES OF OPERATION

System State Machine

The TCS3471 provides control of RGBC and power management functionality through an internal state

machine (Figure 6). After a power-on-reset, the device is in the sleep mode. As soon as the PON bit is set, the

device will move to the start state. It will then continue through the Wait and RGBC states. If these states are

enabled, the device will execute each function. If the PON bit is set to 0, the state machine will continue until

all conversions are completed and then go into a low power sleep mode.

Sleep

PON = 1 (r0:b0)

PON = 0 (r0:b0)

Start

Wait

RGBC

Figure 6. Simplified State Diagram

NOTE: In this document, the nomenclature uses the bit field name in italics followed by the register number and

bit number to allow the user to easily identify the register and bit that controls the function. For example, the

power on (PON) is in register 0, bit 0. This is represented as PON (r0:b0).

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RGBC Operation

The RGBC engine contains RGBC gain control (AGAIN) and four integrating analog-to-digital converters (ADC)

for the RGBC photodiodes. The RGBC integration time (ATIME) impacts both the resolution and the sensitivity

of the RGBC reading. Integration of all four channels occurs simultaneously and upon completion of the

conversion cycle, the results are transferred to the color data registers. This data is also referred to as channel

count.

The transfers are double-buffered to ensure that invalid data is not read during the transfer. After the

transfer, the device automatically moves to the next state in accordance with the configured state machine.

ATIME(r1)

AGAIN(r0x0F, b1:0)

2.4 ms to 700 ms

1ꢀ, 4ꢀ, 16ꢀ, 60ꢀ Gain

RGBC Control

Clear ADC

Red ADC

Clear Data

Red Data

CDATAH(r0x15), CDATA(r0x14)

RDATAH(r0x17), RDATA(r0x16)

Clear

Red

Green ADC Green Data

Blue ADC Blue Data

GDATAH(r0x19), GDATA(r0x18)

BDATAH(r0x1B), BDATA(r0x1A)

Green

Blue

Figure 7. RGBC Operation

The registers for programming the integration and wait times are a 2’s compliment values. The actual time can

be calculated as follows:

ATIME = 256 − Integration Time / 2.4 ms

Inversely, the time can be calculated from the register value as follows:

Integration Time = 2.4 ms × (256 − ATIME)

For example, if a 100-ms integration time is needed, the device needs to be programmed to:

256 − (100 / 2.4) = 256 − 42 = 214 = 0xD6

Conversely, the programmed value of 0xC0 would correspond to:

(256 − 0xC0) × 2.4 = 64 × 2.4 = 154 ms.

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Interrupts

The interrupt feature simplifies and improves system efficiency by eliminating the need to poll the sensor for

light intensity values outside of a user-defined range. While the interrupt function is always enabled and it’s

status is available in the status register (0x13), the output of the interrupt state can be enabled using the RGBC

interrupt enable (AIEN) field in the enable register (0x00).

Two 16-bit interrupt threshold registers allow the user to set limits below and above a desired light level range.

An interrupt can be generated when the RGBC Clear data (CDATA) falls outside of the desired light level

range, as determined by the values in the RGBC interrupt low threshold registers (AILTx) and RGBC interrupt

high threshold registers (AIHTx). It is important to note that the low threshold value must be less than the high

threshold value for proper operation.

To further control when an interrupt occurs, the device provides a persistence filter. The persistence filter allows

the user to specify the number of consecutive out-of-range RGBC occurrences before an interrupt is generated.

The persistence register (0x0C) allows the user to set the persistence (APERS) value. See the persistence

register for details on the persistence filter values. Once the persistence filter generates an interrupt, it will

continue until a special function interrupt clear command is received (see command register).

AIHTH(r07), AIHTL(r06)

PPERS(r0x0C, b3:0)

Upper Limit

RGBC Persistence

Clear

ADC

Clear

Data

Lower Limit

Clear

AILTH(r05), AILTL(r04)

Figure 8. Programmable Interrupt

State Diagram

Figure 9 shows a more detailed flow for the state machine. The device starts in the sleep mode. The PON bit

is written to enable the device. A 2.4-ms delay will occur before entering the start state. If the WEN bit is set,

the state machine will cycle through the wait state. If the WLONG bit is set, the wait cycles are extended by 12×

over normal operation. When the wait counter terminates, the state machine will step to the RGBC state.

The AEN should always be set. In this case, a minimum of 1 integration time step should be programmed. The

RGBC state machine will continue until it reaches the terminal count, at which point the data will be latched in

the RGBC register and the interrupt set, if enabled.

1 to 256steps

Sleep

Step: 2.4 ms

Time: 2.4 ms − 614 ms

PON = 1

PON = 0

WLONG = 0

1 to 256 steps

Step: 2.4 ms

Start

Time: 2.4 ms − 614 ms

Minimum − 2.4 ms

ALS

Wait

Check

ALS

Check

WLONG = 1

1 to 256 steps

Step: 29 ms

ALS

Delay

AEN = 1

WEN = 1

Time: 29 ms − 7.4 s

Minimum − 29 ms

Wait

Time: 2.4 ms

Figure 9. Expanded State Diagram

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I²C Protocol

2

Interface and control are accomplished through an I C serial compatible interface (standard or fast mode) to

a set of registers that provide access to device control functions and output data. The devices support the 7-bit

2

I C addressing protocol.

2

The I C standard provides for three types of bus transaction: read, write, and a combined protocol (Figure 10).

During a write operation, the first byte written is a command byte followed by data. In a combined protocol, the

first byte written is the command byte followed by reading a series of bytes. If a read command is issued, the

register address from the previous command will be used for data access. Likewise, if the MSB of the command

is not set, the device will write a series of bytes at the address stored in the last valid command with a register

address. The command byte contains either control information or a 5-bit register address. The control

commands can also be used to clear interrupts.

2

The I C bus protocol was developed by Philips (now NXP). For a complete description of the I C protocol, please

2

review the NXP I C design specification at http://www.i2c−bus.org/references/.

A

N

P

R

S

Acknowledge (0)

Not Acknowledged (1)

Stop Condition

Read (1)

Start Condition

Sr

W

Repeated Start Condition

Write (0)

... Continuation of protocol

Master-to-Slave

Slave-to-Master

1

7

1

8

1

8

1

...

S

Slave Address

W

A

Command Code

A

Data Byte

A

P

2

I C Write Protocol

1

7

1

8

1

8

1

S

Slave Address

R

A

Data

A

Data

A

P

2

I C Read Protocol

1

7

1

8

1

7

1

S

Slave Address

W

A

Command Code

A

Sr

Slave Address

R

A

8

1

8

1

...

Data

A

Data

A

P

2

I C Read Protocol — Combined Format

2

Figure 10. I C Protocols

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Register Set

The TCS3471 is controlled and monitored by data registers and a command register accessed through the

serial interface. These registers provide for a variety of control functions and can be read to determine results

of the ADC conversions. The register set is summarized in Table 1.

Table 1. Register Address

ADDRESS

−−

RESISTER NAME

COMMAND

ENABLE

ATIME

R/W

W

REGISTER FUNCTION

Specifies register address

RESET VALUE

0x00

0xFF

0x00

ID

0x00

0x01

0x03

0x04

0x05

0x06

0x07

0x0C

0x0D

0x0F

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

R/W

R

Enables states and interrupts

RGBC ADC time

WTIME

AILTL

Wait time

RGBC interrupt low threshold low byte

RGBC interrupt low threshold high byte

RGBC interrupt high threshold low byte

RGBC interrupt high threshold high byte

Interrupt persistence filters

Configuration

AILTH

AIHTL

AIHTH

PERS

CONFIG

CONTROL

ID

Gain control register

Device ID

STATUS

CDATA

R

Device status

0x00

R

Clear ADC low data register

Clear ADC high data register

Red ADC low data register

Red ADC high data register

Green ADC low data register

Green ADC high data register

Blue ADC low data register

Blue ADC high data register

CDATAH

RDATA

R

RDATAH

GDATA

R

GDATAH

BDATA

R

BDATAH

R

2

The mechanics of accessing a specific register depends on the specific protocol used. See the section on I C

protocols on the previous pages. In general, the COMMAND register is written first to specify the specific

control/status register for the following read/write operations.

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Command Register

The command registers specifies the address of the target register for future write and read operations.

Table 2. Command Register

7

6

5

4

3

2

ADD

1

0

COMMAND

− −

COMMAND

TYPE

FIELD

COMMAND

TYPE

BITS

7

DESCRIPTION

Select Command Register. Must write as 1 when addressing COMMAND register.

Selects type of transaction to follow in subsequent data transfers:

6:5

FIELD VALUE

INTEGRATION TIME

Repeated byte protocol transaction

Auto-increment protocol transaction

Reserved — Do not use

00

01

10

11

Special function — See description below

Byte protocol will repeatedly read the same register with each data access.

Block protocol will provide auto-increment function to read successive bytes.

ADD

4:0

Address field/special function field. Depending on the transaction type, see above, this field either

specifies a special function command or selects the specific control-status-register for following write and

read transactions. The field values listed below apply only to special function commands:

FIELD VALUE

00000

READ VALUE

Normal — no action

RGBC interrupt clear

Reserved — Do not write

00110

other

RGBC Interrupt Clear. Clears any pending RGBC interrupt. This special function is self clearing.

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Enable Register (0x00)

The Enable register is used primarily to power the TCS3471 device on and off, and enable functions and

interrupts as shown in Table 3.

Table 3. Enable Register

7

6

5

4

3

2

1

0

Address

0x00

Reserved

AIEN

WEN

Reserved

AEN

PON

ENABLE

FIELD

Reserved

AIEN

BITS

7:5

4

DESCRIPTION

Reserved. Write as 0.

RGBC interrupt enable. When asserted, permits RGBC interrupts to be generated.

Wait enable. This bit activates the wait feature. Writing a 1 activates the wait timer. Writing a 0 disables the

wait timer.

WEN

Reserved

AEN

3

2

1

Reserved. Write as 0.

RGBC enable. This bit actives the two-channel ADC. Writing a 1 activates the RGBC. Writing a 0 disables

the RGBC.

Power ON. This bit activates the internal oscillator to permit the timers and ADC channels to operate.

1

2

PON

0

Writing a 1 activates the oscillator. Writing a 0 disables the oscillator. During reads and writes over the I C

interface, this bit is temporarily overridden and the oscillator is enabled, independent of the state of PON.

NOTE 1: A minimum interval of 2.4 ms must pass after PON is asserted before an RGBC can be initiated.

RGBC Timing Register (0x01)

The RGBC timing register controls the internal integration time of the RGBC clear and IR channel ADCs in

2.4-ms increments. Max RGBC Count = (256 − ATIME) × 1024 up to a maximum of 65535.

Table 4. RGBC Timing Register

FIELD

BITS

DESCRIPTION

INTEG_CYCLES

ATIME

7:0

VALUE

0xFF

0xF6

0xD5

0xC0

0x00

TIME

2.4 ms

24 ms

MAX COUNT

1024

1

10

42

64

256

10240

101 ms

154 ms

700 ms

43008

65535

Wait Time Register (0x03)

Wait time is set 2.4 ms increments unless the WLONG bit is asserted, in which case the wait times are 12×

longer. WTIME is programmed as a 2’s complement number.

Table 5. Wait Time Register

FIELD

BITS

DESCRIPTION

TIME (WLONG = 0)

WTIME

7:0

REGISTER VALUE

WAIT TIME

TIME (WLONG = 1)

0.029 sec

0xFF

0xAB

0x00

1

2.4 ms

204 ms

614 ms

85

2.45 sec

256

7.4 sec

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RGBC Interrupt Threshold Registers (0x04 − 0x07)

The RGBC interrupt threshold registers provides the values to be used as the high and low trigger points for

the comparison function for interrupt generation. If the value generated by the clear channel crosses below the

lower threshold specified, or above the higher threshold, an interrupt is asserted on the interrupt pin.

Table 6. RGBC Interrupt Threshold Registers

REGISTER

AILTL

ADDRESS

0x04

BITS

7:0

DESCRIPTION

RGBC clear channel low threshold lower byte

RGBC clear channel low threshold upper byte

RGBC clear channel high threshold lower byte

RGBC clear channel high threshold upper byte

AILTH

0x05

7:0

AIHTL

0x06

7:0

AIHTH

0x07

7:0

Persistence Register (0x0C)

The persistence register controls the filtering interrupt capabilities of the device. Configurable filtering is

provided to allow interrupts to be generated after each integration cycle or if the integration has produced a result

that is outside of the values specified by the threshold register for some specified amount of time.

Table 7. Persistence Register

7

6

5

4

3

2

1

0

Address

0x0C

PERS

FIELD

Reserved

APERS

BITS

7:4

DESCRIPTION

Reserved

APERS

Reserved

Interrupt persistence. Controls rate of interrupt to the host processor.

3:0

FIELD VALUE

0000

0001

0010

0011

MEANING

INTERRUPT PERSISTENCE FUNCTION

Every RGBC cycle generates an interrupt

Every

1

1 clear channel value outside of threshold range

2 clear channel consecutive values out of range

3 clear channel consecutive values out of range

5 clear channel consecutive values out of range

10 clear channel consecutive values out of range

15 clear channel consecutive values out of range

20 clear channel consecutive values out of range

25 clear channel consecutive values out of range

30 clear channel consecutive values out of range

35 clear channel consecutive values out of range

40 clear channel consecutive values out of range

45 clear channel consecutive values out of range

50 clear channel consecutive values out of range

55 clear channel consecutive values out of range

60 clear channel consecutive values out of range

2

3

0100

0101

0110

5

10

15

20

25

30

35

40

45

50

55

60

0111

1000

1001

1010

1011

1100

1101

1110

1111

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Configuration Register (0x0D)

The configuration register sets the wait long time.

Table 8. Configuration Register

7

6

5

4

3

2

1

0

Address

0x0D

CONFIG

FIELD

WLONG

Reserved

BITS

DESCRIPTION

Reserved

WLONG

Reserved

7:2

Reserved. Write as 0.

Wait Long. When asserted, the wait cycles are increased by a factor 12× from that programmed in the

1

0

WTIME register.

Reserved. Write as 0.

Control Register (0x0F)

The Control register provides eight bits of miscellaneous control to the analog block. These bits typically control

functions such as gain settings and/or diode selection.

Table 9. Control Register

7

6

5

4

3

2

1

0

Address

0x0F

CONTROL

Reserved

AGAIN

FIELD

Reserved

AGAIN

BITS

7:2

DESCRIPTION

Reserved. Write bits as 0

RGBC Gain Control.

FIELD VALUE

1:0

RGBC GAIN VALUE

00

01

10

11

1× gain

4× gain

16× gain

60× gain

ID Register (0x12)

The ID Register provides the value for the part number. The ID register is a read-only register.

Table 10. ID Register

7

6

5

4

3

2

1

0

Address

0x12

ID

FIELD

BITS

DESCRIPTION

0x14 = TCS34711 & TCS34715

0x1D = TCS34713 & TCS34717

ID

7:0

Part number identification

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Status Register (0x13)

The Status Register provides the internal status of the device. This register is read only.

Table 11. Status Register

7

6

5

4

3

2

1

0

Address

0x13

STATUS

FIELD

Reserved

AINT

Reserved

AVALID

BIT

7:5

4

DESCRIPTION

Reserved

AINT

Reserved.

RGBC clear channel Interrupt.

Reserved.

Reserved

AVALID

3:1

0

RGBC Valid. Indicates that the RGBC channels have completed an integration cycle.

RGBC Channel Data Registers (0x14 − 0x1B)

Clear, red, green, and blue data is stored as 16-bit values. To ensure the data is read correctly, a two-byte read

2

I C transaction should be used with a read word protocol bit set in the command register. With this operation,

when the lower byte register is read, the upper eight bits are stored into a shadow register, which is read by a

subsequent read to the upper byte. The upper register will read the correct value even if additional ADC

integration cycles end between the reading of the lower and upper registers.

Table 12. ADC Channel Data Registers

REGISTER

CDATA

ADDRESS

0x14

BITS

7:0

DESCRIPTION

Clear data low byte

CDATAH

RDATA

0x15

Clear data high byte

Red data low byte

Red data high byte

Green data low byte

Green data high byte

Blue data low byte

Blue data high byte

0x16

RDATAH

GDATA

0x17

0x18

GDATAH

BDATA

0x19

0x1A

0x1B

BDATAH

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APPLICATION INFORMATION: HARDWARE

Typical Hardware Application

A typical hardware application circuit is shown in Figure 11. A 1-μF low-ESR decoupling capacitor should be

placed as close as possible to the V pin.

DD

V

BUS

DD

V

DD

R

P

R

P

R

PI

1 mF

TCS3471

INT

SCL

SDA

GND

Figure 11. Typical Application Hardware Circuit

2

V

BUS

in Figure 11 refers to the I C bus voltage, which is either V or 1.8 V. Be sure to apply the specified I C

DD

bus voltage shown in the Available Options table for the specific device being used.

2

The I C signals and the Interrupt are open-drain outputs and require pull-up resistors. The pull-up resistor (R )

P

2

value is a function of the I C bus speed, the I C bus voltage, and the capacitive load. The TAOS EVM running

at 400 kbps, uses 1.5-kΩ resistors. A 10-kΩ pull-up resistor (R ) can be used for the interrupt line.

PI

PCB Pad Layout

Suggested PCB pad layout guidelines for the Dual Flat No-Lead (FN) surface mount package are shown in

Figure 12.

2500

Note: Pads can be

extended further if hand

soldering is needed.

1000

400

650

1700

400

NOTES: A. All linear dimensions are in micrometers.

B. This drawing is subject to change without notice.

Figure 12. Suggested FN Package PCB Layout

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MECHANICAL DATA

PACKAGE FN

TOP VIEW

Dual Flat No-Lead

496 ꢂ 10

PIN OUT

TOP VIEW

PIN 1

V_DD

1

6 SDA

5 INT

4 NC

406

ꢂ 10

2400 ꢂ 75

SCL 2

GND 3

2000

ꢂ 75

Photodiode Active Area

END VIEW

SIDE VIEW

295

Nominal

650 ꢂ 50

203 ꢂ 8

650

BSC

300

ꢂ 50

BOTTOM VIEW

C _{of Solder Contacts and}

L _{Photodiode Array Area (Note B)}

125 Nominal

C

L ^{of Solder Contacts}

of Photodiode Array Area (Note B)

C

L

PIN 1

Pb

750 ꢂ 100

Lead Free

NOTES: A. All linear dimensions are in micrometers.

B. The die is centered within the package within a tolerance of 75 μm.

C. Package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.55.

D. Contact finish is copper alloy A194 with pre-plated NiPdAu lead finish.

E. This package contains no lead (Pb).

F. This drawing is subject to change without notice.

Figure 13. Package FN — Dual Flat No-Lead Packaging Configuration

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MECHANICAL DATA

TOP VIEW

2.00 ꢂ 0.05

1.75

ꢃ 1.50

4.00

B

+ 0.30

8.00

− 0.10

3.50 ꢂ 0.05

ꢃ 0.50

ꢂ 0.05

B

A

DETAIL A

DETAIL B

5ꢁ Max

0.254

2.61 ꢂ 0.05

2.21 ꢂ 0.05

ꢂ 0.02

0.83 ꢂ 0.05

B

o

A

o

K

o

NOTES: A. All linear dimensions are in millimeters. Dimension tolerance is 0.10 mm unless otherwise noted.

B. The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.

C. Symbols on drawing A , B , and K are defined in ANSI EIA Standard 481−B 2001.

o

D. Each reel is 178 millimeters in diameter and contains 3500 parts.

E. TAOS packaging tape and reel conform to the requirements of EIA Standard 481−B.

F. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape.

G. This drawing is subject to change without notice.

Figure 14. Package FN Carrier Tape

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MANUFACTURING INFORMATION

The FN package has been tested and has demonstrated an ability to be reflow soldered to a PCB substrate.

The solder reflow profile describes the expected maximum heat exposure of components during the solder

reflow process of product on a PCB. Temperature is measured on top of component. The components should

be limited to a maximum of three passes through this solder reflow profile.

Table 13. Solder Reflow Profile

PARAMETER

Average temperature gradient in preheating

Soak time

REFERENCE

TCS3471

2.5°C/sec

t

2 to 3 minutes

Max 60 sec

Max 50 sec

Max 10 sec

260°C

soak

Time above 217°C (T1)

t

1

Time above 230°C (T2)

t

2

Time above T

−10°C (T3)

t

peak

3

Peak temperature in reflow

T

peak

Temperature gradient in cooling

Max −5°C/sec

Not to scale — for reference only

T

peak

T

3

T

2

1

Time (sec)

t

3

2

1

t

soak

Figure 15. Solder Reflow Profile Graph

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MANUFACTURING INFORMATION

Moisture Sensitivity

Optical characteristics of the device can be adversely affected during the soldering process by the release and

vaporization of moisture that has been previously absorbed into the package. To ensure the package contains

the smallest amount of absorbed moisture possible, each device is dry-baked prior to being packed for shipping.

Devices are packed in a sealed aluminized envelope called a moisture barrier bag with silica gel to protect them

from ambient moisture during shipping, handling, and storage before use.

The FN package has been assigned a moisture sensitivity level of MSL 3 and the devices should be stored under

the following conditions:

Temperature Range

Relative Humidity

Total Time

5°C to 50°C

60% maximum

12 months from the date code on the aluminized envelope — if unopened

168 hours or fewer

Opened Time

Rebaking will be required if the devices have been stored unopened for more than 12 months or if the aluminized

envelope has been open for more than 168 hours. If rebaking is required, it should be done at 50°C for 12 hours.

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PRODUCTION DATA — information in this document is current at publication date. Products conform to

specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard

warranty. Production processing does not necessarily include testing of all parameters.

LEAD-FREE (Pb-FREE) and GREEN STATEMENT

Pb-Free (RoHS) TAOS’ terms Lead-Free or Pb-Free mean semiconductor products that are compatible with the current

RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous

materials. Where designed to be soldered at high temperatures, TAOS Pb-Free products are suitable for use in specified

lead-free processes.

Green (RoHS & no Sb/Br) TAOS defines Green to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and

Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material).

Important Information and Disclaimer The information provided in this statement represents TAOS’ knowledge and

belief as of the date that it is provided. TAOS bases its knowledge and belief on information provided by third parties,

and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate

information from third parties. TAOS has taken and continues to take reasonable steps to provide representative

and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and

chemicals. TAOS and TAOS suppliers consider certain information to be proprietary, and thus CAS numbers and other

limited information may not be available for release.

NOTICE

Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this

document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised

to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems.

TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product

design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that

the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular

purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any

and all liability, including without limitation consequential or incidental damages.

TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR

USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY

RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY

UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.

LUMENOLOGY, TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced

Optoelectronic Solutions Incorporated.

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型号:	TCS34711FN
是否Rohs认证：	符合
生命周期：	Contact Manufacturer
包装说明：	VSON,
Reach Compliance Code：	unknown
风险等级：	5.59
模拟集成电路 - 其他类型：	ANALOG CIRCUIT
JESD-30 代码：	R-PDSO-N6
长度：	2 mm
功能数量：	1
端子数量：	6
最高工作温度：	70 °C
最低工作温度：	-30 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	VSON
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, VERY THIN PROFILE
座面最大高度：	0.7 mm
最大供电电压 (Vsup)：	3.3 V
最小供电电压 (Vsup)：	2.7 V
标称供电电压 (Vsup)：	3 V
表面贴装：	YES
温度等级：	OTHER
端子形式：	NO LEAD
端子节距：	0.65 mm
端子位置：	DUAL
宽度：	2.4 mm
Base Number Matches：	1

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