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  • 北京元坤伟业科技有限公司

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  • 深圳市恒达亿科技有限公司

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  • 深圳市宗天技术开发有限公司

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  • 深圳市芳益电子科技有限公司

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  • 深圳市嘉胜威科技有限公司

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产品型号TPS560200DBVR的概述

芯片TPS560200DBVR的概述 TPS560200DBVR是一款由德州仪器(Texas Instruments)公司设计的高效非隔离降压(Buck)DC-DC转换器。该芯片能够实现稳压输出,在宽广的输入电压范围内提供高达2A的输出电流,在多种电源管理应用中极具灵活性和可靠性。TPS560200DBVR适用的场合包括便携式设备、电池供电设备、工业电源管理以及各种需要稳定电源的电子设备。 此外,TPS560200DBVR具备出色的电源效率和动态响应能力,可以极大地减少能量损耗。它采用了电流模式控制架构,能够提供较快的瞬态响应以及出色的负载调整能力,使其在不同负载条件下均能保持稳定的输出电压。 芯片TPS560200DBVR的详细参数 在了解TPS560200DBVR的具体参数时,首先需要关注其输入电压范围和输出电流能力。TPS560200DBVR支持的输入电压范围为4.5V至17V,...

产品型号TPS560200DBVR的Datasheet PDF文件预览

TPS560200  
www.ti.com  
SLVSC81 SEPTEMBER 2013  
4.5V to 17V Input, 500mA Synchronous Step Down SWIFT™ Converter  
with Advanced Eco-mode™  
Check for Samples: TPS560200  
1
FEATURES  
DESCRIPTION  
The TPS560200 is an 17V, 500mA, low Iq, adaptive  
2
Integrated Monolithic 0.95Ω High Side and  
0.33Ω Low Side MOSFETs  
on-time D-CAP2™ mode synchronous monolithic  
buck converter with integrated MOSFETs in easy-to-  
use 5-pin SOT23 package.  
500mA Continuous Output Current  
Output Voltage Range: 0.8V to 6.5V  
The TPS560200 enables system designers to  
complete the suite of various end-equipment power  
bus regulators with a cost effective, low component  
count and low standby current solution. The main  
control loop for the device uses the D-CAP2™ mode  
control that provides a fast transient response with no  
external compensation components. The adaptive on-  
time control supports seamless transition between  
PWM mode at higher load conditions and advanced  
Eco-mode™ operation at light loads.  
0.8V Voltage Reference with ±1.3% Accuracy  
Over Temperature  
Advanced Auto-Skip Eco-mode™ for High  
Efficiency at Light Loads  
D-CAP2™ Mode Enables Fast Transient  
Responses  
No External Compensation Needed  
600 kHz Switching Frequency  
2 ms Internal Soft Start  
The TPS560200 also has a proprietary circuit that  
enables the device to adopt to both low equivalent  
series resistance (ESR) output capacitors, such as  
POSCAP or SP-CAP, and ultra-low ESR ceramic  
capacitors. The device operates from 4.5-V to 17-V  
VIN input. The output voltage can be programmed  
between 0.8 V and 6.5 V. The device also features a  
fixed 2 ms soft start time. The device is available in  
the 5-pin SOT23 package.  
Safe Startup into Pre-biased VOUT  
Thermal Shutdown  
–40°C to 125°C Operating Junction  
Temperature Range  
Available in 5-Pin SOT23 Packages  
APPLICATIONS  
Set Top Boxes  
Modems  
DTBs  
ASDLs  
SIMPLIFIED SCHEMATIC  
VOUT  
Lo  
VIN  
VIN  
EN  
PH  
Cin  
Co  
R1  
R2  
VSENSE  
GND  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SWIFT, Eco-mode, D-CAP2 are trademarks of Texas Instruments.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2013, Texas Instruments Incorporated  
TPS560200  
SLVSC81 SEPTEMBER 2013  
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
ORDERING INFORMATION(1)  
TJ  
PACKAGE  
PART NUMBER  
–40°C to +125°C  
5 Pin SOT23  
TPS560200DBVR/T  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
ABSOLUTE MAXIMUM RATINGS(1)  
MIN  
–0.3  
–0.3  
–0.3  
–0.6  
–2  
MAX  
20  
UNIT  
V
VIN  
Input voltage  
EN  
7
V
VSENSE  
3
V
PH  
20  
V
Output voltage  
PH 10ns Transient  
20  
V
EN  
±100  
µA  
A
Source current  
PH  
Current Limit  
Current Limit  
Sink current  
PH  
A
Human Body Model (HBM) QSS 009-105 (JESD22-A114A)  
2
kV  
V
Electrostatic Discharge  
Charged Device Model (CDM) QSS 009-147 (JESD22-C101B.01)  
500  
125  
150  
Operating junction temperature  
Storage temperature  
–40  
–65  
°C  
°C  
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
THERMAL INFORMATION  
TPS560200  
THERMAL METRIC  
UNITS  
SOT23 (5 PINS)  
θJA  
166.8  
100  
θJA  
Junction-to-ambient thermal resistance(1)  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
θJCtop  
θJB  
75.5  
29.2  
3.7  
°C/W  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
ψJB  
28.7  
N/A  
θJCbot  
(1) Test boards conditions:  
a. 2 inches x 2 inches, 2 layers, thickness: 0.062 inch  
b. 2 oz. copper traces located on the top of the PCB  
c. 2 oz. copper ground plane on the bottom of the PCB  
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ELECTRICAL CHARACTERISTICS  
TJ = –40°C to +125°C, VIN = 4.5 V to 17 V (unless otherwise noted)  
DESCRIPTION  
SUPPLY VOLTAGE (VIN PIN)  
VIN Operating input voltage  
VIN Internal UVLO threshold  
VIN Internal UVLO hysteresis  
VIN Shutdown supply current  
VIN Operating– non switching supply current  
ENABLE (EN PIN )  
CONDITIONS / SYMBOL  
MIN  
TYP  
MAX  
UNIT  
4.5  
3.9  
17  
V
V
VIN Rising  
4.35  
200  
3.7  
4.5  
mV  
µA  
µA  
EN = 0 V, VIN = 12 V  
2.0  
35  
9
VSENSE = 850 mV, VIN = 12V  
60  
95  
Rising  
1.16  
1.13  
2
1.29  
V
V
Enable threshold  
Falling  
1.05  
Internal soft start  
VSENSE ramps from 0 V to 0.8 V  
ms  
OUTPUT VOLTAGE  
25°C, VIN = 12 V, VOUT = 1.05 V, IOUT  
= 5 mA, Pulse Skipping  
0.796  
0.792  
0.804  
0.800  
0.812  
0.808  
V
V
25°C, VIN = 12 V, VOUT = 1.05 V, IOUT  
= 100mA, Continuous current mode  
Voltage reference  
VIN = 12 V, VOUT = 1.05 V, IOUT =  
100mA, Continuous current mode  
0.789  
0.800  
0.811  
V
MOSFET  
High side switch resistance(1)  
Low side switch resistance(1)  
CURRENT LIMIT  
VIN = 12 V  
VIN = 12 V  
0.50  
0.20  
0.95  
0.33  
1.50  
0.55  
Ω
Ω
LOUT = 10uH, Valley current, VOUT =  
1.05V  
Low side switch sourcing current limit  
550  
650  
775  
mA  
THERMAL SHUTDOWN  
Thermal shutdown  
170  
10  
°C  
°C  
Thermal shutdown hysteresis  
ON TIME TIMER CONTROL  
On time  
VIN = 12 V  
130  
165  
250  
200  
400  
ns  
ns  
Minimum off time  
25°C, VSENSE = 0.5V  
OUTPUT UNDERVOLTAGE PROTECTION  
Output UVP threshold  
Hiccup time  
Falling  
56%  
63%  
15  
69%  
VREF  
ms  
(1) Measured at pins  
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PIN ASSIGNMENTS  
SOT23 PACKAGE  
(TOP VIEW)  
EN  
1
5
VSENSE  
GND  
PH  
2
3
4
VIN  
PIN FUNCTIONS  
PIN  
DESCRIPTION  
NAME  
EN  
NUMBER  
1
2
3
4
5
Enable pin. Float to enable.  
GND  
PH  
Return for control circuitry and low side power MOSFET.  
The switch node.  
VIN  
Supplies the control circuitry of the power converter.  
VSENSE  
Converter feedback input. Connect to output voltage with feedback resistor divider.  
FUNCTIONAL BLOCK DIAGRAM  
VIN  
VREF  
HS  
Drive  
VSS  
VSENSE  
VREF  
Soft  
Start  
SSDONE  
START  
EN  
VIN  
XCON  
PH  
UVLO  
VREF  
Control  
Logic  
VIN  
LS  
Drive  
TON  
One-Shot  
PGND  
GND  
AGND  
PH  
Thermal  
Shutdown  
ZCD  
ZCD  
Bandgap  
Reference  
LS  
OCP  
VREF  
VREF  
PGND  
BGOK  
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OVERVIEW  
The TPS560200 is a 500-mA synchronous step-down (buck) converter with two integrated N-channel MOSFETs.  
It operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output  
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low  
ESR output capacitors including ceramic and special polymer types.  
DETAILED DESCRIPTION  
PWM Operation  
The main control loop of the TPS560200 is an adaptive on-time pulse width modulation (PWM) controller that  
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with  
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with  
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.  
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one  
shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VOUT, to  
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The  
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the  
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need  
for ESR induced output ripple from D-CAP2™ mode control.  
PWM Frequency and Adaptive On-Time Control  
TPS560200 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The  
TPS560200 runs with a pseudo-constant frequency of 600 kHz by using the input voltage and output voltage to  
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the  
output voltage; therefore, when the duty ratio is VOUT/VIN, the frequency is constant.  
Advanced Auto-Skip Eco-mode™ Control  
The TPS560200 is designed with advanced auto-skip Eco-mode™ to increase higher light load efficiency. As the  
output current decreases from heavy load condition, the inductor current is also reduced. If the output current is  
reduced enough, the inductor current ripple valley reaches the zero level, which is the boundary between  
continuous conduction and discontinuous conduction modes. The rectifying low-side MOSFET is turned off when  
its zero inductor current is detected. As the load current further decreases the converter run into discontinuous  
conduction mode. The on-time is kept approximately the same as is in continuous conduction mode. The off-time  
increases as it takes more time to discharge the output capacitor to the level of the reference voltage with  
smaller load current. The transition point to the light load operation IOUT(LL) current can be calculated in  
Equation 1  
V -V  
IN OUT  
×V  
)
OUT  
(
1
IOUT(LL)  
=
×
2×LOUT×fsw  
V
IN  
(1)  
Soft Start and Pre-Biased Soft Start  
The TPS560200 has an internal 2ms soft-start. When the EN pin becomes high, internal soft-start function  
begins ramping up the reference voltage to the PWM comparator.  
The TPS560200 contains a unique circuit to prevent current from being pulled from the output during startup if  
the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft  
start becomes greater than feedback voltage VVSENSE), the controller slowly activates synchronous rectification by  
starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a  
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.  
This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VOUT) starts and  
ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to  
normal mode operation.  
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Current Protection  
The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The  
switch current is monitored by measuring the low-side FET switch voltage between the PH pin and GND. This  
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature  
compensated.  
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,  
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current  
decreases linearly. The average value of the switch current is the load current Iout. The TPS560200 constantly  
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.  
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented  
per each switching cycle and the converter maintains the low-side switch on until the measured voltage is below  
the voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching  
cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in  
the same manner.  
There are some important considerations for this type of over-current protection. The peak current is the average  
load current plus one half of the peak-to-peak inductor current. The valley current is the average load current  
minus one half of the peak-to-peak inductor current. Since the valley current is used to detect the overcurrent  
threshold, the load current is higher than the over-current threshold. Also, when the current is being limited, the  
output voltage tends to fall as the demanded load current may be higher than the current available from the  
converter. This protection is non-latching. When the VSENSE voltage becomes lower than 63% of the target  
voltage, the UVP comparator detects it. After 7 µs detecting the UVP voltage, device shuts down and re-starts  
after hiccup time.  
When the over-current condition is removed, the output voltage returns to the regulated value.  
Thermal Shutdown  
TPS560200 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 170°C),  
the device is shut off. This is non-latch protection.  
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TYPICAL CHARACTERISTICS  
VIN = 12 V, TA = 25°C (unless otherwise noted).  
100  
80  
60  
40  
20  
0
6
EN = 0 V  
5
4
3
2
1
0
±50  
0
50  
100  
150  
±50  
0
50  
100  
150  
C001  
C002  
TJ Junction Temperature (ƒC)  
TJ Junction Temperature (ƒC)  
Figure 1. SUPPLY CURRENT vs JUNCTION TEMPERATURE  
Figure 2. SHUTDOWN CURRENT vs  
JUNCTION TEMPERATURE  
40  
30  
20  
10  
0
700  
675  
650  
625  
600  
575  
550  
525  
500  
IOUT = 500 mA  
VOUT = 1.05 V  
VOUT = 3.3 V  
VOUT = 1.8 V  
±10  
0
2
4
6
8
10  
4
6
8
10  
12  
14  
16  
18  
C003  
C004  
EN Input Voltage (V)  
VIN - Input Voltage (V)  
Figure 3. EN INPUT CURRENT vs EN INPUT VOLTAGE  
Figure 4. SWITCHING FREQUENCY vs INPUT VOLTAGE  
800  
700  
600  
500  
0.806  
IO = 100 mA  
0.804  
0.802  
0.800  
0.798  
0.796  
0.794  
VOUT = 3.3 V  
400  
300  
VOUT = 1.05 V  
200  
100  
VOUT = 1.8 V  
0
0.0  
0.1  
0.2  
0.3  
0.4  
0.5  
±50  
0
50  
100  
150  
C005  
C006  
IO - Output Current (A)  
TJ Junction Temperature (ƒC)  
Figure 5. SWITCHING FREQUENCY vs OUTPUT CURRENT  
Figure 6. VSENSE VOLTAGE vs JUNCTION TEMPERATURE  
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APPLICATION INFORMATION  
Design Guide  
To begin the design process, the user must know a few application parameters:  
Input voltage range  
Output voltage  
Output current  
Output voltage ripple  
Input voltage ripple  
U1  
TPS560200  
L1 10µH  
VIN 4.5-17V  
VOUT 1.05V, 0.5 A  
4
1
5
3
VIN  
PH  
C5  
R1  
C1  
C2  
C3  
C4  
open  
6.19k  
10µF  
10µF  
10µF  
0.1µF  
EN  
R2  
20.0k  
2
VSENSE  
GND  
Figure 7. Typical Application Schematic  
Output Voltage Resistors Selection  
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use  
1% tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT  
.
To improve efficiency at light loads consider using larger value resistors, high resistance is more susceptible to  
noise, and the voltage errors from the VSENSE input current are more noticeable.  
R1´0.8 V  
R2 =  
VOUT -0.8V  
(2)  
Output Filter Selection  
The output filter used with the TPS560200 is an LC circuit. This LC filter has double pole at:  
1
F
P
=
2p L  
x C  
OUT  
OUT  
(3)  
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal  
gain of the TPS560200. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain  
rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero  
that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the  
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole  
of Equation 3 is located below the high frequency zero but close enough that the phase boost provided be the  
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the  
values recommended in Table 1  
Table 1. Recommended Component Values  
L1  
Output Voltage  
(V)  
R1  
(kΩ)  
R2  
(kΩ)  
C5  
(pF)  
C3 + C4  
(µF)  
(µH)  
Typ  
10  
Min  
Max  
1.0  
1.05  
1.2  
1.5  
1.8  
2.5  
4.99  
6.19  
10.0  
17.4  
24.9  
42.2  
20.0  
20.0  
20.0  
20.0  
20.0  
20.0  
10 + 10  
10 + 10  
10 + 10  
10 + 10  
10 + 10  
10 + 10  
10  
10  
10  
optional  
optional  
10  
10  
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Table 1. Recommended Component Values (continued)  
L1  
Output Voltage  
R1  
(kΩ)  
R2  
(kΩ)  
C5  
(pF)  
C3 + C4  
(µF)  
(µH)  
Typ  
10  
(V)  
Min  
Max  
3.3  
5.0  
61.9  
105  
20.0  
20.0  
optional  
optional  
10 + 10  
10 + 10  
10  
Since the DC gain is dependent on the output voltage, the required inductor value increases as the output  
voltage increases. Additional phase boost can be achieved by adding a feed forward capacitor (C5) in parallel  
with R1. The feed forward capacitor is most effective for output voltages at or above 1.8 V.  
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,  
Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak  
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 600 kHz for  
fSW  
.
Use 600 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS  
current of Equation 6.  
V
- V  
V
IN(max)  
OUT  
OUT  
I
=
x
LPP  
V
L
x
fsw  
IN(max)  
OUT  
(4)  
(5)  
ILPP  
I
= I  
OUT  
+
LPEAK  
2
1
2
2
I
=
I
+
I
LOUT(RMS)  
OUT  
LPP  
12  
(6)  
For this design example, the calculated peak current is 0.582 A and the calculated RMS current is 0.502 A. The  
inductor used is a Würth 744777910 with a peak current rating of 2.6 A and an RMS current rating of 2 A.  
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54628 is intended for use  
with ceramic or other low ESR capacitors. The recommended values are given in Table 1. Use Equation 7 to  
determine the required RMS current rating for the output capacitor.  
V
x (V - V  
)
OUT  
IN  
OUT  
I
=
COUT(RMS)  
12 x V x L  
x fsw  
IN  
OUT  
(7)  
For this design two MuRata GRM32DR61E106KA12L 10µF output capacitors are used. The typical ESR is 2 mΩ  
each. The calculated RMS current is 0.047 A and each output capacitor is rated for 3A.  
Input Capacitor Selection  
The TPS560200 requires an input decoupling capacitor and a bulk capacitor is needed depending on the  
application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1 µF  
capacitor (C2) from pin 4 to ground is optional to provide additional high frequency filtering. The capacitor voltage  
rating needs to be greater than the maximum input voltage.  
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APPLICATION CURVES  
VIN = 12 V, VOUT = 1.05 V, TA = 25°C (unless otherwise noted).  
100  
90  
90  
80  
70  
60  
80  
70  
VIN = 5 V  
60  
VIN = 12 V  
VIN = 12 V  
50  
40  
30  
20  
10  
0
VIN = 5 V  
50  
40  
30  
20  
10  
0
0.0  
0.1  
0.2  
0.3  
0.4  
0.5  
0.001  
0.01  
0.1  
1
C015  
C016  
Output Current - A  
Output Current - A  
Figure 8. Efficiency  
Figure 9. Light Load Efficiency  
1.5  
1.0  
0.50  
0.40  
VIN = 5 V  
0.30  
IOUT = 0.25 A  
VIN = 12 V  
0.20  
0.5  
0.10  
0.0  
0.00  
±0.10  
±0.20  
±0.30  
±0.40  
±0.50  
±0.5  
±1.0  
±1.5  
0.0  
0.1  
0.2  
0.3  
0.4  
0.5  
4
6
8
10  
12  
14  
16  
18  
C017  
C018  
Output Current - A  
Input Voltage - V  
Figure 10. Load Regulation  
Figure 11. Line Regulation  
60  
180  
V
= 50 mV/div (ac coupled)  
OUT  
40  
20  
120  
60  
Phase  
0
0
Gain  
-20  
-40  
-60  
-60  
-120  
-180  
I
= 200 mA/div  
OUT  
125 mA to 375 mA load step  
slew rate = 500 mA / µsec  
100  
1000  
10000  
100000  
1000000  
C019  
Frequency - Hz  
Time = 200 µs/div  
Figure 13. Transient Response, 25% to 75% Load Step  
Figure 12. Loop Response, IOUT = 0.25 A  
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APPLICATION CURVES (continued)  
VIN = 12 V, VOUT = 1.05 V, TA = 25°C (unless otherwise noted).  
V
= 5 V/div  
IN  
V
= 50 mV/div (ac coupled)  
OUT  
EN = 5 V/div  
I
= 200 mA/div  
OUT  
10 mA to 250 mA load step  
slew rate = 500 mA / µsec  
V
= 500 mV/div  
OUT  
Time = 2 ms/div  
Time = 200 µs/div  
Figure 14. Transient Response, 2% to 50% Load Step  
Figure 15. Start Up Relative to EN  
V
= 20 mV/div (ac coupled)  
V
= 20 mV/div (ac coupled)  
OUT  
OUT  
PH = 5 V/div  
PH = 5 V/div  
Time = 1 µs/div  
Figure 16. Output Ripple, IOUT = 500 mA  
Time = 5 µs/div  
Figure 17. Output Ripple, IOUT = 30 mA  
V
= 20 mV/div (ac coupled)  
OUT  
PH = 5 V/div  
Time = 2 ms/div  
Figure 18. Output Ripple, IOUT = 0 mA  
Copyright © 2013, Texas Instruments Incorporated  
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11  
Product Folder Links: TPS560200  
TPS560200  
SLVSC81 SEPTEMBER 2013  
www.ti.com  
LAYOUT GUIDELINES  
The VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor. Care should be taken to  
minimize the loop area formed by the bypass capacitor connection. the VIN pin, and the GND pin of the IC. The  
typical recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the optimum  
placement is closest to the VIN and GND pins of the device. An additional high frequency bypass capacitor may  
be added. See Figure 19 for a PCB layout example. The GND pin should be tied to the PCB ground plane at the  
pin of the IC. The PH pin should be routed to a small copper area directly adjacent to the pin. Make the  
circulating loop from PH to the output inductor, output capacitors and back to GND as tight as possible while  
preserving adequate etch width to reduce conduction losses in the copper. Connect the exposed thermal pad to  
bottom or internal layer ground plane using vias as shown. Additional vias may be used adjacent to the IC to tie  
top side copper to the internal or bottom layer copper. The additional external components can be placed  
approximately as shown. It may be possible to obtain acceptable performance with alternate layout schemes,  
however this layout has been shown to produce good results and is intended as a guideline.  
VIN  
VIN  
GND  
HIGH FREQENCY  
OUTPUT  
BYPASS  
INDUCTOR  
CAPACITOR  
VIN  
PH  
GND  
EN  
VOUT  
VIN  
INPUT  
BYPASS  
CAPACITOR  
TO ENABLE  
CONTROL  
VSENSE  
OUTPUT  
FILTER  
CAPACITOR  
GND  
FEEDBACK  
GND  
RESISTORS  
OPTIONAL  
FEED FORWARD  
CAPACITOR  
VIA to Ground Plane  
Figure 19. Typical Layout  
12  
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Product Folder Links: TPS560200  
 
PACKAGE OPTION ADDENDUM  
www.ti.com  
26-Sep-2013  
PACKAGING INFORMATION  
Orderable Device  
TPS560200DBVR  
TPS560200DBVT  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 125  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
ACTIVE  
SOT-23  
SOT-23  
DBV  
5
5
3000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
Level-1-260C-UNLIM  
L562  
L562  
ACTIVE  
DBV  
250  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
-40 to 125  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
27-Sep-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPS560200DBVR  
TPS560200DBVT  
SOT-23  
SOT-23  
DBV  
DBV  
5
5
3000  
250  
178.0  
178.0  
9.0  
9.0  
3.23  
3.23  
3.17  
3.17  
1.37  
1.37  
4.0  
4.0  
8.0  
8.0  
Q3  
Q3  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
27-Sep-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TPS560200DBVR  
TPS560200DBVT  
SOT-23  
SOT-23  
DBV  
DBV  
5
5
3000  
250  
180.0  
180.0  
180.0  
180.0  
18.0  
18.0  
Pack Materials-Page 2  
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