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  • 北京元坤伟业科技有限公司

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  • TPS65123RGTR
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • TPS65123RGTR 现货库存
  • 数量9000 
  • 厂家TI 
  • 封装QFN-16 
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  • 深圳市欧立现代科技有限公司

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  • TPS65123RGTR
  • 数量900 
  • 厂家TI 
  • 封装SMD 
  • 批号24+ 
  • ★★专业IC现货,诚信经营,市场最优价★★
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  • 深圳市雅维特电子有限公司

     该会员已使用本站15年以上
  • TPS65123RGTR
  • 数量20000 
  • 厂家TI 
  • 封装深圳原装现货0755-83975781 
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  • 深圳市得捷芯城科技有限公司

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  • TPS65123RGTR
  • 数量10048 
  • 厂家TI(德州仪器) 
  • 封装QFN16 
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  • 深圳市得捷芯城科技有限公司

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  • TPS65123RGTR
  • 数量3842 
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  • 上海磐岳电子有限公司

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  • 北京中其伟业科技有限公司

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  • 深圳市和诚半导体有限公司

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  • 万三科技(深圳)有限公司

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  • 数量660000 
  • 厂家Texas Instruments(德州仪器) 
  • 封装16-VFQFN Exposed Pad 
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  • 深圳市芯福林电子有限公司

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  • 深圳市一线半导体有限公司

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  • 深圳市创思克科技有限公司

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  • 深圳市芯脉实业有限公司

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  • TPS65123RGTR
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  • 深圳市恒益昌科技有限公司

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产品型号TPS65123RGTR的概述

TPS65123RGTR芯片概述 TPS65123RGTR是由德州仪器(Texas Instruments,TI)公司开发的一款高效能电源管理芯片,主要用于驱动液晶显示器(LCD)面板,特别是电视和显示器中的显示控制电路。该芯片具有多种功能,能够提供多种输出电压,以满足不同LCD面板的需求。TPS65123RGTR在现代显示器设计中具有重要价值,因其在功能、效率和集成度上的优越表现而广受欢迎。 TPS65123RGTR详细参数 1. 输入电压范围: TPS65123RGTR的输入电压范围为3V到16V,支持多种电源供电方案。 2. 输出电压: 该芯片提供多个输出电压,通常包括VGH(高电压供电)、VGL(负电压供电)和VCOM(共模电压). 3. 输出电流: TPS65123RGTR具有超过100mA的输出电流,足以驱动大多数LCD面板的需求。 4. 工作频率: 集成了高频开关调节器,...

产品型号TPS65123RGTR的Datasheet PDF文件预览

TPS65120, TPS65121, TPS65123, TPS65124  
www.ti.com  
SLVS531AJUNE 2004REVISED MARCH 2005  
SINGLE-INDUCTOR QUADRUPLE-OUTPUT  
TFT LCD POWER SUPPLY  
FEATURES  
Automatic or Programmable Power  
Sequencing  
Main Output, VMAIN  
Complete 1 mm Component Profile Solution  
2.5 V to 5.5 V Input Voltage Range  
Output Short Circuit Protected  
16-Pin QFN Package (3 × 3 × 0,9 mm)  
– Adjustable Voltage, 3.0 V to 5.6 V/25 mA  
– Post-Regulated for Low Ripple (5mVPP  
– ±0.8% Typical Accuracy  
– Efficiency up to 83%  
)
Positive Output, VGH  
APPLICATIONS  
– Adjustable Voltage up to 20 V/2 mA  
– ±3% Typical Accuracy  
Small Form Factor a-Si and LTPS TFT LCD  
Cell Phones, Smart Phones  
PDAs, Pocket PCs  
Portable DVD  
Digital-Still Cameras, Camcorders  
Handheld Instruments  
Negative Output, VGL  
– Adjustable Voltage down to -18 V/2 mA  
– ±3% Typical Accuracy  
Auxiliary 1.8 V/3.3 V Linear Regulator  
Portable GPS  
Car Navigation Systems  
DESCRIPTION  
The TPS6512x DC-DC converter supplies all three voltages required by amorphous-silicon (a-Si) and  
low-temperature poly-silicon (LTPS) TFT-LCD displays. The compact layout of the TPS6512x uses a single  
inductor to generate independently-regulated positive and negative outputs. A free-running variable peak current  
PWM control scheme time-multiplexes the inductor between outputs. This control architecture operates at a  
pseudo-fixed-frequency to provide fast response to line and load transients while maintaining a relatively  
constant switching frequency and high efficiency over a wide range of input and output voltages. Due to the high  
switching frequency capability of the device, inexpensive and ultra-thin 8.2 or 10 µH inductors can be used.  
The main output, VMAIN, is post-regulated to provide a low-ripple source drive voltage for the LCD display. The  
auxiliary outputs generate a boosted output voltage, VGH, up to 20 V, and a negative output voltage, VGL, down to  
-18 V for the LCD gate drive. The device has internal current limiting for high reliability under fault conditions.  
Additionally, the device offers a fixed output linear regulator for the LCD logic circuitry.  
100  
90  
TPS65123  
D1  
80  
70  
60  
VGL  
VIN  
SWN  
VIN  
R3  
R4  
C1  
2.2 µ F  
down to −18 V/2 mA  
2.7 V to 5.5 V  
L1  
10µH  
RUN  
EN  
C3  
100 nF  
SWP  
FBL  
50  
40  
30  
20  
10  
0
GATE  
VGH  
VGH  
VMAIN  
VMAIN  
FBM  
R5  
R6  
up to 20 V/2 mA  
3.0 V to 5.3 V/25 mA  
R1  
R2  
C2  
100 nF  
BOOT  
C5  
FBH  
C4  
1µ F  
220 nF  
PGND  
AGND  
V
IN  
− Input Voltage − V  
A
A
I
− Load Current − mA  
BOOT  
Figure 1. Typical Application  
Figure 2. Core Converter Efficiency  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
 
TPS65120, TPS65121, TPS65123, TPS65124  
www.ti.com  
SLVS531AJUNE 2004REVISED MARCH 2005  
These devices have limited built-in ESD protection. The leads should be shorted together or the device  
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.  
ORDERING INFORMATION  
TA  
INTEGRATED  
LINEAR REGULATOR  
POWER SEQUENCING  
PACKAGE  
PART NUMBER(1)  
PACKAGE  
MARKING  
Fixed 3.3V output voltage  
Automatic Power-Up/Down  
Automatic Power-Up/Down  
Automatic Power-Up/Down  
3 × 3 QFN-16  
3 × 3 QFN-16  
3 × 3 QFN-16  
3 × 3 QFN-16  
TPS65120RGT  
TPS65121RGT  
TPS65123RGT  
TPS65124RGT  
BKA  
BKB  
BKC  
BKD  
Fixed 1.8V output voltage  
-40 to 85°C  
NO  
NO  
Programmable  
Power-Up/Down  
(1) The xyz package is available in tape and reel. Add R suffix (xyzR) to order quantities of TBD parts. Add T suffix (xyzT) to order  
quantities of 250 parts.  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range (unless otherwise noted)(1)  
UNIT  
VIN  
-0.3 V to +6 V  
VIN - 24 V to VIN +0.3 V  
- 0.3 V to +23 V  
- 0.3 V to +21 V  
- 0.3 V to +6 V  
- 0.3 V to +6.2 V  
-0.3 V to VIN + 0.3 V  
Internally limited  
-40°C to 85°C  
Input voltage(2)  
Voltage(2)  
SWN  
SWP  
VGH  
VMAIN, LDOIN, LDOOUT, ENVGL, ENVGH  
BOOT  
(2)  
Input voltage at GATE, EN, RUN  
Power dissipation  
Operating temperature range  
Maximum operating junction temperature, TJ(max)  
Storage temperature range  
135°C  
65°C to 150°C  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltage values are with respect to network ground terminal.  
DISSIPATION RATINGS(1)  
PACKAGE  
RθJA  
DERATING FACTOR ABOVE TA = 25°C  
RGT  
68°C/W  
15mW/°C  
(1) Maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power  
dissipation at any allowable ambient temperature is PD = [TJ(max)-TA]/ θJA  
.
2
TPS65120, TPS65121, TPS65123, TPS65124  
www.ti.com  
SLVS531AJUNE 2004REVISED MARCH 2005  
ELECTRICAL CHARACTERISTICS  
VIN = 3.6 V, EN = RUN = VIN, L = 10 µH, TA = -40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)  
PARAMETER  
CONVERTER STAGE  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
R
R
R
L_MAIN330 at VMAIN = 5 V,  
L_VGH12 kat VGH = 12 V,  
L_VGL12 kat VGL = -12 V,  
Input voltage for full load operation  
Minimum input voltage for start-up  
2.7  
5.5  
V
V
VLDOIN= GND, TA = -40°C to 85°C  
VIN  
RL_MAIN660 at VMAIN = 5 V,  
RL_VGH24 kat VGH = 12 V,  
RL_VGL24 kat VGL = -12 V,  
2.5  
VLDOIN= GND, TA = -20°C to 85°C  
RL_MAIN = 250 at VMAIN = 5 V  
VLDOIN= ENVGH = ENVGL = GND  
f
Switching frequency  
Output power on VGH  
4.0  
MHz  
mW  
V
V
V
V
V
V
V
V
IN2.7 V  
IN2.5 V  
IN2.7 V  
IN2.5 V  
IN2.5 V  
IN2.7 V  
IN3 V  
35  
15  
PGH  
35  
PGL  
Output power on VGL  
mW  
mW  
15  
60  
120  
150  
250  
Total output power on  
VBOOT + VGH + VGL  
PTOT  
IN4.5 V  
VMAIN = 5.0 V, IBOOT = 20 mA,  
VGH = 15 V, VGL = -10 V,  
η
Power efficiency  
83%  
IGH = IGL = 100 µA, VLDOIN = GND  
ILIM  
P-MOS1 current limit  
2.7 V VIN5.5 V  
2.7 V VIN5.5 V  
VIN = VGS = 3.6 V  
VIN = VGS = 2.5 V  
VBOOT = VGS = 3.7 V  
VBOOT = VGS = 5 V  
150  
65  
200  
mA  
mA  
ISTART-UP  
P-MOS1 start-up current limit  
2.5  
4.3  
6.9  
3.5  
2.3  
P-MOS1 switch on-resistance  
N-MOS1 switch on-resistance  
3.8  
1.9  
rDS(ON)  
1.4  
P-MOS1 leakage current  
N-MOS1 leakage current  
0.01  
0.01  
VDS = 6 V, TA = 25°C  
µA  
VGS = VBOOT = 5.5 V, VSWP = 2 V,  
IBOOT = ID = 50 mA  
N-MOS2 + P-MOS2 forward voltage drop  
N-MOS3 + D1 forward voltage drop  
400  
900  
600  
mV  
mV  
VGS = VBOOT = 5.5 V, VSWP = 2 V,  
IGH = ID = 50 mA  
1100  
CONVERTER SUPPLY CURRENT  
Quiescent current into VIN  
IMAIN = IGH = IGL = 0 mA,  
VGH = +15 V, VGL = -15 V,  
VMAIN = 5 V, VFBH = VFBM = +1.5 V,  
VFBL = -0.2 V, VBOOT = 5.25 V,  
140  
30  
170  
60  
Quiescent current into BOOT  
IQ  
µA  
µA  
Quiescent current into VGH  
0.1  
0.1  
1
1
VLDOIN = GND, EN = RUN = VIN  
TA = 25°C  
,
ISD  
Shutdown current  
TA = 25°C  
3
TPS65120, TPS65121, TPS65123, TPS65124  
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SLVS531AJUNE 2004REVISED MARCH 2005  
ELECTRICAL CHARACTERISTICS (continued)  
VIN = 3.6 V, EN = RUN = VIN, L = 10 µH, TA = -40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
MAIN OUTPUT  
VMAIN  
Main output voltage range  
3.0  
25  
5.6  
V
V
MAIN5.3 V  
MAIN5.3 V  
IMAIN  
Maximum main output current  
mA  
V
7.5  
2.7 V VIN5.5 V, 100 µA IMAIN25 mA,  
TA = -20°C to 50°C  
1.203 1.213 1.223  
1.195 1.213 1.231  
V
V
VFBM  
Feedback regulation voltage  
2.7 V VIN5.5 V,  
0 mA IMAIN25 mA  
IFBM  
Feedback input bias current  
Load regulation  
VFBM= VREF  
0.01  
0.006  
130  
5
0.1  
µA  
%/mA  
mV  
IMAIN = 0 to 25 mA, VMAIN = 5 V  
IMAIN = 10 mA  
Minimum dropout voltage  
Main output voltage ripple  
Short-circuit current limit  
IMAIN = 10 mA  
mVP-P  
mA  
ISC_MAIN  
VBOOT = 5.5 V  
50  
Discharge resistor for power-down se-  
quence  
RDIS_VMAIN  
10  
kΩ  
VGH OUTPUT  
VGH  
IGH  
VGH output voltage range  
VIN + 0.5  
20  
6
V
mA  
kΩ  
Maximum DC output current  
VGH precharge resistor  
Feedback regulation voltage  
Feedback input bias current  
Load regulation  
1
VFBH  
IFBH  
2.7 V VIN5.5 V, 0 mA IGH2 mA  
VFBH = 0 V  
1.177 1.213 1.249  
V
0.01  
-0.11  
0.01  
0.1  
µA  
IGH = 0 to 2 mA, VGH = 15 V  
VIN = 2.7 V to 5.5 V, IGH = 100 µA  
%/mA  
%/V  
Line regulation  
200 µA load, VGH = 15 V,  
COUT = 220 nF, CFF = 10 pF  
VGH output voltage ripple  
20  
10  
mV  
Discharge resistor for power-down se-  
quence  
RDIS_VGH  
kΩ  
VGL OUTPUT  
VGL  
IGL  
VGL Output voltage range  
-18  
-2.5  
6
V
mA  
V
Maximum DC output current  
Feedback regulation voltage  
Feedback input bias current  
Load regulation  
VFBL  
IFBL  
2.7 V VIN5.5 V, 0 mA IGL2 mA  
VFBL = 0 V  
-0.036  
0
0.01  
0.13  
0.1  
0.036  
0.1  
µA  
IGL = 0 to 2 mA, VGL = -15 V  
VIN = 2.7 V to 5.5 V, IGL = 100 µA  
%/mA  
%/V  
Line regulation  
200 µA load, VGL = -15 V,  
COUT = 220 nF  
VGL output voltage ripple  
20  
mV  
4
TPS65120, TPS65121, TPS65123, TPS65124  
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SLVS531AJUNE 2004REVISED MARCH 2005  
ELECTRICAL CHARACTERISTICS (continued)  
VIN = 3.6 V, EN = RUN = VIN, L = 10 µH, TA = -40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
LINEAR REGULATOR STAGE - AUXILIARY OUTPUT  
VLDOIN  
Input voltage range  
2.5  
1.8  
20  
5.8  
V
V
VLDOIN  
-0.5  
VLDOOUT  
Output voltage range  
ILDOOUT  
ISC_LDO  
Maximum output current  
Short-circuit current limit  
Minimum dropout voltage  
mA  
mA  
mV  
VLDOOUT = 0 V  
50  
ILDOOUT = 10 mA  
400  
2.5 V VLDOIN 5.5 V,  
0 mA ILDOOUT20 mA  
Total accuracy  
Load regulation  
Line regulation  
±3%  
ILDOOUT = 0 to 20 mA  
0.006  
0.013  
%/mA  
%/V  
VLDOIN = VLDOOUT + 0.5 V (min 2.5 V)  
to 5.5 V, ILDOOUT = 20 mA  
VLDOIN = VLDOOUT + 0.4 V (min 2.5 V),  
TA = 25°C  
IQ_LDO  
Linear regulator quiescent current  
Linear regulator shutdown current  
11  
20  
1
µA  
µA  
ISD_LDO  
GATE = VIN  
0.2  
GATE DRIVER  
Gate output pull-down resistance  
VGATE < 500 mV  
100  
100  
kΩ  
kΩ  
V
Gate output pull-up resistance  
High level input voltage  
Low level input voltage  
VIH  
VIL  
1.4  
1.4  
0.4  
2.3  
V
UNDERVOLTAGE LOCKOUT  
VUVLO  
Undervoltage lockout threshold  
VIN falling  
2.15  
V
LOGIC SIGNALS EN, RUN, ENVGL, ENVGH  
VIH  
VIL  
High level input voltage  
Low level input voltage  
V
V
0.4  
0.1  
0.1  
ENVGL, ENVGH = VIN or GND (TPS65124)  
EN, RUN = VIN  
0.01  
0.01  
100  
ILKG  
Logic input leakage current  
µA  
EN, RUN pin pull-down resistance  
EN, RUN 0.4 v  
kΩ  
5
TPS65120, TPS65121, TPS65123, TPS65124  
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SLVS531AJUNE 2004REVISED MARCH 2005  
PIN ASSIGNMENTS  
TPS65120/1/2  
(TOP VIEW)  
TPS65123  
(TOP VIEW)  
TPS65124  
(TOP VIEW)  
16 15 14 13  
16 15 14 13  
16 15 14 13  
Exposed  
EN  
RUN  
1
1
2
3
12  
12  
1
EN  
EN  
RUN  
12  
PGND  
BOOT  
VGH  
PGND  
BOOT  
VGH  
PGND  
BOOT  
VGH  
Exposed  
Thermal Die*  
AGND  
Exposed  
Thermal Die*  
AGND  
2
3
11  
10  
9
11  
10  
2
3
RUN  
AGND  
AGND  
11  
Thermal Die*  
AGND  
LDOIN  
10  
9
ENVGL  
ENVGH  
4
FBH  
4
9
4
FBH  
LDOOUT  
FBH  
5
6
5
6
7
7
8
8
5
6
7
8
TERMINAL FUNCTIONS  
TERMINAL  
I/O  
DESCRIPTION  
NAME  
NO.  
VIN  
15  
I
This is the input voltage pin of the device.  
This pin can either be the gate driver output to an external small P-Channel MOSFET (see application  
GATE  
RUN  
EN  
16  
2
I/O section), or an active high control input. Pulling GATE above the 1.4 V logic-high level and RUN to a logic-low  
level disables the integrated active power-down sequencing.  
RUN controls the external P-Channel MOSFET. This pin must be terminated and not be left floating. Forcing  
this pin to a logic-high level turns on the external MOSFET switch.  
I
This is the enable pin of the multiple-output dc-to-dc converter. This pin must be terminated and not be left  
1
I
floating. A simultaneous logic-high level on EN and RUN enables the converter and a logic-low shuts down  
the device.  
SWN  
SWP  
PGND  
VGH  
14  
13  
12  
10  
I/O Connect the inductor to this pin. This pin is connected to the source of the high-side MOSFET switch.  
I/O Connect the inductor to this pin. This pin is connected to the drain of the low-side MOSFET switch.  
O
O
Power ground. Connect to AGND underneath the IC.  
Positive output  
Provides a bootstrapped supply for the rectifier MOSFET driver, enabling the gate of the MOSFET to be  
driven above the output voltage.  
BOOT  
11  
O
VMAIN  
FBH  
8
9
I
I
Main output  
Feedback pin for the positive output voltage divider. Regulates to 1.213 V nominal.  
Feedback pin for the negative output voltage divider. Regulates to 0 V nominal. Connect feedback resistor  
divider between VGL and main output.  
FBL  
5
6
I
I
FBM  
AGND  
Feedback pin for the main output voltage divider. Regulates to 1.213V nominal.  
Analog ground. Connect to power ground (PGND) underneath IC. Pins 3 and 4 are only used for AGND in  
TPS65123.  
7, 3, 4  
Auxiliary linear regulator input. If this pin is connected to GND, the voltage regulator is disabled  
(TPS65120/1/2). The low-dropout series-pass regulator (LDO) is enabled according to the GATE signal  
timing.  
LDOIN  
3
I
LDOOUT  
ENVGL  
ENVGH  
4
3
4
O
I
Auxiliary linear regulator output (TPS65120/1/2).  
Enable pin for negative output (TPS65124). This pin should be terminated and not be left floating.  
Enable pin for positive output (TPS65124). This pin should be terminated and not be left floating.  
I
6
TPS65120, TPS65121, TPS65123, TPS65124  
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SLVS531AJUNE 2004REVISED MARCH 2005  
FUNCTIONAL BLOCK DIAGRAM - TPS65120/1/2/3  
VIN  
GATE  
Power Down Seq Off  
Undervoltage  
Lockout  
100kR  
Bias Supply  
Current Limit  
Comparator  
P−MOS1  
VMAIN  
T
on  
Oscillator  
RUN  
EN  
S
Min Off Time  
SWN  
EN  
R
V
REF  
REF  
BOOT  
SWP  
VGH  
D1  
N−MOS3  
BOOT  
R
DIS_VGH  
V
R
R
FBH  
FBL  
P−MOS2  
N−MOS2  
BOOT  
BOOT  
FBM  
Control  
Logic  
Power Up/Down  
Sequencer  
LDO  
DIS_VMAIN  
VMAIN  
EN  
R
VMAIN  
Power Down Seq Off  
V
= 1.213V  
REF  
BOOT  
Bandgap  
N−MOS1  
AGND  
PGND  
LDOIN  
LDO  
LDOOUT  
EN_LDOAUX  
NOT PRESENT IN TPS65123  
7
TPS65120, TPS65121, TPS65123, TPS65124  
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SLVS531AJUNE 2004REVISED MARCH 2005  
FUNCTIONAL BLOCK DIAGRAM - TPS65124  
GATE  
VIN  
Power Down Seq Off  
Undervoltage  
Lockout  
100kR  
Bias Supply  
Current Limit  
P−MOS1  
Comparator  
on  
VMAIN  
T
Oscillator  
RUN  
EN  
S
Min Off Time  
SWN  
SWP  
EN  
R
V
V
REF  
REF  
BOOT  
D1  
N−MOS3  
BOOT  
VGH  
R
DIS_VGH  
R
R
Control  
Logic  
FBH  
FBL  
P−MOS2  
N−MOS2  
BOOT  
FBM  
BOOT  
Power Up/Down  
Sequencer  
LDO  
DIS_VMAIN  
VMAIN  
EN  
VMAIN  
R
Power Down Seq Off  
ENVGH  
ENVGL  
BOOT  
N−MOS1  
AGND  
PGND  
V
= 1.213V  
REF  
Bandgap  
8
TPS65120, TPS65121, TPS65123, TPS65124  
www.ti.com  
SLVS531AJUNE 2004REVISED MARCH 2005  
PARAMETER MEASUREMENT INFORMATION  
TPS65120  
D1  
V
V
VIN  
SWN  
GL  
IN  
down to −18 V/2 mA  
2.7 V to 5.5 V  
R3  
R4  
C1  
2.2 mF  
L1  
10m H  
RUN  
EN  
C3  
220 nF  
SWP  
FBL  
GATE  
VGH  
V
VMAIN  
FBM  
V
MAIN  
GH  
3.0 V to 5.3 V/20 mA  
up to 20 V/2 mA  
R1  
R2  
R5  
R6  
BOOT  
C2  
220 nF  
C5  
220 nF  
FBH  
C4  
1
mF  
LDOIN  
LDOOUT  
PGND  
V
AUX  
3.3 V/20 mA  
AGND  
C6  
220 nF  
A
A
List of Components:  
U = TPS6512x  
1
L = EPCOS SIMID1812-C  
1
D = ZETEX ZUMD54C  
1
C
X
= X5R/X7R  
TYPICAL CHARACTERISTICS  
Table of Graphs  
FIGURE  
η
Core converter efficiency  
Main output efficiency  
vs Load current  
vs Input voltage  
vs Load current  
vs Input voltage  
3
4
5
6
VMAIN  
Output ripple voltage  
DC output voltage  
7
vs Load current  
8
Load transient response  
9
VGH, VGL  
Positive, negative output ripple voltage  
DC output voltage  
10, 11  
12  
13  
14  
15  
16  
17  
VGH  
VGL  
fs  
vs Load current  
vs Load current  
vs Load current  
vs Input voltage  
DC output voltage  
Switching frequency  
IQ  
No load quiescent current  
Power-Up Sequencing (TPS65120)  
Power-Down Sequencing (TPS65120)  
9
TPS65120, TPS65121, TPS65123, TPS65124  
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SLVS531AJUNE 2004REVISED MARCH 2005  
TPS65124  
CORE CONVERTER EFFICIENCY  
vs  
TPS65124  
CORE CONVERTER EFFICIENCY  
vs  
LOAD CURRENT  
INPUT VOLTAGE  
100  
90  
100  
95  
90  
85  
80  
75  
70  
V
V
= 3.6 V,  
IN  
= 5 V,  
MAIN  
V
= 5 V  
MAIN  
ENVGL = ENVGH = GND  
80  
70  
60  
50  
40  
30  
20  
10  
0
I
= 15 mA  
BOOT  
I
= 5 mA  
BOOT  
65  
60  
V
IN  
= 3.6 V  
ENVGL = ENVGH = GND  
2.7  
3.1  
3.5  
3.9  
4.3  
4.7  
5.1  
5.5  
0.1  
1
10  
100  
V
IN  
− Input Voltage − V  
I
− Output Current − mA  
BOOT  
Figure 3.  
Figure 4.  
MAIN OUTPUT EFFICIENCY  
MAIN OUTPUT EFFICIENCY  
vs  
vs  
LOAD CURRENT  
INPUT VOLTAGE  
100  
90  
80  
70  
60  
50  
40  
30  
100  
95  
V
= 3.6 V  
IN  
V
V
V
= 5 V,  
= 15 V @ 200 mA,  
= −10 V @ 200 mA  
MAIN  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
40  
GH  
GL  
V
= 5 V @ 10 mA,  
= 15 V @ 200 mA,  
= −10 V @ 200 mA  
MAIN  
GH  
V
V
GL  
V
= 5 V @ 5 mA,  
MAIN  
V
= 15 V @ 200 mA,  
= −10 V @ 200 mA  
V
V
V
= 3.3 V,  
GH  
MAIN  
V
GL  
= 7.5 V @ 200 mA,  
= −3 V @ 200 mA  
GH  
GL  
V
= 3.3 V @ 10 mA,  
MAIN  
V
= 7.5 V @ 200 mA,  
GH  
V
GL  
= −3 V @ 200 mA  
0
2
4
6
8
10 12 14 16 18 20  
2.7  
3.1  
3.5  
3.9  
4.3  
4.7  
5.1  
5.5  
I
− Output Current − mA  
MAIN  
V
IN  
− Input Voltage − V  
Figure 5.  
Figure 6.  
10  
TPS65120, TPS65121, TPS65123, TPS65124  
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SLVS531AJUNE 2004REVISED MARCH 2005  
MAIN DC OUTPUT VOLTAGE  
vs  
MAIN OUTPUT RIPPLE VOLTAGE  
LOAD CURRENT  
5.05  
5.04  
5.03  
5.02  
5.01  
5
V
V
V
= 3.6 V,  
IN  
= 15 V @ 200 mA,  
= −10 V @ 200 mA  
GH  
GL  
V
BOOT  
(50 mV/div,  
5.8 V Offset)  
4.99  
4.98  
4.97  
4.96  
4.95  
V
MAIN  
(10 mV/div,  
5 V Offset)  
V
V
= 3.6 V,  
IN  
= 5 V @ 20 mA,  
MAIN  
ENVGL = ENVGH = LOW  
t − Time − 5 ms/div  
0
2
4
6
8
10 12 14 16 18 20  
I
− Output Current − mA  
MAIN  
Figure 7.  
Figure 8.  
MAIN OUTPUT LOAD  
TRANSIENT RESPONSE  
POSITIVE, NEGATIVE OUTPUT RIPPLE  
V
V
= 3.6 V,  
IN  
V
V
V
V
= 3.6 V,  
= 5 V @ 5 mA,  
IN  
MAIN  
= 5 V,  
MAIN  
ENVGL = ENVGH = LOW  
= 15 V @ 100 mA,  
= −10 V @ 100 mA  
GH  
GL  
V
MAIN  
(50 mV/div,  
5 V Offset)  
V
GH  
(50 mV/div,  
AC Coupled)  
V
GL  
(20 mV/div,  
AC Coupled)  
I
MAIN  
(10 mA/div)  
C
OUT  
= 220 nF  
t − Time − 20 ms/div  
t − Time − 10 ms/div  
Figure 9.  
Figure 10.  
11  
TPS65120, TPS65121, TPS65123, TPS65124  
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SLVS531AJUNE 2004REVISED MARCH 2005  
POSITIVE, NEGATIVE OUTPUT  
RIPPLE VOLTAGE  
POSITIVE OUTPUT (VGH) LOAD REGULATION  
15.15  
15.10  
15.05  
15  
V
V
V
V
= 3.6 V,  
IN  
MAIN  
V
V
V
= 3.6 V,  
IN  
MAIN  
= 5 V @ 5 mA,  
= 5 V, @ 5 mA  
= −10 V @ 200 mA  
GL  
= 15 V @ 100 mA,  
= −10 V @ 100 mA  
GH  
GL  
V
GH  
(20 mV/div,  
AC Coupled)  
10 pF Feed-Forward  
Capacitor Across R  
1
14.95  
14.90  
14.85  
V
GL  
(20 mV/div,  
AC Coupled)  
0.1  
1
10  
t − Time − 10 ms/div  
Figure 11.  
I
− Output Current − mA  
GH  
Figure 12.  
SWITCHING FREQUENCY  
vs  
NEGATIVE OUTPUT (VGL) LOAD REGULATION  
LOAD CURRENT  
10  
−9.90  
−9.92  
−9.94  
−9.96  
−9.98  
−10  
V
V
V
= 3.6 V,  
V
MAIN  
= 3.6 V,  
IN  
MAIN  
IN  
= 5 V @ 5 mA,  
= 15 V @ 200 mA  
V
= 5 V,  
ENVGH = ENVGL = GND  
GH  
−10.02  
−10.04  
−10.06  
−10.08  
−10.10  
1
0.1  
10  
1
0.1  
1
10  
100  
I
− Output Current − mA  
GL  
I
− Output Current − mA  
MAIN  
Figure 13.  
Figure 14.  
12  
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QUIESCENT CURRENT  
vs  
TPS65120  
POWER-UP SEQUENCING  
INPUT VOLTAGE  
300  
250  
200  
150  
100  
RUN  
V
LOGIC  
V
LOGIC  
(5 V/div)  
V
MAIN  
V
MAIN  
(2 V/div)  
V
GH  
V
GH  
(5 V/div)  
V
IN  
= 3.6 V, EN = HIGH,  
R
R
R
= 1 kW,  
= 120 kW,  
= 100 kW,  
MAIN  
GH  
GL  
V
V
= 3.3 V, V = 7.5 V, V = −3 V  
GL  
V
GL  
MAIN  
GH  
GL  
50  
0
(5 V/div)  
No-Load Quiescent Current Includes  
Output Voltage Divider Network Bias Current  
2.5 2.8  
3
3.3 3.5 3.8  
4
4.3 4.5 4.8 5 5.3 5.5  
t − Time − 100 ms/div  
V
IN  
− Input Voltage − V  
Figure 15.  
Figure 16.  
TPS65120  
POWER-DOWN SEQUENCING  
RUN  
V
LOGIC  
V
LOGIC  
(5 V/div)  
V
MAIN  
V
MAIN  
(2 V/div)  
V
GH  
(5 V/div)  
V
GH  
V
GL  
V
GL  
V
= 3.6 V, EN = HIGH,  
IN  
(5 V/div)  
R
R
R
= 1 kW,  
MAIN  
= 120 kW,  
= 100 kW,  
GH  
GL  
t − Time − 5 ms/div  
Figure 17.  
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DETAILED DESCRIPTION  
The standard application circuit ( Figure 1) of the TPS65120 is a complete power supply for TFT LCD displays.  
The circuit generates four independent supplies for the source driver (VMAIN), the gate drivers (VGH, VGL) and a  
logic supply for the timing controller. The input voltage range is from 2.5 V to 5.5 V.  
The TPS65120/1/2 contains a high-performance switching regulator and two low-dropout linear regulators  
(LDOs). One of the LDOs generates VMAIN and the other powers the logic inside the panel. The TPS65123  
includes only one linear regulator to provide the main output with low ripple voltage and can be set from 3.0 V to  
5.3 V with an external resistor voltage divider. The TPS65124 integrates programmable power sequencing for  
highest flexibility.  
OPERATION  
The TPS6512x generates both positive and negative supply voltages using a single inductor. It alternates  
between acting as a step-up converter and an inverting converter on a cycle-by-cycle basis. All output voltages  
are independently regulated.  
A free-running, variable-peak-current PWM control scheme is used to time-multiplex the inductor between BOOT,  
VGH, and VGL outputs. This inherently-stable control architecture operates at a pseudo fixed frequency, providing  
fast response to line and load transients while maintaining a relatively constant switching frequency and high  
efficiency over a wide range of input and output voltages.  
During the first cycle of operation, internal switches N-MOS1 and P-MOS1 are turned on. SWN connects to VIN,  
SWP pulls to ground and the inductor current rises. Once the inductor current reaches the DC current limit (ILIM  
)
of 150 mA (typ) the internal control logic can either turn off N-MOS1 or P-MOS1 to service the requesting output.  
Depending on the required output power, the converter starts another cycle or enters a pulse-skipping  
modulation scheme to increase efficiency under light loads. The current into the SWN pin measures the inductor  
current. The TPS6512x controls the inductor current to regulate BOOT, VGH, and VGL output voltages.  
To achieve low ripple voltage and high accuracy, the main output (VMAIN) is post-regulated by an integrated LDO.  
This LDO regulator regulates energy from the BOOT output down to 5.3 V (max). To achieve the highest  
efficiency, the BOOT voltage is regulated to minimize the dropout voltage across the LDO to approximately VMAIN  
+ 0.5 V.  
In addition, the VMAIN, VGH, VGL outputs are monitored for fault conditions that last longer than the fault-timer  
period of 100 µs (typ). The device goes into a latched shutdown state in case of a fault condition.  
Soft Start  
The TPS6512x has an internal soft-start circuit that limits the inrush current during startup. This prevents possible  
voltage drops of the input voltage in case the battery or a high impedance power source is connected to the input  
of the device.  
The device powers up by precharging the BOOT output capacitor to VIN. During the precharge phase, the  
current through the rectifying switch N-MOS2 is limited. This also limits the output current under short-circuit  
conditions on the BOOT output. To ensure proper startup of the device, the BOOT output must be left unloaded  
during the precharge phase.  
After the precharge phase, the converter operates with an ISTART-UP current limit of 65 mA (typ), then increases  
gradually to the full current limit of 150 mA (typ).  
Undervoltage Lockout  
To ensure that the input voltage is high enough for reliable operation, the TPS6512x includes an under-voltage  
lockout (UVLO) circuit. The UVLO threshold at the VIN pin is 2.15 V (typ) falling and 2.25 V (typ) rising. The 100  
mV (typ) hysteresis prevents supply transients from causing restarts.  
Once the input voltage exceeds the UVLO rising threshold, the controller can enable the reference voltage and  
precharges BOOT. When the input voltage falls below the UVLO falling threshold, the controller turns off the  
reference and all the regulator outputs, and pulls GATE high with an internal 100 kresistor to turn off P1 (  
Figure 18).  
14  
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DETAILED DESCRIPTION (continued)  
Enable and Power Sequencing (TPS65120/1/2/3)  
To correctly power up most TFT panels, the gate-drive supplies must be sequenced such that the negative  
supply (VGL) powers up before the positive supply (VGH). The TPS65120/1/2/3 controls this sequence through an  
enable pin.  
Once RUN is high, the TPS65120/1/2/3 turns on the external P-channel MOSFET P1 (see Figure 18) by pulling  
GATE low. GATE is pulled down with a 100 kresistor. The DC/DC converter then starts, enabling the BOOT  
output.  
Pulling the enable pin (EN) high enables the MAIN output. When the output voltage VMAIN has reached 90% of its  
nominal value, the negative output enables. VGH is delayed until the negative voltage has reached 90% of its  
nominal value.  
Pulling the RUN pin low shuts down the device. Power-down sequencing starts by switching off VGH and VGL  
.
The VGH output capacitor is actively discharged by an internal resistor while VGL is only discharged by its  
feedback voltage divider. The required time to discharge the output capacitor at VGL output depends on the load  
current. Once VFBL has reached 1.2 V (typ) the main output is turned off followed by the output voltage VLOGIC  
.
This sequence is shown in Figure 19.  
When no power sequencing is required on the digital supply voltage (VLOGIC), tie EN and RUN signals together  
and GATE can be connected to a logic-high level to disable the power-down sequencer. Each output turns off  
depending upon load current and output capacitance.  
P1  
V
IN  
V
= 3.3 V  
R9  
LOGIC  
RUN  
R10  
C7  
TPS65120  
SWN  
GATE, EN_LDOAUX  
D1  
V
= 3.3 V  
IN  
5.75V  
V
VIN  
GL  
R3  
R4  
C1  
L1  
V
RUN  
EN  
BOOT  
C3  
SWP  
FBL  
, EN  
V
GATE  
VGH  
LOGIC  
V
V
MAIN  
GH  
VMAIN  
FBM  
BOOT  
R5  
R6  
V
MAIN  
R1  
R2  
C5  
C2  
FBH  
V
C4  
GL  
LDOIN  
LDOOUT  
PGND  
AGND  
A
A
V
GH  
Figure 18. Power Sequencing on Digital Supply Voltage,  
VLOGIC  
Figure 19. TPS65120/1/2/3 Power Sequence  
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DETAILED DESCRIPTION (continued)  
Enable and Power Sequencing (TPS65124)  
The TPS65124 controls the power sequencing of VLOGIC, VMAIN, VGH and VGL with four separate enable pins.  
These pins must be terminated and not be left floating to prevent instability.  
Once RUN is pulled high and the input voltage on VIN exceeds the rising input UVLO threshold, the reference is  
turned on and the external P-channel MOSFET P1 (see Figure 20) is switched on by pulling GATE low. The  
GATE is pulled down with a 100 kresistor. The DC/DC converter then starts up, enabling the BOOT output.  
Pulling enable pin high (EN) powers on the MAIN output. This power sequencing must occur before the gate  
voltages are enabled. Conversely VGL and VGH output voltages must be turned off by pulling ENVGL and ENVGH  
inputs to ground before the MAIN output is switch off.  
To clamp the VGLoutput near zero when the MAIN output is still on, an external diode (D2) can be used. In some  
applications this diode may already be implemented in the display.  
P1  
VLOGIC = 3.3V  
V
IN  
D2  
RUN  
TPS65124  
optional  
VGL  
D1  
VIN = 3.3V  
VIN  
SWN  
R3  
R4  
GATE  
C1  
L1  
5.75V  
RUN  
C3  
GATE  
SWP  
FBL  
V
EN  
EN  
BOOT  
VGH  
VMAIN  
VGH  
VMAIN  
FBM  
R5  
R6  
R1  
R2  
V
LOGIC  
C2  
C5  
FBH  
BOOT  
C4  
EN  
V
MAIN  
ENVGH  
ENVGL  
ENVGH  
ENVGL  
AGND  
PGND  
ENVGH  
A
A
V
GH  
ENVGL  
V
GL  
Figure 20. Power Sequencing on Digital Supply Voltage,  
VLOGIC  
Figure 21. TPS65124 Programmable Power Sequence  
Fault Protection  
All TPS6512x outputs are protected against a short circuit to ground. During steady-state operation, if the output  
VMAIN, VGH or VGL falls below its fault detection threshold the device simultaneously turns off all three outputs.  
Once VMAIN comes down to 700 mV typ, the GATE output is pulled to VIN, the auxiliary LDO (TPS65120/1/2) is  
disabled and the device enters a shutdown state.  
The auxiliary LDO present in TPS65120/1/2 has an integrated current foldback circuit for reliable short-circuit  
protection.  
The device can be enabled again by toggling the enable pins (RUN, EN) below 0.4 V or by cycling the input  
voltage below the UVLO falling threshold (2.15 V typ).  
16  
 
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APPLICATION INFORMATION  
OUTPUT POWER CAPABILITY  
The first step in the design procedure is to calculate the maximum output current for each output under certain  
input and output voltage conditions. The TPS6512x uses time-multiplex operation to share the inductive storage  
element between BOOT, VGH and VGL outputs. To avoid complex calculations it is recommended to use the  
specified output-power data from the electrical characteristics table to determine the maximum output-power  
capability.  
The following example shows how to proceed for given requirements:  
Input Voltage = 3.0 V  
MAIN Output = 5.0 V @ 10 mA  
VGH output = 12 V @ 500 µA  
VGL output = -12 V @ 300 µA  
1. Calculate Maximum Output Power on VGH Output  
PGH = VGH ×IGH  
2. Calculate Maximum Output Power on VGL Output  
PGL = VGL ×IGL  
3. Calculate Maximum Output Power on BOOT Output  
2
VMAIN  
PBOOT = PMAIN × ηLDO _ MAIN  
×IMAIN for V < VMAIN + 0.5  
IN  
VMAIN + 0.5  
2
VMAIN  
PBOOT = PMAIN × ηLDO _ MAIN  
×IMAIN for V > VMAIN  
IN  
V
IN  
4. Maximum Output Power Verification  
The electrical characteristics table states that for VIN > 3.0 V, the maximum power on VGH and VGL outputs  
must be lower than 35 mW each. Furthermore, the total output power (PBOOT + PGH + PGL) must be lower than  
150 mW.  
In our design example, PGH = 6 mW, PGL = 3.6 mW, and PBOOT = 55 mW. Since these numbers are well below  
the specified values, we can conclude that TPS6512x can reasonably power such a display.  
SETTING THE OUTPUT VOLTAGE  
The output voltages are defined as shown in Figure 22.  
R5 + R6  
V
MAIN = VFBM ×  
R6  
with an internal reference voltage VFBM typical = 1.213V.  
R1+ R2  
V
GH = VFBH ×  
R2  
with an internal reference voltage VFBH typical = 1.213V.  
R3  
VGL = VMAIN  
×
R4  
To minimize the operating quiescent current, set R2, R4 and R6 in the range 100 kto 300 k. Great care  
should be taken to route the FBx lines away from noise sources such as the inductor or the SWN and SWP lines.  
A feed-forward capacitor across the upper feedback resistor (R1, R3) on VGH and VGL outputs can be used to  
provide more overdrive for the error comparator. This feed-forward capacitor helps to reduce the output ripple  
voltage. A good starting value is 10 pF.  
17  
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APPLICATION INFORMATION (continued)  
The larger the feed-forward capacitor the worse the load regulation of the device. Therefore, when concern for  
load regulation is paramount, select a capacitor value as small as possible. Another possibility to further reduce  
ripple voltage on VGH and VGL outputs is to increase output-capacitor values (C2, C3).  
V
IN  
TPS65120  
D1  
2.7 V to 5.5 V  
V
VIN  
GL  
SWN  
down to −18 V/2 mA  
C1  
2.2 µF  
R3  
R4  
L1  
10  
RUN  
EN  
C3  
100 nF  
µH  
SWP  
FBL  
V
GH  
GATE  
VGH  
up to 20 V/2 mA  
V
MAIN  
VMAIN  
FBM  
3.0 V to 5.3 V/25 mA  
R5  
R6  
R1  
R2  
BOOT  
C2  
100 nF  
C4  
C5  
220 nF  
FBH  
1µF  
LDOIN  
V
LDOOUT  
PGND  
AUX  
3.3 V/20 mA  
C6  
220 nF  
AGND  
A
A
Figure 22. Typical Application  
INDUCTOR SELECTION  
Since the control scheme of the TPS6512x device is inherently stable, the inductor value does not affect the  
stability of the converter. To operate the TPS6512x properly at full performance, choose inductors in the range  
8.2 µH to 10 µH.  
The selection of the inductor is primarily based on the required output power. The variable peak current PWM  
control scheme used in TPS6512x automatically adapts the peak inductor current (between 65mA typ. and  
150mA typ.) depending on output power and input voltage.  
At moderate loads, the converter typically operates with a peak inductor current in the range of 65mA to 100mA,  
allowing the use of inductors in the 0603 case size. In order not to saturate the inductor when operating at a  
higher output power, select an inductor with a higher saturation-current rating.  
The inductor series in Table 1 from various suppliers have been used with the TPS6512x converter.  
Table 1. List of Inductors  
MANUFACTURER  
SERIES  
DIMENSIONS  
LQ LB1608 1.6 x 0.8 x 0.8 = 1.02 mm3  
LQ CB2012 2.0 x 1.2 x 1.2 = 2.88 mm3  
LQ CBL2012 2.0 x 1.2 x 1.0 = 2.40 mm3  
TAIYO YUDEN  
GLF1608  
GLF2012  
1.6 x 0.8 x 0.8 = 1.02 mm3  
2.0 x 1.2 x 1.2 = 2.88 mm3  
TDK  
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DIODE SELECTION  
To achieve high efficiency, use a Schottky diode. The voltage rating must be higher than the input voltage plus  
the absolute value of the negative output. The current rating of the diode must meet the converter peak  
inductor-current rating when servicing the VGL output. The main parameter affecting the efficiency of the  
converter is the forward voltage and the reverse leakage current of the diode, both should be as low as possible.  
The following diodes from different suppliers listed in Table 2 have been used with the TPS6512x converter.  
Table 2. List of Diodes  
MANUFACTURER  
ROHM  
REFERENCE  
RB521G-30  
BAT54-HT3  
ZUMD54  
REVERSE VOLTAGE  
30 V  
30 V  
30 V  
VISHAY  
ZETEX  
CAPACITOR SELECTION  
The TPS65120 converter requires six capacitors. The input capacitor is primarily a function of the board layout.  
In designs with long traces, for good input filtering, we recommend a ceramic input capacitor (X5R/X7R type) of  
at least 1 µF placed as close as possible to the converter.  
To operate properly, the TPS6512x requires a bootstrap capacitor of 1 µF (or larger) on the BOOT output.  
Additionally the minimum BOOT capacitance must be larger than two times the capacitor value connected to the  
MAIN and AUXILIARY LDO outputs (in case LDO AUX is connected to the BOOT output).  
The TPS6512x peak-current control scheme is inherently stable. The filtering capacitors on VGH and VGL  
outputs are basically determined as a function of the required current and permissible ripple voltage. For small  
form-factor TFT-LCD applications, typical values in the range of 100 nF to 1 µF are usually required. A good  
starting point is 220 nF. For high output power on VGH and VGL outputs, the capacitance may need to approach  
2 µF.  
For stable operation, TPS6512x requires a 220-nF ceramic capacitor on the MAIN and AUXILIARY LDO outputs.  
Larger capacitor values can be used to achieve lower output-voltage noise without sacrificing stability.  
In general, ceramic X5R types are strongly recommended for their low ESR and ESL and capaci-  
tance-versus-bias-voltage stability. Be certain that the capacitors used are rated for the maximum voltage with  
adequate safety margin.  
LAYOUT CONSIDERATIONS  
As for all switching power supplies, the layout is an important step in the design. If the layout is not carefully  
done, the regulator could become unstable, displaying double or missing pulses as well as EMI problems.  
Therefore, use wide, short traces for the main current paths. Route these traces first.  
Place the input capacitor as close as possible to the IC pins as well as the inductor and output capacitors. Place  
the inductor and diode as close as possible to the switch pins to minimize noise coupling into other circuits.  
Use a common ground node for power ground and a different one for control ground (AGND) to minimize the  
effects of ground noise. Connect these ground nodes together (star point) at any place close to one of the  
ground pins of the IC and make sure that small-signal components returning to the AGND pin do not share the  
switching-current paths.  
Feedback pins and divider networks are high-impedance nodes and should therefore be routed away from the  
inductor and shielded with a ground plane or trace to minimize noise coupling into the control loop.  
19  
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APPLICATION EXAMPLES  
TPS65120  
D1  
VGL  
VIN  
SWN  
VIN  
down to −18 V/2 mA  
R3  
R4  
C1  
2.2  
2.7 V to 5.5 V  
L1  
10  
F
µ
RUN  
EN  
C3  
220 nF  
H
µ
GPIO  
SWP  
FBL  
GATE  
VGH  
VGH  
up to +20 V/2 mA  
VMAIN  
3.0 V to 5.3 V/25 mA  
VMAIN  
FBM  
R5  
R1  
R2  
C2  
220 nF  
BOOT  
C5  
FBH  
C4 R6  
220 nF  
1
µF  
LDOIN  
LDOOUT  
PGND  
VLOGIC = 3.3 V  
C6  
220 nF  
AGND  
A
A
Figure 23. Complete TFT-LCD Power Supply from 1 cell Li-Ion  
TPS65123  
D1  
VGL  
VIN  
SWN  
VIN  
C1  
2.7 V to 5.5 V  
L1  
RUN  
EN  
R3  
C3  
220 nF  
RUN  
VGH  
SWP  
FBL  
GATE  
VGH  
RUN  
R4b  
R4a  
N−MOS  
R1  
R2  
C2  
220 nF  
VISHAY SI1032  
FBH  
VMAIN  
VMAIN  
FBM  
R5  
R6  
BOOT  
PGND  
C5  
220 nF  
C4  
1µF  
AGND  
A
A
R3  
1.2 VMAIN  
VGL _ OFFThreshold 1.2  
V
= 5.0 V, V = 15 V, V = −10 V  
GH GL  
MAIN  
VGL = VMAIN  
×
R4b = R3  
R4a  
R = 540 k, R = 270 k, R = 680 kΩ  
3
4a  
4b  
R4a  
Figure 24. VGLVMAIN Power Down-Sequencing Threshold Shifting  
EN  
Negative  
VGL2  
LDO  
C7  
TPS65121  
D1  
VIN  
VGL1  
VIN  
SWN  
R3  
R4  
C1  
L1  
>
RUN  
EN  
C3 C7  
GPIO  
VGH  
SWP  
FBL  
GATE  
VGH  
VMAIN  
VMAIN  
FBM  
R5  
R6  
R1  
R2  
C2  
220 nF  
BOOT  
C5  
220 nF  
FBH  
C4  
1
µF  
LDOIN  
LDOOUT  
PGND  
VLOGIC  
C6  
220 nF  
AGND  
A
A
Negative LDO = TPS723xx series  
Figure 25. Additonal Negative Gate Driver Voltage  
20  
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TPS65124  
D1  
VGL  
VIN  
VIN  
SWN  
C7  
C1  
2.2 µF  
R3  
R4  
L1  
RUN  
GATE  
C3  
220 nF  
10 pF  
SWP  
FBL  
GPIO1  
EN  
VGH  
VGH  
C6  
R1  
R2  
C2  
10 pF  
220 nF  
FBH  
VMAIN  
VMAIN  
FBM  
R5  
R6  
N&P MOS  
BOOT  
C5  
C8  
C4  
GPIO2  
GPIO3  
ENVGH  
ENVGL  
2.2  
100 nF  
µF  
4.7 µF  
PGND  
AGND  
GPIO4  
A
A
N&P MOS = VISHAY Si1016  
D1 = VISHAY BAT54A−HT3  
Figure 26. Fully Programmable Sequencing Featuring Very Low Gate Ripple Voltage  
TPS65124  
D1  
ENVGH,  
ENVGL  
(2V/div)  
VNEG  
VIN  
VIN  
SWN  
−12 V  
C1  
R3  
R4  
L1  
RUN  
GATE  
C3  
220 nF  
SWP  
FBL  
V
GH  
V
GH  
EN  
(5V/div)  
VPOS  
12 V  
VGH  
VPOS  
R1  
R2  
C2  
220 nF  
FBH  
VREF  
VMAIN  
FBM  
V
GL  
R5  
R6  
V
= 3.6V  
(5V/div)  
IN  
EN = RUN = HIGH  
BOOT  
C5  
220 nF  
C4  
EN  
ENVGH  
ENVGL  
F
µ
R
GH  
R
GL  
= 60 k  
= 60 kΩ  
1
V
GL  
PGND  
AGND  
R1 = 887 k  
R2 = 100 kΩ  
A
A
R3 = R4 = 680 kΩ  
R5 = 845 kΩ  
R6 = 270 kΩ  
Figure 27. Dual Output Tracking Regulator with High Accuracy Reference Voltage  
TPS65123  
D1  
VGL  
VIN  
VIN  
SWN  
C1  
L1  
RUN  
EN  
R3  
C3  
SWP  
FBL  
RUN  
VGH  
GATE  
VGH  
EN TPS65120  
LDO  
EN  
IN  
OUT  
BOOT  
R4  
R1  
R2  
C4  
2.2  
C2  
FBH  
µ
F
VMAIN  
VMAIN  
FBM  
R5  
R6  
C5  
1uF  
PGND  
AGND  
A
A
External LDO = TPS792xx series  
Ext. LDO nominal output voltage setting recommended at 1% lower than VMAIN.  
Figure 28. Boosting Main Output Current, IMAIN > 25mA  
21  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
PACKAGING INFORMATION  
Orderable Device  
TPS65120RGTR  
TPS65120RGTRG4  
TPS65120RGTT  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
Top-Side Markings  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4)  
ACTIVE  
QFN  
QFN  
QFN  
QFN  
QFN  
QFN  
RGT  
16  
16  
16  
16  
16  
16  
3000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
BKA  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
RGT  
RGT  
RGT  
RGT  
RGT  
3000  
250  
Green (RoHS  
& no Sb/Br)  
BKA  
BKA  
BKA  
BKB  
BKB  
BKB  
Green (RoHS  
& no Sb/Br)  
TPS65120RGTTG4  
TPS65121RGTR  
TPS65121RGTRG4  
250  
Green (RoHS  
& no Sb/Br)  
3000  
3000  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
TPS65121RGTT  
TPS65121RGTTG4  
TPS65123RGTR  
OBSOLETE  
OBSOLETE  
ACTIVE  
QFN  
QFN  
QFN  
RGT  
RGT  
RGT  
16  
16  
16  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
-40 to 85  
-40 to 85  
-40 to 85  
3000  
3000  
250  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
Level-2-260C-1 YEAR  
BKC  
BKC  
BKC  
BKC  
BKD  
BKD  
BKD  
BKD  
TPS65123RGTRG4  
TPS65123RGTT  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
QFN  
QFN  
QFN  
QFN  
QFN  
QFN  
QFN  
RGT  
RGT  
RGT  
RGT  
RGT  
RGT  
RGT  
16  
16  
16  
16  
16  
16  
16  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
Green (RoHS  
& no Sb/Br)  
TPS65123RGTTG4  
TPS65124RGTR  
TPS65124RGTRG4  
TPS65124RGTT  
250  
Green (RoHS  
& no Sb/Br)  
3000  
3000  
250  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
TPS65124RGTTG4  
250  
Green (RoHS  
& no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4)  
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a  
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
8-Apr-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPS65120RGTR  
TPS65120RGTT  
TPS65121RGTR  
TPS65123RGTR  
TPS65123RGTT  
TPS65124RGTR  
TPS65124RGTT  
QFN  
QFN  
QFN  
QFN  
QFN  
QFN  
QFN  
RGT  
RGT  
RGT  
RGT  
RGT  
RGT  
RGT  
16  
16  
16  
16  
16  
16  
16  
3000  
250  
330.0  
180.0  
330.0  
330.0  
180.0  
330.0  
180.0  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
3.3  
3.3  
3.3  
3.3  
3.3  
3.3  
3.3  
3.3  
3.3  
3.3  
3.3  
3.3  
3.3  
3.3  
1.1  
1.1  
1.1  
1.1  
1.1  
1.1  
1.1  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
3000  
3000  
250  
3000  
250  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
8-Apr-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TPS65120RGTR  
TPS65120RGTT  
TPS65121RGTR  
TPS65123RGTR  
TPS65123RGTT  
TPS65124RGTR  
TPS65124RGTT  
QFN  
QFN  
QFN  
QFN  
QFN  
QFN  
QFN  
RGT  
RGT  
RGT  
RGT  
RGT  
RGT  
RGT  
16  
16  
16  
16  
16  
16  
16  
3000  
250  
338.1  
210.0  
338.1  
338.1  
210.0  
338.1  
210.0  
338.1  
185.0  
338.1  
338.1  
185.0  
338.1  
185.0  
20.6  
35.0  
20.6  
20.6  
35.0  
20.6  
35.0  
3000  
3000  
250  
3000  
250  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
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Copyright © 2013, Texas Instruments Incorporated  
配单直通车
TPS65123RGTR产品参数
型号:TPS65123RGTR
Brand Name:Texas Instruments
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
IHS 制造商:TEXAS INSTRUMENTS INC
零件包装代码:QFN
包装说明:HVQCCN, LCC16,.12SQ,20
针数:16
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
Factory Lead Time:1 week
风险等级:0.86
其他特性:ALSO OPERATES IN ADJUSTABLE MODE FROM 3V TO 5.6V
模拟集成电路 - 其他类型:SWITCHING REGULATOR
控制模式:CURRENT-MODE
控制技术:PULSE WIDTH MODULATION
最大输入电压:5.5 V
最小输入电压:2.7 V
标称输入电压:3.6 V
JESD-30 代码:S-PQCC-N16
JESD-609代码:e4
长度:3 mm
湿度敏感等级:2
最大负输入电压:-1.5 V
功能数量:1
端子数量:16
最高工作温度:85 °C
最低工作温度:-40 °C
最大输出电流:0.2 A
封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN
封装等效代码:LCC16,.12SQ,20
封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260
电源:3.6 V
认证状态:Not Qualified
座面最大高度:0.9 mm
子类别:Power Management Circuits
最大供电电流 (Isup):0.17 mA
标称供电电压 (Vsup):3.6 V
表面贴装:YES
切换器配置:SINGLE
最大切换频率:4000 kHz
技术:CMOS
温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD
端子节距:0.5 mm
端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3 mm
Base Number Matches:1
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