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产品型号TPS73601MDBVREP的概述

芯片TPS73601MDBVREP概述 TPS73601MDBVREP是一款高精度的低压差（LDO）线性稳压器，设计用于提供稳定的输出电压，广泛应用于电源管理系统中。该芯片具有高输入电压范围、低电源噪声以及低静态功耗等优良特性。TPS736系列芯片由德州仪器（Texas Instruments, TI）生产，其设计目标是提供必要的电源管理解决方案，以满足现代电子设备对电源质量的严格要求。该芯片通常用于微控制器、数模转换器（DAC）、射频（RF）电源和各种其他数字和模拟电路中。详细参数 TPS73601MDBVREP的主要技术参数如下： 1. 输出电压：该芯片提供固定的输出电压（通常为3.3V或5V）和可调式输出电压版本。输出电压的精度通常在±2%以内。 2. 输入电压范围：该芯片的输入电压范围为1.8V至5.5V，支持多种电源输入选项，能够满足不同应用的需求。 3. 最大...

产品型号TPS73601MDBVREP的Datasheet PDF文件预览

TPS73601-EP, TPS73615-EP, TPS73618-EP

TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP

www.ti.com .................................................................................................................................................. SGLS326C–APRIL 2006–REVISED FEBRUARY 2009

CAP-FREE NMOS 400 mA LOW-DROPOUT REGULATORS

WITH REVERSE CURRENT PROTECTION

FEATURES

–

Adjustable Output from 1.2 V to 5.5 V

Custom Outputs Available

•

Controlled Baseline

–

One Assembly

APPLICATIONS

One Test Site

•

Portable/Battery-Powered Equipment

Post-Regulation for Switching Supplies

Noise-Sensitive Circuitry Such as VCOs

Point of Load Regulation for DSPs, FPGAs,

ASICs, and Microprocessors

One Fabrication Site

•

Extended Temperature Performance of

–55°C to 125°C

Enhanced Diminishing Manufacturing Sources

(DMS) Support

•

Enhanced Product-Change Notification

Optional

(1)

Qualification Pedigree

V_IN

V_OUT

OUT

TPS736xx

GND

Stable With No Output Capacitor or Any Value

or Type of Capacitor

•

Input Voltage Range of 1.7 V to 5.5 V

Ultra-Low Dropout Voltage: 75 mV Typical

Excellent Load Transient Response—With or

Without Optional Output Capacitor

Optional

Typical Application Circuit for Fixed-Voltage Versions

•

New NMOS Topology Delivers Low Reverse

Leakage Current

Low Noise: 30 µV_RMSTypical

(10 Hz to 100 kHz)

•

0.5% Initial Accuracy

1% Overall Accuracy Over Line, Load, and

Temperature

•

Less Than 1-µA Max I_Qin Shutdown Mode

Thermal Shutdown and Specified Min/Max

Current Limit Protection

•

Available in Multiple Output Voltage Versions

–

Fixed Outputs of 1.2 V to 3.3 V

(1) Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

temperature cycle, autoclave or unbiased HAST,

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

justifying use of this component beyond specified

performance and environmental limits.

N/C - No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS73601-EP, TPS73615-EP, TPS73618-EP

TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP

SGLS326C–APRIL 2006–REVISED FEBRUARY 2009.................................................................................................................................................. www.ti.com

DESCRIPTION

The TPS736xx family of low-dropout (LDO) linear voltage regulators uses a new topology—an NMOS pass

element in a voltage-follower configuration. This topology is stable using output capacitors with low ESR and

allows operation without a capacitor. It also provides high reverse blockage (low reverse current) and ground-pin

current that is nearly constant over all values of output current.

The TPS736xx uses an advanced BiCMOS process to yield high precision while delivering low dropout voltages

and low ground-pin current. Current consumption, when not enabled, is under 1 µA and ideal for portable

applications. The low output noise (30 µV_RMSwith 0.1-µF C_NR) is ideal for powering VCOs. These devices are

protected by thermal shutdown and foldback current limit.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PRODUCT INFORMATION

(1)

PRODUCT

V_OUT

xx is normal output voltage (for example, 25 = 2.5 V, 01 = Adjustable⁽²⁾).

yyy is package designator.

TPS736xxMyyyREP

z is package quantity.

(1) Additional output voltages from 1.25 V to 4.3 V in 100 mV increments are available on a quick-turn basis using innovative factory

EEPROM programming. Minimum order quantities apply; contact TI for details and availability.

(2) For fixed 1.2-V operation, tie FB to OUT.

ORDERING INFORMATION⁽¹⁾

T_A

PACKAGE⁽²⁾

ORDERABLE PART NUMBER

TPS73601MDBVREP

TPS73615MDBVREP

TPS73618MDBVREP

TPS73625MDBVREP

TPS73630MDBVREP

TPS73632MDBVREP

TPS73633MDBVREP

TPS73601MDCQREP

TPS73601MDRBREP

TOP-SIDE MARKING

PJRM

T59

T60

SOT23 - DBV

T61

–55°C to 125°C

T62

T63

T64

SOT223 - DCQ

SON - DRB

PWZM

PMNM

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

TERMINAL FUNCTIONS

SOT23

(DBV)

SOT223

(DCQ)

3x3 SON

(DRB)

NAME

DESCRIPTION

PIN NO.

GND

3, 6

4, Pad

Unregulated input supply

Ground

Enable. Driving EN high turns on the regulator. Driving this pin low puts the regulator into

shutdown mode. See the Shutdown section under Applications Information for more details.

EN can be connected to IN if not used.

Fixed-voltage versions only. Connecting an external capacitor to this pin bypasses noise

generated by the internal bandgap, reducing output noise to low levels.

Feedback. Adjustable-voltage version only. This is the input to the control loop error

amplifier and is used to set the output voltage of the device.

OUT

Output of the regulator. There are no output capacitor requirements for stability.

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Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

TPS73633-EP

TPS73601-EP, TPS73615-EP, TPS73618-EP

TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP

100

110

120

130

Continuous T − 5C

140

150

160

A. T_J= T_JA× W + T_A(Standard. JESD 51 conditions)

Figure 1. TPS736xxDBVzEP Estimated Device Life at Elevated Temperatures Electromigration Fail Mode

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Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

TPS73633-EP

TPS73601-EP, TPS73615-EP, TPS73618-EP

TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted⁽¹⁾

UNIT

V_INrange

–0.3 to 6

V_ENrange

–0.3 to 6

V_OUTrange

–0.3 to 5.5

Peak output current

Output short-circuit duration

Continuous total power dissipation

Junction temperature range, T_J

Storage temperature range

Internally limited

Indefinite

See Dissipation Ratings Table

–55 to 150

–65 to 150

°C

Human-Body Model - HBM

ESD rating

Charged-Device Model - CDM

500

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics

is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

POWER DISSIPATION RATINGS⁽¹⁾

DERATING FACTOR

ABOVE T_A= 25°C

_A≤ 25°C

T_A= 70°C

T_A= 85°C

BOARD

PACKAGE

R_θJC

R_θJA

POWER RATING POWER RATING POWER RATING

Low-K⁽²⁾

High-K⁽³⁾

Low-K⁽²⁾

High-K⁽³⁾

High-K⁽³⁾⁽⁴⁾

DBV

DCQ

DRB

64°C/W

15°C/W

1.2°C/W

255°C/W

180°C/W

53°C/W

45°C/W

40°C/W

3.9 mW/°C

5.6 mW/°C

18.9 mW/°C

22.2 mW/°C

25.0 mW/°C

392 mW

556 mW

216 mW

306 mW

157 mW

222 mW

755 mW

889 mW

1000 mW

1887 mW

2222 mW

2500 mW

1038 mW

1222 mW

1375 mW

(1) See the Thermal Protection section for more information related to thermal design.

(2) The JEDEC Low-K (1s) board design used to derive this data was a 3 in × 3 in, two-layer board with 2 oz copper traces on top of the

board.

(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3 in × 3 in, multilayer board with 1 oz internal power and ground

planes, and 2-oz copper traces on the top and bottom of the board.

(4) Based on preliminary thermal simulations.

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Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

TPS73633-EP

TPS73601-EP, TPS73615-EP, TPS73618-EP

TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP

ELECTRICAL CHARACTERISTICS

over operating temperature range (T_A= –55°C to 125°C), V_IN= V_OUT(nom)+ 0.5 V⁽¹⁾, I_OUT= 10 mA, V_EN= 1.7 V, and

C_OUT= 0.1 µF (unless otherwise noted). Typical values are at T_J= 25°C.

PARAMETER

Input voltage range^{(1) (2)}

TEST CONDITIONS

MIN

1.7

TYP

MAX

5.5

UNIT

V_IN

V_FB

Internal reference (TPS73601)

T_J= 25°C

1.198

1.2

1.21

Output voltage range

(TPS73601)

5.5 –

V_DO

V_FB

–0.5%

–1%

V_OUT

Nominal

T_J= 25°C

0.5%

Accuracy⁽¹⁾

Over V_IN, I_OUT

and T

V_OUT+ 0.5 V ≤ V_IN≤ 5.5 V,

10 mA ≤ I_OUT≤ 400 mA

±0.5%

ΔV_OUT%/ΔV_INLine regulation⁽¹⁾

V_O(nom)+ 0.5 V ≤ V_IN≤ 5.5 V

1 mA ≤ I_OUT≤ 400 mA

0.01

0.002

%/V

ΔV_OUT%/ΔI_OUTLoad regulation

%/mA

10 mA ≤ I_OUT≤ 400 mA

0.0005

Dropout voltage⁽³⁾

V_DO

I_OUT= 400 mA

200

800

(V_IN= V_OUT(nom)– 0.1 V)

Z_O(DO)

I_CL

Output impedance in dropout

Output current limit

1.7 V ≤ V_IN≤ V_OUT+ V_DO

V_OUT= 0.9 × V_OUT(nom)

V_OUT= 0 V

0.25

650

Ω

400

µA

I_SC

Short-circuit current

450

I_REV

Reverse leakage current⁽⁴⁾(–I_IN

)

V_EN≤ 0.5 V, 0 V ≤ V_IN≤ V_OUT

0.1

550

1000

I_OUT= 10 mA (I_Q)

I_OUT= 400 mA

400

I_GND

Ground-pin current

µA

800

I_SHDN

I_FB

Shutdown current (I_GND

)

V_EN≤ 0.5 V, V_OUT≤ V_IN≤ 5.5 V

0.02

µA

FB pin current (TPS73601)

0.1

0.45

f = 100 Hz, I_OUT= 400 mA

f = 10 kHz, I_OUT= 400 mA

C_OUT= 10 µF, No C_NR

Power-supply rejection ratio

(ripple rejection)

PSRR

27 × V_OUT

8.5 × V_OUT

Output noise voltage

BW = 10 Hz to 100 kHz

V_N

µV_RMS

µs

C_OUT= 10 µF, C_NR= 0.01 µF

V_OUT= 3 V, R_L= 30 Ω, C_OUT= 1 µF,

C_NR= 0.01 µF

t_STR

Startup time

600

V_EN(HI)

V_EN(LO)

I_EN(HI)

Enable high (enabled)

1.7

V_IN

0.5

0.1

Enable low (shutdown)

Enable pin current (enabled)

V_EN= 5.5 V

0.02

160

140

µA

Shutdown, temperature increasing

Reset, temperature decreasing

T_SD

T_A

Thermal shutdown temperature

Operating ambient temperature

°C

-55

125

(1) Minimum V_IN= V_OUT+ V_DOor 1.7 V, whichever is greater.

(2) For V_OUT(nom)< 1.6 V, when V_IN≤ 1.6 V, the output locks to V_INand may result in a damaging over-voltage level on the output. To avoid

this situation, disable the device before powering down the V_IN

(3) V_DOis not measured for the TPS73615 (V_OUT(nom)= 1.5 V) since minimum V_IN= 1.7 V.

(4) See the Applications section for more information.

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Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

TPS73633-EP

TPS73601-EP, TPS73615-EP, TPS73618-EP

TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP

FUNCTIONAL BLOCK DIAGRAMS

4-MHz

Charge Pump

Thermal

Protection

Ref

Servo

27 kW

Bandgap

Error

Amp

Current

OUT

Limit

8 kW

GND

R + R = 80 kW

Figure 2. Fixed-Voltage Version

Standard 1% Resistor

Values for Common

Output Voltages

4-MHz

Charge Pump

1.2 V

1.5 V

1.8 V

2.5 V

2.8 V

3 V

Short

Open

23.2 kΩ

28 kΩ

95.3 kΩ

56.2 kΩ

36.5 kΩ

33.2 kΩ

30.9 kΩ

30.1 kΩ

Thermal

Protection

39.2 kΩ

44.2 kΩ

46.4 kΩ

52.3 kΩ

Ref

Servo

27 kW

Bandgap

Error

Amp

3.3 V

NOTE: V

= (R + R )/R × 1.204;

1 2 2

OUT

Current

Limit

19 kΩ for best

accuracy

GND

80 kW

8 kW

Figure 3. Adjustable-Voltage Version

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Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

TPS73633-EP

TPS73601-EP, TPS73615-EP, TPS73618-EP

TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP

TYPICAL CHARACTERISTICS

For all voltage versions, T_J= 25°C, V_IN= V_OUT(nom)+ 0.5 V, I_OUT= 10 mA, V_EN= 1.7 V, and C_OUT= 0.1 µF

(unless otherwise noted)

LOAD REGULATION

Referred to I_OUT= 10 mA

LINE REGULATION

0.20

0.15

0.10

0.05

0.5

0.4

0.3

0.2

0.1

Referred to V = V

+ 0.5 V at I

= 10 mA

OUT

−40°C

25°C

125°C

25°C

125°C

−

0.1

0.2

0.3

0.4

0.5

−

0.05

0.10

0.15

0.20

−40°C

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

100

150

200

250

300

350 400

−

V_INV_OUT(V)

I_OUT(mA)

Figure 4.

Figure 5.

DROPOUT VOLTAGE vs OUTPUT CURRENT

DROPOUT VOLTAGE vs TEMPERATURE

100

TPS73625DBV

= 400 mA

125°C

OUT

25°C

−40°C

−

100

150

200

250

300

350

400

100

125

Temperature (°C)

I_OUT(mA)

Figure 6.

OUTPUT VOLTAGE ACCURACY HISTOGRAM

Figure 7.

OUTPUT VOLTAGE DRIFT HISTOGRAM

= 10 mA

OUT

= 10 mA

OUT

All Voltage Versions

Worst Case dV

/dT (ppm/°C)

V_OUTError (%)

OUT

Figure 8.

Figure 9.

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Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

TPS73633-EP

TPS73601-EP, TPS73615-EP, TPS73618-EP

TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP

TYPICAL CHARACTERISTICS (continued)

For all voltage versions, T_J= 25°C, V_IN= V_OUT(nom)+ 0.5 V, I_OUT= 10 mA, V_EN= 1.7 V, and C_OUT= 0.1 µF

(unless otherwise noted)

GROUND-PIN CURRENT vs OUTPUT CURRENT

GROUND PIN CURRENT vs TEMPERATURE

1000

900

800

700

600

500

400

300

200

100

1000

900

800

700

600

500

400

300

200

100

= 400 mA

OUT

= 5.5 V

= 3 V

= 2 V

= 5.5 V

= 4 V

= 2 V

100

200

300

400

−

100

125

Temperature (°C)

I_OUT(mA)

Figure 10.

Figure 11.

CURRENT LIMIT vs V_OUT

(FOLDBACK)

GROUND PIN CURRENT in SHUTDOWN

vs TEMPERATURE

800

700

600

500

400

300

200

100

= 0.5 V

= V + 0.5 V

ENABLE

I_CL

I_SC

0.1

TPS73633

0.5

0.01

−

100

125

1.0

1.5

2.0

2.5

3.0

3.5

Temperature (°C)

V_OUT(V)

Figure 12.

CURRENT LIMIT vs V_IN

Figure 13.

CURRENT LIMIT vs TEMPERATURE

800

750

700

650

600

550

500

450

400

800

750

700

650

600

550

500

450

400

−

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

100

125

Temperature (°C)

V_IN(V)

Figure 14.

Figure 15.

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Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

TPS73633-EP

TPS73601-EP, TPS73615-EP, TPS73618-EP

TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP

TYPICAL CHARACTERISTICS (continued)

For all voltage versions, T_J= 25°C, V_IN= V_OUT(nom)+ 0.5 V, I_OUT= 10 mA, V_EN= 1.7 V, and C_OUT= 0.1 µF

(unless otherwise noted)

PSRR (RIPPLE REJECTION) vs FREQUENCY

PSRR (RIPPLE REJECTION) vs V_IN– V_OUT

= 100 mA

= Any

= 1 mA

OUT

= 1 µF

OUT

= 1 mA

OUT

= 10 µF

= 100 mA

OUT

= 1 µF

= 1 mA

OUT

= Any

OUT

= 100 mA

OUT

Frequency = 100 kHz

OUT

= 10 µF

= 2.5 V

OUT

= Any

OUT

= 0 µF

= V

+ 1 V

OUT

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

100

10k

100k

10M

−

V_INV_OUT(V)

Frequency (Hz)

Figure 16.

Figure 17.

NOISE SPECTRAL DENSITY

C_NR= 0 µF

C_NR= 0.01 µF

OUT

= 1 µF

OUT

= 1 µF

OUT

= 0 µF

0.1

OUT

= 10 µF

OUT

= 0 µF

OUT

= 10 µF

= 150 mA

100

= 150 mA

100

OUT

0.01

10k

100k

10k

100k

Frequency (Hz)

Figure 18.

Figure 19.

RMS NOISE VOLTAGE vs C_OUT

RMS NOISE VOLTAGE vs C_NR

140

120

100

= 5 V

OUT

= 5 V

OUT

= 3.3 V

OUT

= 3.3 V

OUT

= 1.5 V

OUT

= 1.5 V

OUT

= 0 µF

OUT

10 Hz < Frequency < 100 kHz

0.1

10p

100p

10n

C_OUT( F)

C_NR(F)

Figure 20.

Figure 21.

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Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

TPS73633-EP

TPS73601-EP, TPS73615-EP, TPS73618-EP

TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP

TYPICAL CHARACTERISTICS (continued)

For all voltage versions, T_J= 25°C, V_IN= V_OUT(nom)+ 0.5 V, I_OUT= 10 mA, V_EN= 1.7 V, and C_OUT= 0.1 µF

(unless otherwise noted)

TPS73633

LOAD TRANSIENT RESPONSE

TPS73633

LINE TRANSIENT RESPONSE

= 3.8 V

OUT

= 0 µF

= 1 µF

= 10 µF

= 400 mA

OUT

100 mV/tick

50 mV/tick

V_OUT

I_OUT

= 0 µF

OUT

50 mV/div

OUT

= 100 µF

50 mV/div

1 V/div

20 mV/tick

50 mA/tick

OUT

5.5 V

= 0.5 V/µs

400 mA

4.5 V

10 mA

10 µs/div

Figure 22.

Figure 23.

TPS73633

TURNON RESPONSE

TPS73633

TURNOFF RESPONSE

= 1 kΩ

= 20 Ω

= 0 µF

V_OUT

OUT

= 10 µF

OUT

= 20 Ω

= 1 µF

1 V/div

1V/div

OUT

= 1 kΩ

= 20 Ω

= 0 µF

OUT

= 10 µF

OUT

2 V

V_EN

1 V/div

0 V

100 µs/div

Figure 24.

Figure 25.

TPS73633

POWER UP/POWER DOWN

I_ENABLEvs TEMPERATURE

V_IN

V_OUT

0.1

−

0.01

50 ms/div

−

100

125

Temperature (°C)

Figure 26.

Figure 27.

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Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

TPS73633-EP

TPS73601-EP, TPS73615-EP, TPS73618-EP

TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP

TYPICAL CHARACTERISTICS (continued)

For all voltage versions, T_J= 25°C, V_IN= V_OUT(nom)+ 0.5 V, I_OUT= 10 mA, V_EN= 1.7 V, and C_OUT= 0.1 µF

(unless otherwise noted)

TPS73601

RMS NOISE VOLTAGE vs C_ADJ

TPS73601

I_FBvs TEMPERATURE

160

140

120

100

= 2.5 V

= 0 µF

= 39.2 kΩ

OUT

10 Hz < Frequency < 100 kHz

10p

100p

10n

−

100

125

Temperature (°C)

C_FB(F)

Figure 28.

Figure 29.

TPS73601

LOAD TRANSIENT, ADJUSTABLE VERSION

TPS73601

LINE TRANSIENT, ADJUSTABLE VERSION

= 10 nF

= 39.2 kΩ

= 2.5 V

OUT

CFB = 10 nF

= 0 µF

OUT

= 0 µF

OUT

100 mV/div

200 mV/div

OUT

= 10 µF

OUT

= 10 µF

OUT

4.5 V

400 mA

3.5 V

10 mA

OUT

25 µs/div

5 µs/div

Figure 31.

Figure 30.

Submit Documentation Feedback

Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

TPS73633-EP

TPS73601-EP, TPS73615-EP, TPS73618-EP

TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP

APPLICATION INFORMATION

supply near the regulator. This counteracts reactive

The TPS736xx belongs to a family of new-generation

input sources and improves transient response, noise

LDO regulators that use an NMOS pass transistor to

rejection, and ripple rejection.

higher-value

achieve ultra-low-dropout performance, reverse

current blockage, and freedom from output capacitor

constraints. These features, combined with low noise

and an enable input, make the TPS736xx ideal for

portable applications. This regulator family offers a

wide selection of fixed-output voltage versions and an

adjustable-output version. All versions have thermal

and overcurrent protection, including foldback current

limit.

capacitor may be necessary if large, fast rise-time

load transients are anticipated, or the device is

located several inches from the power source.

The TPS736xx does not require an output capacitor

for stability and has maximum phase margin with no

capacitor. It is designed to be stable for all available

types and values of capacitors. In applications where

V_IN− V_OUT< 0.5 V and multiple low ESR capacitors

are in parallel, ringing may occur when the product of

C_OUTand total ESR drops below 50 Ω. Total ESR

includes all parasitic resistance, including capacitor

ESR and board, socket, and solder-joint resistance.

In most applications, the sum of capacitor ESR and

trace resistance meets this requirement.

Figure 32 shows the basic circuit connections for the

fixed-voltage models. Figure 33 shows the

connections for the adjustable-output version

(TPS73601). R₁and R₂can be calculated for any

output voltage using the formula in Figure 33. Sample

resistor values for common output voltages are

shown in Figure 3. For the best accuracy, make the

parallel combination of R₁and R₂approximately 19

kΩ.

Output Noise

A precision band-gap reference is used to generate

the internal reference voltage, V_REF. This reference is

the dominant noise source within the TPS736xx and

it generates approximately 32 µV_RMS(10 Hz to

100 kHz) at the reference output (NR). The regulator

control loop gains up the reference noise with the

same gain as the reference voltage, so that the noise

voltage of the regulator is approximately given by:

Optional input capacitor.

May improve source

impedance, noise, or PSRR.

Optional output capacitor.

May improve load transient,

noise, or PSRR.

V_IN

V_OUT

OUT

TPS736xx

GND

V_OUT

V_REF

(R₁) R₂)

Optional bypass

capacitor to reduce

output noise

V_N+ 32 mV_RMS

+ 32 mV_RMS

R₂

(1)

Since the value of V_REFis 1.2 V, this relationship

reduces to:

Figure 32. Typical Application Circuit for

Fixed-Voltage Versions

mV_RMS

ǒ Ǔ

V_N(mV_RMS) + 27

V_OUT(V)

(2)

Optional input capacitor.

May improve source

Optional output capacitor.

May improve load transient,

noise, or PSRR.

for the case of no C_NR

impedance, noise, or PSRR.

V_IN

V_OUT

An internal 27-kΩ resistor in series with the noise

reduction pin (NR) forms a low-pass filter for the

voltage reference when an external noise reduction

capacitor, C_NR, is connected from NR to ground. For

C_NR= 10 nF, the total noise in the 10-Hz to 100-kHz

bandwidth is reduced by a factor of ~3.2, giving the

approximate relationship:

OUT

TPS736xx

R₁

R₂

C_FB

GND

Optional capacitor

reduces output noise

and improves

(R₁+ R₂)

1.204

V_OUT

R₁

mV_RMS

ǒ Ǔ

V_N(mV_RMS) + 8.5

V_OUT(V)

transient response.

(3)

Figure 33. Typical Application Circuit for

Adjustable-Voltage Versions

for C_NR= 10 nF.

This noise reduction effect is shown as RMS Noise

Voltage vs C_NRin Figure 21.

Input and Output Capacitor Requirements

Although an input capacitor is not required for

stability, it is good analog design practice to connect

a 0.1-µF to 1-µF low ESR capacitor across the input

Submit Documentation Feedback

Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

TPS73633-EP

TPS73601-EP, TPS73615-EP, TPS73618-EP

TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP

The TPS73601 adjustable version does not have the

noise-reduction pin available. However, connecting a

feedback capacitor, C_FB, from the output to the FB pin

reduces output noise and improves load transient

performance.

avoid degraded transient response. The boundary of

this transient dropout region is approximately twice

the

dropout.

Values

V_IN– V_OUTabove this line ensure normal transient

response.

The TPS736xx uses an internal charge pump to

develop an internal supply voltage sufficient to drive

the gate of the NMOS pass element above V_OUT. The

charge pump generates ~250 µV of switching noise

at ~4 MHz; however, charge-pump noise contribution

is negligible at the output of the regulator for most

Operating in the transient dropout region can cause

an increase in recovery time. The time required to

recover from a load transient is a function of the

magnitude of the change in load current rate, the rate

of change in load current, and the available

headroom (V_INto V_OUTvoltage drop). Under

worst-case conditions [full-scale instantaneous load

change with (V_IN– V_OUT) close to dc dropout levels],

values of I_OUTand C_OUT

the TPS736xx can take

microseconds to return to the specified regulation

accuracy.

a couple of hundred

Board Layout Recommendation to Improve

PSRR and Noise Performance

To improve ac performance such as PSRR, output

noise, and transient response, it is recommended that

the board be designed with separate ground planes

for V_INand V_OUT, with each ground plane connected

only at the GND pin of the device. In addition, the

ground connection for the bypass capacitor should

connect directly to the GND pin of the device.

Transient Response

The low open-loop output impedance provided by the

NMOS pass element in

configuration allows operation without an output

capacitor for many applications. As with any

regulator, the addition of a capacitor (nominal value

1 µF) from the output pin to ground reduces

undershoot magnitude but increases duration. In the

adjustable version, the addition of a capacitor, C_FB

from the output to the adjust pin also improves the

transient response.

voltage-follower

Internal Current Limit

The TPS736xx internal current limit helps protect the

regulator during fault conditions. Foldback helps to

protect the regulator from damage during output

short-circuit conditions by reducing current limit when

V_OUTdrops below 0.5 V. See Figure 12 for a graph of

The TPS736xx does not have active pulldown when

the output is overvoltage. This allows applications

that connect higher voltage sources, such as

alternate power supplies, to the output. This also

results in an output overshoot of several percent if

load current quickly drops to zero when a capacitor is

connected to the output. The duration of overshoot

can be reduced by adding a load resistor. The

overshoot decays at a rate determined by output

capacitor C_OUTand the internal/external load

resistance. The rate of decay is given by:

I_OUTvs V_OUT

Shutdown

The enable (EN) pin is active high and is compatible

with standard TTL-CMOS levels. V_ENbelow 0.5 V

(max) turns the regulator off and drops the ground-pin

current to approximately 10 nA. When shutdown

capability is not required, EN can be connected to

V_IN. When a pullup resistor is used, and operation

down to 1.8 V is required, use pullup resistor values

below 50 kΩ.

Fixed-voltage version:

V_OUT

dVńdt +

C_OUT 80 kW ø R_LOAD

(4)

Dropout Voltage

Adjustable-voltage version:

The TPS736xx uses an NMOS pass transistor to

achieve extremely low dropout. When (V_IN– V_OUT) is

less than the dropout voltage (V_DO), the NMOS pass

device is in its linear region of operation and the

input-to-output resistance is the R_DS-ONof the NMOS

pass element.

V_OUT

dVńdt +

(

)

C_OUT 80 kW ø R₁) R₂ø R_LOAD

(5)

For large step changes in load current, the TPS736xx

requires a larger voltage drop from V_INto V_OUTto

Submit Documentation Feedback

Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

TPS73633-EP

TPS73601-EP, TPS73615-EP, TPS73618-EP

TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP

Reverse Current

35°C above the maximum expected ambient

condition of the application. This produces

worst-case junction temperature of 125°C at the

highest expected ambient temperature and

worst-case load.

The NMOS pass element of the TPS736xx provides

inherent protection against current flow from the

output of the regulator to the input when the gate of

the pass device is pulled low. To ensure that all

charge is removed from the gate of the pass element,

EN must be driven low before the input voltage is

removed. If this is not done, the pass element may be

left on due to stored charge on the gate.

The internal protection circuitry of the TPS736xx has

been designed to protect against overload conditions.

It was not intended to replace proper heatsinking.

Continuously running the TPS736xx into thermal

shutdown degrades reliability.

After EN is driven low, no bias voltage is needed on

any pin for reverse current blocking. Note that

reverse current is specified as the current flowing out

of the IN pin due to voltage applied on the OUT pin.

There is additional current flowing into the OUT pin

due to the 80-kΩ internal resistor divider to ground

(see Figure 2 and Figure 3).

Power Dissipation

The ability to remove heat from the die is different for

each

package

type,

presenting

different

considerations in the PCB layout. The PCB area

around the device that is free of other components

moves the heat from the device to the ambient air.

Performance data for JEDEC low- and high-K boards

are shown in the Power Dissipation Ratings table.

Using heavier copper increases the effectiveness in

removing heat from the device. The addition of plated

through-holes to heat-dissipating layers also

improves the heatsink effectiveness.

For the TPS73601, reverse current may flow when

V_FBis more than 1 V above V_IN.

Thermal Protection

Thermal protection disables the output when the

junction temperature rises to approximately 160°C,

allowing the device to cool. When the junction

temperature cools to approximately 140°C, the output

circuitry is again enabled. Depending on power

dissipation, thermal resistance, and ambient

temperature, the thermal protection circuit may cycle

on and off. This limits the dissipation of the regulator,

protecting it from damage due to overheating.

Power dissipation depends on input voltage and load

conditions. Power dissipation is equal to the product

of the output current times the voltage drop across

the output pass element (V_INto V_OUT):

P_D+ (V_IN* V_OUT) I_OUT

(6)

Power dissipation can be minimized by using the

lowest-possible input voltage necessary to ensure the

required output voltage.

Any tendency to activate the thermal protection circuit

indicates excessive power dissipation or an

inadequate heatsink. For reliable operation, junction

temperature should be limited to 125°C maximum. To

estimate the margin of safety in a complete design

Package Mounting

Solder-pad footprint recommendations for the

TPS736xx are presented in application bulletin Solder

Pad Recommendations for Surface-Mount Devices

(AB-132), available from the TI web site at

www.ti.com.

(including

heatsink),

increase

the

ambient

temperature until the thermal protection is triggered;

use worst-case loads and signal conditions. For good

reliability, thermal protection should trigger at least

Submit Documentation Feedback

Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

TPS73633-EP

PACKAGE OPTION ADDENDUM

www.ti.com

19-Nov-2011

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

TPS73601MDBVREP

TPS73601MDCQREP

TPS73601MDCQREPG4

TPS73601MDRBREP

TPS73615MDBVREP

TPS73618MDBVREP

TPS73625MDBVREP

TPS73630MDBVREP

TPS73632MDBVREP

TPS73633MDBVREP

TPS73633MDBVREPG4

V62/06626-01XE

ACTIVE

SOT-23

SOT-223

SON

DBV

DCQ

DRB

DBV

DCQ

DRB

DBV

3000

2500

3000

2500

3000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU Level-1-260C-UNLIM

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

SOT-23

SOT-223

SON

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

V62/06626-01YE

Green (RoHS

& no Sb/Br)

V62/06626-01ZE

Green (RoHS

& no Sb/Br)

V62/06626-02XE

SOT-23

Green (RoHS

& no Sb/Br)

V62/06626-03XE

Green (RoHS

& no Sb/Br)

V62/06626-04XE

Green (RoHS

& no Sb/Br)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

19-Nov-2011

Status ⁽¹⁾

ACTIVE

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

V62/06626-05XE

V62/06626-06XE

V62/06626-07XE

SOT-23

DBV

3000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS73601-EP, TPS73615-EP, TPS73618-EP, TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP :

Catalog: TPS73601, TPS73615, TPS73618, TPS73625, TPS73630, TPS73632, TPS73633

•

Automotive: TPS73601-Q1

•

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

19-Nov-2011

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Nov-2011

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS73601MDBVREP

TPS73601MDRBREP

TPS73615MDBVREP

TPS73618MDBVREP

TPS73625MDBVREP

TPS73630MDBVREP

TPS73632MDBVREP

TPS73633MDBVREP

SOT-23

SON

DBV

DRB

DBV

3000

179.0

330.0

179.0

8.4

12.4

8.4

3.2

3.3

3.2

3.3

3.2

1.4

1.0

1.4

4.0

8.0

4.0

8.0

12.0

8.0

SOT-23

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Nov-2011

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS73601MDBVREP

TPS73601MDRBREP

TPS73615MDBVREP

TPS73618MDBVREP

TPS73625MDBVREP

TPS73630MDBVREP

TPS73632MDBVREP

TPS73633MDBVREP

SOT-23

SON

DBV

DRB

DBV

3000

203.0

370.0

203.0

355.0

203.0

35.0

55.0

35.0

SOT-23

Pack Materials-Page 2

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

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TPS73601MDBVREP产品参数

型号:	TPS73601MDBVREP
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	SOT-23
包装说明：	SOT-23, 5 PIN
针数：	5
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	6 weeks
风险等级：	0.88
Samacsys Confidence：	3
Samacsys Status：	Released
Samacsys PartID：	630772
Samacsys Pin Count：	5
Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	SOT23 (5-Pin)
Samacsys Footprint Name：	DBV
Samacsys Released Date：	2020-02-25 12:34:26
Is Samacsys：	N
可调性：	ADJUSTABLE
最大回动电压 1：	0.2 V
标称回动电压 1：	0.075 V
最大输入电压：	5.5 V
最小输入电压：	1.7 V
JESD-30 代码：	R-PDSO-G5
JESD-609代码：	e4
长度：	2.9 mm
湿度敏感等级：	1
功能数量：	1
输出次数：	1
端子数量：	5
工作温度TJ-Max：	150 °C
工作温度TJ-Min：	-55 °C
最高工作温度：	125 °C
最低工作温度：	-55 °C
最大输出电流 1：	0.4 A
最大输出电压 1：	5.5 V
最小输出电压 1：	1.2 V
封装主体材料：	PLASTIC/EPOXY
封装代码：	LSSOP
封装等效代码：	TSOP5/6,.11,37
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
包装方法：	TR
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
调节器类型：	ADJUSTABLE POSITIVE SINGLE OUTPUT LDO REGULATOR
座面最大高度：	1.45 mm
子类别：	Other Regulators
表面贴装：	YES
技术：	BICMOS
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.95 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	1.6 mm
Base Number Matches：	1

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