TPS7A49xx
SBVS121A –AUGUST 2010–REVISED SEPTEMBER 2010
www.ti.com
LAYOUT
PACKAGE MOUNTING
at least +35°C above the maximum expected ambient
condition of your particular application. This
Solder pad footprint recommendations for the
TPS7A49xx are available at the end of this product
datasheet and at www.ti.com.
configuration produces
a
worst-case junction
temperature of +125°C at the highest expected
ambient temperature and worst-case load.
The internal protection circuitry of the TPS7A49xx
has been designed to protect against overload
conditions. It was not intended to replace proper
heatsinking. Continuously running the TPS7A49xx
into thermal shutdown degrades device reliability.
BOARD LAYOUT RECOMMENDATIONS TO
IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for IN and OUT, with each ground plane connected
only at the GND pin of the device. In addition, the
ground connection for the output capacitor should
connect directly to the GND pin of the device.
POWER DISSIPATION
The ability to remove heat from the die is different for
each
package
type,
presenting
different
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data or JEDEC low- and high-K boards
are given in the Dissipation Ratings Table. Using
heavier copper increases the effectiveness in
removing heat from the device. The addition of plated
through-holes to heat dissipating layers also improves
the heatsink effectiveness.
Equivalent series inductance (ESL) and equivalent
series resistance (ESR) must be minimized to
maximize performance and ensure stability. Every
capacitor (CIN, COUT, CNR/SS, CBYP) must be placed as
close as possible to the device and on the same side
of the printed circuit board (PCB) as the regulator
itself.
Do not place any of the capacitors on the opposite
side of the PCB from where the regulator is installed.
The use of vias and long traces is strongly
discouraged because they may impact system
performance negatively and even cause instability.
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element, as shown in
Equation 2:
If possible, and to ensure the maximum performance
denoted in this product datasheet, use the same
layout pattern used for TPS7A49 evaluation board,
available at www.ti.com.
PD = (VIN - VOUT) IOUT
(2)
SUGGESTED LAYOUT AND SCHEMATIC
THERMAL PROTECTION
Layout is a critical part of good power-supply design.
There are several signal paths that conduct
fast-changing currents or voltages that can interact
with stray inductance or parasitic capacitance to
generate noise or degrade the power-supply
performance. To help eliminate these problems, the
IN pin should be bypassed to ground with a low ESR
Thermal protection disables the output when the
junction temperature rises to approximately +170°C,
allowing the device to cool. When the junction
temperature cools to approximately +150°C, the
output circuitry is enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage as a result of
overheating.
ceramic bypass capacitor with
dielectric.
a X5R or X7R
The GND pin should be tied directly to the PowerPAD
under the IC. The PowerPAD should be connected to
any internal PCB ground planes using multiple vias
directly under the IC.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to a maximum of
+125°C. To estimate the margin of safety in a
complete design (including heatsink), increase the
ambient temperature until the thermal protection is
triggered; use worst-case loads and signal conditions.
For good reliability, thermal protection should trigger
It may be possible to obtain acceptable performance
with alternate PCB layouts; however, the layout
shown in Figure 30 and the schematic shown in
Figure 31 have been shown to produce good results
and are meant as a guideline.
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