TPS7A9201DSKT中文资料应用文章市场行情现货热卖使用介绍-中国IC网-芯三七

当前位置：IC37首页_>T字母起始型号索引_>T字母起始型号索引第430页更新时间：2025-01-24 17:30:15

产品型号TPS7A9201DSKT的概述

TPS7A9201DSKT芯片概述 TPS7A9201DSKT是一款高性能线性稳压器，属于德州仪器（Texas Instruments）旗下的TPS系列。它不仅在电源管理应用中具有极高的效率和稳定性，而且还支持多种工作模式，使其在不同的工作环境中都能运作良好。此芯片的设计旨在满足现代电子设备对安全性、功耗和空间利用的高要求，广泛应用于消费电子、工业控制、通信和汽车电子等领域。芯片的基本参数 TPS7A9201DSKT具有多项优异的性能指标，使其成为许多复杂电源设计的首选。以下为该芯片的详细参数： 1. 输入电压范围：TPS7A9201DSKT的输入电压范围为2.5V至20V，充分满足了大部分应用场景的需求。其低输入电压能力使得该芯片在电池供电设备中表现尤为出色。 2. 输出电压：此稳压器可以调节输出电压，范围为1.2V至17V，根据外部电阻的不同选择进行配置。 3. 输出电流：最大输...

产品型号TPS7A9201DSKT的Datasheet PDF文件预览

Support &

Community

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

TPS7A92

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

TPS7A92

2A 高精度、低噪声 LDO 稳压器

1 特性

3 说明

•

整个线路、负载和温度范围内的精度达 1.0%

TPS7A92 是一款低噪声 (4.8µV_RMS)、低压降 (LDO)

稳压器，可提供 2A 负载电流，其压降仅为 180mV。

低输出噪声：4.6µV_RMS(10Hz–100kHz)

低压降：2A 时 180mV（典型值）

宽输入电压范围：1.4V 至 6.5V

宽输出电压范围：0.8V 至 5.2V

高电源纹波抑制 (PSRR)：

TPS7A92 输出可通过外部电阻在 0.8V 至 5.2V 范围内

进行调节。TPS7A92 的宽输入电压范围支持其在低至

1.4V 和高达 6.5V 的电压下工作。

凭借 1% 的输出电压精度（整个线路、负载和温度范

围内）和用于降低浪涌电流的软启动功能，TPS7A92

非常适合为敏感类模拟低压器件 [例如压控振荡器

(VCO)、模数转换器 (ADC)、数模转换器 (DAC)、高端

处理器和现场可编程门阵列 (FPGA)] 供电。

–

直流时为 60dB

100kHz 时为 40dB

1MHz 时为 40dB

•

快速瞬态响应

通过可选软启动充电电流实现可调节的启动浪涌控

制

TPS7A92 旨在为高速通信、视频、医疗或测试和测量

等应用中的噪声敏感类组件供电。此器件具有极低的

4.6µV_RMS输出噪声和宽带 PSRR（1MHz 时为

40dB），可最大限度地减少相位噪声和时钟抖动。这

些特性最大限度提升了计时器件、ADC 和 DAC 的性

能。

•

开漏电源正常 (PG) 输出

_θJC= 3.2°C/W

与 22µF 或更大的陶瓷输出电容器一起工作时保持

稳定

•

2.5mm × 2.5mm 10 引脚 WSON 封装

器件信息⁽¹⁾

2 应用

器件型号

TPS7A92

封装

封装尺寸（标称值）

•

高速模拟电路：

WSON (10)

2.50mm x 2.50mm

–

压控振荡器 (VCO)、模数转换器 (ADC)、数模

转换器 (DAC) 以及低压差分信令 (LVDS)

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

成像：互补金属氧化物半导体 (CMOS) 传感器，视

频专用集成电路 (ASIC)

空白

•

测试和测量

仪器仪表、医疗和音频

数字负载：串化解串器 (SerDes)，现场可编程栅极

阵列 (FPGA)，DSP

典型应用电路

典型应用图

TPS7A92

2.0 V

OUT

1.2 V

C_OUT

22 ꢀF

C_IN

R₁5.9 kW

22 mF

SS_CTRL

NR/SS

C_FF10 nF

V_OUT

R₂

11.8 kW

OUT

C_NR/SS

R_PG

0.1 mF

20 kW

GND

VDD

ADC3xxx

ADC3xJxx

ADS4xJBxx

ADC5xJxx

ADC12Jxxxx

ADC

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBVS318

TPS7A92

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

www.ti.com.cn

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 3

6.1 Absolute Maximum Ratings ...................................... 3

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 4

6.6 Typical Characteristics.............................................. 6

Detailed Description ............................................ 12

7.1 Overview ................................................................. 12

7.2 Functional Block Diagram ....................................... 12

7.3 Feature Description................................................. 12

7.4 Device Functional Modes........................................ 16

Application and Implementation ........................ 17

8.1 Application Information............................................ 17

8.2 Typical Application .................................................. 21

Power Supply Recommendations...................... 22

10 Layout................................................................... 22

10.1 Layout Guidelines ................................................. 22

10.2 Layout Example .................................................... 23

11 器件和文档支持 ..................................................... 24

11.1 器件支持................................................................ 24

11.2 文档支持 ............................................................... 24

11.3 接收文档更新通知 ................................................. 24

11.4 社区资源................................................................ 25

11.5 商标....................................................................... 25

11.6 静电放电警告......................................................... 25

11.7 术语表 ................................................................... 25

12 机械、封装和可订购信息....................................... 25

4 修订历史记录

Changes from Revision A (April 2018) to Revision B

Page

•

Added footnotes to Recommended Operating Conditions table ............................................................................................ 4

Changes from Original (July 2017) to Revision A

Page

•

已更改 value of C_NR/SScapacitor from 10 nF to 100 nF in Application Example figure........................................................ 21

TPS7A92

www.ti.com.cn

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

5 Pin Configuration and Functions

DSK Package

2.5-mm × 2.5-mm 10-Pin WSON

Top View

OUT

Thermal

Pad

NR/SS

GND

SS_CTRL

Not to scale

Pin Functions

NAME

NO.

I/O

DESCRIPTION

Enable pin. This pin turns the LDO on and off. If V_EN≥ V_IH(EN), the regulator is enabled. If V_EN≤ V_IL(EN), the

regulator is disabled. The EN pin must be connected to IN if the enable function is not used.

Feedback pin. This pin is the input to the control loop error amplifier and is used to set the output voltage of the

device.

GND

—

Device GND. Connect to the device thermal pad.

9, 10

Input pin. A 10 µF or greater input capacitor is required.

Noise reduction pin. Connect this pin to an external capacitor to bypass the noise generated by the internal band-

gap reference. The capacitor reduces the output noise to very low levels and sets the output ramp rate to limit

inrush current.

NR/SS

—

OUT

1, 2

Regulated output. A 22 µF or greater capacitor must be connected from this pin to GND for stability.

Open-drain power-good indicator pin for the LDO output voltage. A 10-kΩ to 100-kΩ external pullup resistor is

required. This pin can be left floating or connected to GND if not used.

Soft-start control pin. Connect this pin either to GND or IN to change the NR/SS capacitor charging current. If a

C_NR/SScapacitor is not used, SS_CTRL must be connected to GND to avoid output overshoot.

SS_CTRL

Thermal pad

—

Connect the thermal pad to the printed circuit board (PCB) ground plane, for an example layout see 图 42.

6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range and all voltages with respect to GND (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

IN, PG, EN

7.0

7.5

V_IN+ 0.3⁽²⁾

3.6

IN, PG, EN (5% duty cycle, pulse duration = 200 µs)

Voltage

OUT

SS_CTRL

NR/SS, FB

OUT

Internally limited

Current

PG (sink current into device)

Operating junction, T_J

Storage, T_stg

–55

150

Temperature

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The absolute maximum rating is V_IN+ 0.3 V or 7.0 V, whichever is smaller.

TPS7A92

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

www.ti.com.cn

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

±2000

±500

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)

MIN

MAX

6.5

UNIT

V_IN

Input supply voltage range

Output voltage range

1.4

V_OUT

I_OUT

C_IN

0.8 - 1%

5.2 + 1%

Output current

Input capacitor, each input

Output capacitor⁽¹⁾⁽²⁾

µF

kΩ

°C

C_OUT

C_NR/SS

R_PG

T_J

Noise-reduction capacitor

Power-good pullup resistance

Junction temperature range

100

125

–40

(1) When I_OUT≤ 1 A, the C_OUTminimum is 10 µF and the effective output capacitance of 5 µF (minimum) is required for stability.

(2) Effective output capacitance of 11 µF (minimum) is required for stability.

6.4 Thermal Information

TPS7A92

THERMAL METRIC⁽¹⁾

DSK (WSON)

10 PINS

56.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

46.3

29.1

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.8

ψ_JB

29.4

R_θJC(bot)

3.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

over operating temperature range (T_J= –40°C to +125°C), V_IN= 1.4 V, V_OUT(TARGET)= 0.8 V, I_OUT= 50 mA, V_EN= 1.4 V, C_OUT

= 22 μF, C_NR/SS= 0 nF, C_FF= 0 nF, SS_CTRL = GND, PG pin pulled up to V_INxwith 100 kΩ, and for each channel (unless

otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN

Input supply voltage range

Reference voltage

Input supply UVLO

V_UVLO

1.4

6.5

V_REF

V_UVLO

V_HYS

0.8

1.31

290

V_INrising

1.39

Output voltage range

Output voltage accuracy⁽¹⁾⁽²⁾

Line regulation

0.8 – 1.0%

–1.0%

5.2 + 1.0%

1.0%

V_OUT

0.8 V ≤ V_OUT≤ 5 V, 5 mA ≤ I_OUT≤ 2 A

I_OUT= 5 mA, 1.4 V ≤ V_IN≤ 6.5 V

5 mA ≤ I_OUT≤ 2 A

ΔV_OUT(ΔVIN)

0.003

0.03

%/V

%/A

ΔV_OUT(ΔIOUT)

Load regulation

V_IN≥ 1.4 V, 0.8 V ≤ V_OUT≤ 5.0 V,

I_OUT= 2 A, V_FB= 0.8 V – 3%

V_DO

Dropout voltage

400

(1) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.

(2) The device is not tested under conditions where V_IN> V_OUT+ 2.5 V and I_OUT= 2 A because the power dissipation is higher than the

maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the power

dissipation limit of the package under test.

TPS7A92

www.ti.com.cn

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

Electrical Characteristics (continued)

over operating temperature range (T_J= –40°C to +125°C), V_IN= 1.4 V, V_OUT(TARGET)= 0.8 V, I_OUT= 50 mA, V_EN= 1.4 V, C_OUT

= 22 μF, C_NR/SS= 0 nF, C_FF= 0 nF, SS_CTRL = GND, PG pin pulled up to V_INxwith 100 kΩ, and for each channel (unless

otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_OUTforced at 0.9 × V_OUT(TARGET)

V_IN= V_OUT(TARGET)+ 300 mV

I_LIM

Output current limit

2.3

2.6

2.9

Both channels enabled, per channel,

V_IN= 6.5 V, I_OUT= 5 mA

2.1

0.1

3.5

I_GND

GND pin current

Both channels enabled, per channel,

V_IN= 1.4 V, I_OUT= 2 A

Both channels shutdown, per channel, PGx = (open),

V_IN= 6.5 V, V_EN= 0.5 V

I_SDN

I_EN

Shutdown GND pin current

EN pin current

0.2

0.4

µA

V_IN= 6.5 V, 0 V ≤ V_EN≤ 6.5 V

–0.2

EN pin low-level input voltage

(device disabled)

V_IL(EN)

EN pin high-level input voltage

(device enabled)

V_IH(EN)

I_{SS_CTRL}

V_IT(PG)

1.1

–0.2

82%

6.5

0.2

SS_CTRL pin current

PG pin threshold

V_IN= 6.5 V, 0 V ≤ V_{SS_CTRL}≤ 6.5 V

µA

For PG transitioning low with falling V_OUT, expressed

as a percentage of V_OUT(TARGET)

88.9%

93%

For PG transitioning high with rising V_OUT, expressed

as a percentage of V_OUT(TARGET)

V_hys(PG)

PG pin hysteresis

V_OL(PG)

I_lkg(PG)

PG pin low-level output voltage

PG pin leakage current

V_OUT< V_IT(PG), I_PG= –1 mA (current into device)

V_OUT> V_IT(PG), V_PG= 6.5 V

0.4

µA

V_NR/SS= GND, 1.4 V ≤ V_IN≤ 6.5 V,

V_{SS_CTRL}= GND

4.0

6.2

9.0

I_NR/SS

NR/SS pin charging current

µA

V_NR/SS= GND, 1.4 V ≤ V_IN≤ 6.5 V, V_{SS_CTRL}= V_IN

100

150

100

I_FB

FB pin leakage current

V_IN= 6.5 V, V_FB= 0.8 V

–100

f = 500 kHz, V_INx= 2.0 V, V_OUT= 1.2 V,

I_OUT= 2 A, C_NR/SS= 10 nF, C_FF= 10 nF

PSRR

Power-supply ripple rejection

4.6

BW = 10 Hz to 100 kHz, V_IN= 1.8 V, V_OUT= 0.8 V,

I_OUT= 2.0 A, C_NR/SS= 10 nF, C_FF= 10 nF

V_n

Output noise voltage

Noise spectral density

μV_RMS

nV/√Hz

f = 10 kHz, V_IN= 1.8 V, V_OUT= 0.8 V,

I_OUT= 2.0 A, C_NR/SS= 10 nF, C_FF= 10 nF

Output active discharge

resistance

R_diss

V_EN= GND

250

Shutdown, temperature increasing

Reset, temperature decreasing

160

140

T_sd

Thermal shutdown temperature

°C

TPS7A92

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

www.ti.com.cn

6.6 Typical Characteristics

at T_J= 25°C, 1.4 V ≤ V_IN≤ 6.5 V, V_IN≥ V_OUT(NOM)+ 0.3 V, V_OUT= 0.8 V, SS_CTRL = GND, I_OUT= 5 mA, V_EN= 1.1 V, C_OUT

22 μF, C_NR/SS= C_FF= 0 nF, PG pin pulled up to V_OUTwith 100 kΩ, and SS_CTRL = GND (unless otherwise noted)

V_IN

1.5 V

1.7 V

2.0 V

2.2 V

V_IN

1.4 V

1.5 V

1.8 V

2.5 V

2.0 V

100

10k

Frequency (Hz)

100k

10M

100

10k

Frequency (Hz)

100k

10M

Figu

V_OUT= 0.8 V, I_OUT= 2.0 A, C_OUT= 22 µF,

C_NR/SS= C_FF= 10 nF

V_OUT= 1.2 V, I_OUT= 2.0 A, C_OUT= 22 µF,

C_NR/SS= C_FF= 10 nF

图 1. PSRR vs Frequency and Input Voltage

图 2. PSRR vs Frequency and Input Voltage

V_IN

3.6 V

3.7 V

3.8 V

4.0 V

4.35 V

5.5 V

5.6 V

5.7 V

5.8 V

5.9 V

6.0 V

100

10k

Frequency (Hz)

100k

10M

100

10k

Frequency (Hz)

100k

10M

Figu

V_OUT= 3.3 V, I_OUT= 2.0 A, C_OUT= 22 µF,

C_NR/SS= C_FF= 10 nF

V_OUT= 5 V, I_OUT= 2.0 A, C_OUT= 22 µF,

C_NR/SS= C_FF= 10 nF

图 3. PSRR vs Frequency and Input Voltage

图 4. PSRR vs Frequency and Input Voltage

I_OUT= 100 mA

I_OUT= 500 mA

I_OUT= 1 A

I_OUT= 1.5 A

I_OUT= 2 A

I_OUT= 100 mA

I_OUT= 500 mA

I_OUT= 1 A

I_OUT= 1.5 A

I_OUT= 2 A

100

10k

100k

10M

100

10k

100k

10M

Frequency (Hz)

Figu

V_OUT= 1.2 V, V_IN= V_EN= 1.7 V, C_OUT= 22 µF,

C_NR/SS= C_FF= 10 nF

V_OUT= 3.3 V, V_IN= V_EN= 3.8 V, C_OUT= 22 µF,

C_NR/SS= C_FF= 10 nF

图 5. PSRR vs Frequency and Output Current

图 6. PSRR vs Frequency and Output Current

TPS7A92

www.ti.com.cn

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

Typical Characteristics (接下页)

at T_J= 25°C, 1.4 V ≤ V_IN≤ 6.5 V, V_IN≥ V_OUT(NOM)+ 0.3 V, V_OUT= 0.8 V, SS_CTRL = GND, I_OUT= 5 mA, V_EN= 1.1 V, C_OUT

22 μF, C_NR/SS= C_FF= 0 nF, PG pin pulled up to V_OUTwith 100 kΩ, and SS_CTRL = GND (unless otherwise noted)

V_OUT

0.8 V, 4.6 mV_RMS

1.2 V, 5.3 mV_RMS

1.8 V, 6.6 mV_RMS

3.3 V, 9.6 mV_RMS

5 V, 12.8 mV_RMS

0.5

0.2

0.1

0.05

0.02

0.01

C_NR= Open

C_NR= 10 nF

C_NR= 100 nF

C_NR= 1 uF

C_NR= 10 uF

0.005

0.002

0.001

100

10k

100k

10M

100

10k

100k

10M

Frequency (Hz)

Figu

V_OUT= 1.2 V, V_IN= V_EN= 1.7 V, I_OUT= 2.0 A, C_OUT= 22 µF,

C_FF= 10 nF

V_IN= V_OUT+ 1.0 V, I_OUT= 2.0 A, C_IN= C_OUT= 22 µF,

C_NR/SS= C_FF= 10 nF, V_RMSBW = 10 Hz to 100 kHz

图 7. PSRR vs Frequency and C_NR/SS

图 8. Spectral Noise Density vs Frequency and

Output Voltage

C_NR

C_FF

None, 11.2 mV_RMS

1 mF, 4.8 mV_RMS

10µF, 4.7 mV_RMS

None, 7.8 mV_RMS

10 nF, 5.3 mV_RMS

10 nF, 5.1 mV_RMS

100 nF, 4.8 mV_RMS

100 nF, 5.3 mV_RMS

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

100

10k

100k

10M

100

10k

100k

10M

Frequency (Hz)

V_IN= 2.2 V, V_OUT= 1.2 V, I_OUT= 2.0 A, C_IN= C_OUT= 22 µF,

C_FF= 10 nF, V_RMSBW = 10 Hz to 100 kHz

V_IN= 2.2 V, V_OUT= 1.2 V, I_OUT= 2.0 A, C_IN= C_OUT= 22 µF,

C_NR/SS= 10 nF, V_RMSBW = 10 Hz to 100 kHz

图 10. Spectral Noise Density vs Frequency and C_FF

图 9. Spectral Noise Density vs Frequency and C_NR/SS

Temperature

C_OUT

10 mF, 5.3 mV_RMS

22 mF, 5.4 mV_RMS

100 mF, 6.1 mV_RMS

-40èC

0èC

25èC

85èC

125èC

2.8

2.6

2.4

2.2

0.5

0.2

0.1

0.05

0.02

0.01

0.005

0.002

0.001

1.8

100

10k

100k

10M

100

200

300

400

500

600

700

800

Frequency (Hz)

Output Voltage (mV)

Figu

V_IN= 1.4 V, V_OUT= 0.8 V

V_IN= 2.2 V, V_OUT= 1.2 V, I_OUT= 2.0 A, C_IN= 22 µF,

C_NR/SS= C_FF= 10 nF, V_RMSBW = 10 Hz to 100 kHz

图 11. Spectral Noise Density vs Frequency and C_OUT

图 12. Current Limit Foldback

TPS7A92

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

www.ti.com.cn

Typical Characteristics (接下页)

at T_J= 25°C, 1.4 V ≤ V_IN≤ 6.5 V, V_IN≥ V_OUT(NOM)+ 0.3 V, V_OUT= 0.8 V, SS_CTRL = GND, I_OUT= 5 mA, V_EN= 1.1 V, C_OUT

22 μF, C_NR/SS= C_FF= 0 nF, PG pin pulled up to V_OUTwith 100 kΩ, and SS_CTRL = GND (unless otherwise noted)

400

350

300

250

200

150

100

2.8

2.7

2.6

2.5

2.4

Temperature

25èC

-40èC

0èC

125èC

85èC

-50

-25

100

125

150

250

500

750 1000 1250 1500 1750 2000

Output Current (mA)

Temperature (èC)

V_IN= 1.4 V, V_OUT= 0.8 V

V_IN= 5.5 V

图 13. Current Limit vs Temperature

图 14. Dropout Voltage vs Output Current

600

500

400

300

200

100

0.5

0.4

0.3

0.2

0.1

Temperature

-40èC

0èC

25èC

85èC

125èC

-40èC

0èC

25èC

85èC

125èC

-0.1

-0.2

-0.3

-0.4

-0.5

1.5

2.5

3.5

4.5

5.5

250

500

750 1000 1250 1500 1750 2000

Output Current (mA)

Input Voltage (V)

I_OUT= 2 A

V_IN= 1.4 V

图 15. Dropout Voltage vs Input Voltage

图 16. Load Regulation

0.5

0.4

0.3

0.2

0.1

Temperature

25èC

-40èC

0èC

25èC

85èC

125èC

-40èC

0èC

125èC

2.5

85èC

1.5

-0.1

-0.2

-0.3

-0.4

-0.5

0.5

1.5

2.5

3.5

4.5

5.5

6.5

0.5

1.5

2.5

3.5

4.5

5.5

6.5

Input Voltage (V)

I_OUT= 50 mA

V_EN= 0.4 V

图 17. Line Regulation

图 18. Shutdown Current vs Input Voltage

TPS7A92

www.ti.com.cn

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

Typical Characteristics (接下页)

at T_J= 25°C, 1.4 V ≤ V_IN≤ 6.5 V, V_IN≥ V_OUT(NOM)+ 0.3 V, V_OUT= 0.8 V, SS_CTRL = GND, I_OUT= 5 mA, V_EN= 1.1 V, C_OUT

22 μF, C_NR/SS= C_FF= 0 nF, PG pin pulled up to V_OUTwith 100 kΩ, and SS_CTRL = GND (unless otherwise noted)

4.5

2.5

Temperature

25èC

Temperature

25èC

-40èC

0èC

125èC

-40èC

0èC

125èC

85èC

3.5

2.5

1.5

0.5

1.5

2.5

3.5

4.5

5.5

6.5

250

500

750 1000 1250 1500 1750 2000

Output Current (mA)

Input Voltage (V)

V_IN= 1.4 V

图 20. Ground Current vs Input Voltage

图 19. Ground Current vs Output Current

600

500

400

300

200

100

600

500

400

300

200

100

Temperature

-40èC

0èC

25èC

85èC

125èC

-40èC

0èC

25èC

85èC

125èC

0.5

1.5

PG Current (mA)

2.5

0.5

1.5

PG Current (mA)

2.5

图 21. PG Low Level Voltage vs PG Current

图 22. PG Low Level Voltage vs PG Current

(V_IN= 1.4 V)

(V_IN= 6.5 V)

100

PG Falling

PG Rising

-50

-25

100

125

150

-50

-25

100

125

150

Temperature (èC)

V_IN= V_PG= 6.5 V

图 23. PG Threshold vs Temperature

图 24. PG Leakage Current vs Temperature

TPS7A92

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

www.ti.com.cn

Typical Characteristics (接下页)

at T_J= 25°C, 1.4 V ≤ V_IN≤ 6.5 V, V_IN≥ V_OUT(NOM)+ 0.3 V, V_OUT= 0.8 V, SS_CTRL = GND, I_OUT= 5 mA, V_EN= 1.1 V, C_OUT

22 μF, C_NR/SS= C_FF= 0 nF, PG pin pulled up to V_OUTwith 100 kΩ, and SS_CTRL = GND (unless otherwise noted)

150

140

130

120

110

100

8.5

V_IN

1.4 V

V_IN

1.4 V

6.5 V

7.5

6.5

5.5

4.5

-50

-25

100

125

150

-50

-25

100

125

150

Temperature (èC)

图 25. Soft-Start Current vs Temperature

图 26. Soft-Start Current vs Temperature

(SS_CTRL = V_IN

(SS_CTRL = GND)

)

1.4

1.35

1.3

1.1

UVLO Falling

UVLO Rising

V_IL(EN)

V_IH(EN)

0.9

0.8

0.7

0.6

0.5

0.4

1.25

1.2

1.15

1.1

1.05

-50

-25

100

125

150

-50

-25

100

125

150

Temperature (èC)

图 27. Enable Threshold vs Temperature

图 28. Input UVLO Threshold vs Temperature

Output Current

Load Transient

Output Current

Load Transient

-10

-20

-30

-40

-50

-60

-70

-80

-10

-20

-30

-40

-50

-60

-70

-80

60 120 180 240 300 360 420 480 540 600

Time ({/ms}

60 120 180 240 300 360 420 480 540 600

Time (ms)

Figu

V_IN= 1.5 V, I_OUT= 100 mA to 2 A to 100 mA at 1 A/µs,

C_OUT= 22 µF, V_PG= V_OUT

V_IN= 5.5 V, I_OUT= 100 mA to 2 A to 100 mA at 1 A/µs,

C_OUT= 22 µF, V_PG= V_OUT

图 29. Load Transient Response (V_OUT= 1.2 V)

图 30. Load Transient Response (V_OUT= 5.0 V)

TPS7A92

www.ti.com.cn

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

Typical Characteristics (接下页)

at T_J= 25°C, 1.4 V ≤ V_IN≤ 6.5 V, V_IN≥ V_OUT(NOM)+ 0.3 V, V_OUT= 0.8 V, SS_CTRL = GND, I_OUT= 5 mA, V_EN= 1.1 V, C_OUT

22 μF, C_NR/SS= C_FF= 0 nF, PG pin pulled up to V_OUTwith 100 kΩ, and SS_CTRL = GND (unless otherwise noted)

V_EN

1 V/div

V_IN

2 V/div

V_OUT

200 mV/div

V_OUT

20 mV/div

V_PG

200mV/div

V_PG

1 V/div

Time (50 ms/div)

Time (200 ms/div)

V_IN= 1.4 V, V_PG= V_OUT

V_IN= 1.4 V to 6.5 V to 1.4 V at 2 V/µs, V_OUT= 0.8 V,

I_OUT= 2 A, C_NR/SS= C_FF= 10 nF, V_PG= V_OUT

图 31. Line Transient

图 32. Start-Up (SS_CTRL = GND, C_NR/SS= 0 nF)

V_EN

1 V/div

V_OUT

200 mV/div

V_PG

200 mV/div

V_PG

200 mV/div

Time (500 ms/div)

Time (50 ms/div)

V_IN= 1.4 V, V_PG= V_OUT

图 33. Start-Up (SS_CTRL = GND, C_NR/SS= 10 nF)

图 34. Start-Up (SS_CTRL = V_IN, C_NR/SS= 10 nF)

V_EN

1 V/div

V_OUT

200 mV/div

V_PG

200 mV/div

Time (2 ms/div)

V_IN= 1.4 V, V_PG= V_OUT

图 35. Start-Up (SS_CTRL = V_IN, C_NR/SS= 1 µF)

TPS7A92

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

www.ti.com.cn

7 Detailed Description

7.1 Overview

The TPS7A92 is a low-noise, high PSRR, low dropout (LDO) regulator capable of sourcing a 2-A load with only

400 mV of maximum dropout. The TPS7A92 can operate down to a 1.4-V input voltage and a 0.8-V output

voltage. This combination of low-noise, high PSRR, and low dropout voltage makes the device an ideal LDO to

power a multitude of loads from noise-sensitive communication components in high-speed communications

applications to high-end microprocessors or field-programmable gate arrays (FPGAs).

As shown in the Functional Block Diagram section, the TPS7A92 linear regulator features a low-noise, 0.8-V

internal reference that can be filtered externally to obtain even lower output noise. The internal protection circuitry

(such as the undervoltage lockout) prevents the device from turning on before the input is high enough to ensure

accurate regulation. Foldback current limiting is also included, allowing the output to source the rated output

current when the output voltage is in regulation but reduces the allowable output current during short-circuit

conditions. The internal power-good detection circuit allows users to sequence down-stream supplies and be

alerted if the output voltage is below a regulation threshold.

7.2 Functional Block Diagram

PSRR

Boost

Current

Limit

OUT

Charge

Pump

Active

R_NR/SS= 280 kW

Discharge

0.8-V

V_REF

Error

Amp

Soft-Start

Control

I_NR/SS

SS_CTRL

NR/SS

200 pF

Internal

Controller

UVLO

Circuits

0.889 x V_REF

Thermal

Shutdown

GND

7.3 Feature Description

7.3.1 Output Enable

The enable pin for the TPS7A92 is active high. The output voltage is enabled when the enable pin voltage is

greater than V_IH(EN)and disabled with the enable pin voltage is less than V_IL(EN). If independent control of the

output voltage is not needed, then connect the enable pin to the input.

The TPS7A92 has an internal pulldown MOSFET that connects a discharge resistor from V_OUTto ground when

the device is disabled to actively discharge the output voltage.

7.3.2 Dropout Voltage (V_DO

)

Dropout voltage (V_DO) is defined as the V_IN– V_OUTvoltage at the rated current (I_RATED) of 2 A, where the pass-

FET is fully on and in the ohmic region of operation. V_DOindirectly specifies a minimum input voltage above the

nominal programmed output voltage at which the output voltage is expected to remain in regulation. If the input

falls below the nominal output regulation, then the output follows the input.

TPS7A92

www.ti.com.cn

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

Feature Description (接下页)

Dropout voltage is determined by the R_DS(ON)of the pass-FET. Therefore, if the LDO operates below the rated

current, then the V_DOfor that current scales accordingly. The R_DS(ON)for the TPS7A92 can be calculated using 公

式 1:

V_DO

R_DS(ON)

I_RATED

(1)

7.3.3 Output Voltage Accuracy

Output voltage accuracy specifies minimum and maximum output voltage error, relative to the expected nominal

output voltage stated as a percent. The TPS7A92 features an output voltage accuracy of 1% that includes the

errors introduced by the internal reference, load regulation, and line regulation variance across the full range of

rated load and line operating conditions over temperature, as specified by the Electrical Characteristics table.

Output voltage accuracy also accounts for all variations between manufacturing lots.

7.3.4 High Power-Supply Ripple Rejection (PSRR)

PSRR is a measure of how well the LDO control loop rejects noise from the input source to make the dc output

voltage as noise-free as possible across the frequency spectrum (usually measured from 10 Hz to 10 MHz).

Even though PSRR is a loss in noise signal amplitude, the PSRR curves in the Typical Characteristics section

are shown as positive values in decibels (dB) for convenience. 公式 2 gives the PSRR calculation as a function

of frequency where input noise voltage [V_IN(f)] and output noise voltage [V_OUT(f)] are the amplitudes of the

respective sinusoidal signals.

≈

∆

’

◊

V (f)

PSRR (dB) = 20 Log₁₀

V_OUT(f)

(2)

Noise that couples from the input to the internal reference voltage is a primary contributor to reduced PSRR

performance. Using a noise-reduction capacitor is recommended to filter unwanted noise from the input voltage,

which creates a low-pass filter with an internal resistor to improve PSRR performance at lower frequencies.

LDOs are often employed not only as a step-down regulators, but also to provide exceptionally clean power rails

for noise-sensitive components. This usage is especially true for the TPS7A92, which features an innovative

circuit to boost the PSRR between 200 kHz and 1 MHz. This boost circuit helps further filter switching noise from

switching-regulators that operate in this region; see 图 1. To achieve the maximum benefit of this PSRR boost

circuit, using a capacitor with a minimum impedance in the 100-kHz to 1-MHz band is recommended.

7.3.5 Low Output Noise

LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits. The

TPS7A92 is designed for system applications where minimizing noise on the power-supply rail is critical to

system performance. This scenario is the case for phase-locked loop (PLL)-based clocking circuits where

minimum phase noise is all important, or in test and measurement systems where even small power-supply

noise fluctuations can distort instantaneous measurement accuracy.

The TPS7A92 includes a low-noise reference ensuring minimal output noise in normal operation. Further

improvements can be made by adding a noise reduction capacitor (C_NR/SS), a feedforward capacitor (C_FF), or a

combination of the two. See the Noise-Reduction and Soft-Start Capacitor (C_NR/SS) and Feed-Forward Capacitor

(C_FF) sections for additional design information.

For more information on noise and noise measurement, see the How to Measure LDO Noise white paper.

7.3.6 Output Soft-Start Control

Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after the EN and UVLO

thresholds are exceeded. The noise-reduction capacitor (C_NR/SS) serves a dual purpose of both governing output

noise reduction and programming the soft-start ramp during turn-on. Larger values for the noise-reduction

capacitors decrease the noise but also result in a slower output turn-on ramp rate.

TPS7A92

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

www.ti.com.cn

Feature Description (接下页)

The TPS7A92 features an SS_CTRL pin. When the SS_CTRL pin is grounded, the charging current for the

NR/SS pin is 6.2 µA (typ); when this pin is connected to IN, the charging current for the NR/SS pin is increased

to 100 µA (typ). The higher current allows the use of a much larger noise-reduction capacitor and maintains a

reasonable startup time. 图 36 shows a simplified block diagram of the soft-start circuit. The switch SW is opened

to turn off the I_NR/SScurrent source after V_FBreaches approximately 97% of V_REF. The final 3% of V_NR/SSis

charged through the noise reduction resistor (R_NR), which creates an RC delay. R_NRis approximately 280 kΩ and

applications that require the highest accuracy when using a large value C_NR/SSmust take this RC delay into

account.

If a noise-reduction capacitor is not used on the NR/SS pin, tying the SS_CTRL pin to the IN pin can result in

output voltage overshoot of approximately 10%. This overshoot is minimized by either connecting the SS_CTRL

pin to GND or using a capacitor on the NR/SS pin.

I_NR/SS

R_NR

NR/SS Control

V_REF

C_NR/SS

V_FB

GND

图 36. Simplified Soft-Start Circuit

7.3.7 Power-Good Function

The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage.

When the feedback pin voltage falls below the PG threshold voltage (V_IT(PG)), the PG pin open-drain output

engages and pulls the PG pin close to GND. When the feedback voltage exceeds the V_IT(PG)threshold by an

amount greater than V_HYS(PG), the PG pin becomes high impedance. By connecting a pullup resistor to an

external supply, any downstream device can receive power-good as a logic signal that can be used for

sequencing. Make sure that the external pullup supply voltage results in a valid logic signal for the receiving

device or devices. Using a pullup resistor from 10 kΩ to 100 kΩ is recommended. Using an external reset device

such as the TPS3890 is also recommended in applications where high accuracy is needed or in applications

where microprocessor induced resets are needed.

When using a feed-forward capacitor (C_FF), the time constant for the LDO startup is increased whereas the

power-good output time constant stays the same, possibly resulting in an invalid status of the power-good output.

To avoid this issue and to receive a valid PG output, make sure that the time constant of both the LDO startup

and the power-good output are matching, which can be done by adding a capacitor in parallel with the power-

good pullup resistor. For more information, see the Pros and Cons of Using a Feedforward Capacitor with a Low-

Dropout Regulator application report.

The state of PG is only valid when the device is operating above the minimum input voltage of the device and

power good is asserted regardless of the output voltage state when the input voltage falls below the UVLO

threshold minus the UVLO hysteresis. 图 37 illustrates a simplified block diagram of the power-good circuit.

When the input voltage falls below approximately 0.8 V, there is not enough gate drive voltage to keep the open-

drain, power-good device turned on and the power-good output is pulled high. Connecting the power-good pullup

resistor to the output voltage can help minimize this effect.

TPS7A92

www.ti.com.cn

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

Feature Description (接下页)

V_PG

V_REF

V_IN

V_FB

GND

UVLO

GND

图 37. Simplified PG Circuit

7.3.8 Internal Protection Circuitry

7.3.8.1 Undervoltage Lockout (UVLO)

The TPS7A92 has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing

a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the

input drops during turn on, the UVLO has approximately 290 mV of hysteresis.

The UVLO circuit responds quickly to glitches on V_INand disables the output of the device if this rail starts to

collapse too quickly. Use an input capacitor that is large enough to slow input transients to less then two volts

per microsecond.

7.3.8.2 Internal Current Limit (I_CL

)

The internal current-limit circuit is used to protect the LDO against transient high-load current faults or shorting

events. The LDO is not designed to operate in current limit under steady-state conditions. During an overcurrent

event where the output voltage is pulled 10% below the regulated output voltage, the LDO sources a constant

current as specified in the Electrical Characteristics table. When the output voltage falls, the amount of output

current is reduced to better protect the device. During a hard short-circuit event, the current is reduced to

approximately 2.2 A. See 图 12 in the Typical Characteristics section for more information about the current-limit

foldback behavior. Note also that when a current-limit event occurs, the LDO begins to heat up because of the

increase in power dissipation. The increase in heat can trigger the integrated thermal shutdown protection circuit.

7.3.8.3 Thermal Protection

The TPS7A92 contains a thermal shutdown protection circuit to turn off the output current when excessive heat is

dissipated in the LDO. Thermal shutdown occurs when the thermal junction temperature (T_J) of the pass-FET

exceeds 160°C (typical). Thermal shutdown hysteresis assures that the LDO again resets (turns on) when the

temperature falls to 140°C (typical). The thermal time-constant of the semiconductor die is fairly short, and thus

the output turns on and off at a high rate when thermal shutdown is reached until power dissipation is reduced.

The internal protection circuitry of the TPS7A92 is designed to protect against thermal overload conditions. The

circuitry is not intended to replace proper heat sinking. Continuously running the TPS7A92 into thermal shutdown

degrades device reliability.

For reliable operation, limit junction temperature to a maximum of 125°C. To estimate the thermal margin in a

given layout, increase the ambient temperature until the thermal protection shutdown is triggered using worst-

case load and highest input voltage conditions. For good reliability, thermal shutdown must occur at least 35°C

above the maximum expected ambient temperature condition for the application. This configuration produces a

worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.

TPS7A92

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

www.ti.com.cn

7.4 Device Functional Modes

表 1 provides a quick comparison between the normal, dropout, and disabled modes of operation.

表 1. Device Functional Modes Comparison

PARAMETER

OPERATING MODE

V_IN

I_OUT

I_OUT< I_CL

—

T_J

T_J< T_sd

Normal⁽¹⁾

Dropout⁽¹⁾

Disabled⁽²⁾

V_IN> V_OUT(nom)+ V_DO

V_IN< V_OUT(nom)+ V_DO

V_IN< V_UVLO

V_EN> V_IH(EN)

V_EN< V_IL(EN)

T_J< T_sd

T_J> T_sd

(1) All table conditions must be met.

(2) The device is disabled when any condition is met.

7.4.1 Normal Operation

The device regulates to the nominal output voltage when all of the following conditions are met.

•

The input voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO)

The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased

below the enable falling threshold

•

The output current is less than the current limit (I_OUT< I_CL

The device junction temperature is less than the thermal shutdown temperature (T_J< T_sd)

)

7.4.2 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout. In this mode, the output voltage tracks

the input voltage. During this mode, the transient performance of the device becomes significantly degraded

because the pass device is in a triode state and no longer controls the current through the LDO. Line or load

transients in dropout can result in large output-voltage deviations.

When the device is in a steady dropout state (defined as when the device is in dropout, V_IN< V_OUT(NOM)+ V_DO

right after being in a normal regulation state, but not during startup), the pass-FET is driven as hard as possible.

When the input voltage returns to V_IN≥ V_OUT(NOM)+ V_DO, V_OUTcan overshoot for a short period of time if the input

voltage slew rate is greater than 0.1 V/µs.

7.4.3 Disabled

The output of the TPS7A92 can be shutdown by forcing the enable pin below 0.4 V. When disabled, the pass

device is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an

internal resistor from the output to ground.

TPS7A92

www.ti.com.cn

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS7A92 is a linear voltage regulator operating from 1.4 V to 6.5 V on the input and regulates voltages

between 0.8 V to 5.0 V within 1% accuracy and a 2-A maximum output current. Efficiency is defined by the ratio

of output voltage to input voltage because the TPS7A92 is a linear voltage regulator. To achieve high efficiency,

the dropout voltage (V_IN– V_OUT) must be as small as possible, thus requiring a very low dropout LDO.

Successfully implementing an LDO in an application depends on the application requirements. This section

discusses key device features and how to best implement them to achieve a reliable design.

8.1.1 Adjustable Output

The output voltage of the TPS7A9201 can be adjusted from 0.8 V to 5.2 V by using a resistor divider network as

shown in 图 38.

V_IN

V_OUT

C_OUT

OUT

R₁

C_IN

SS_CTRL

R₂

NR/SS

C_NR/SS

GND

图 38. Adjustable Operation

R₁and R₂can be calculated for any output voltage range using 公式 3. This resistive network must provide a

current greater than or equal to 5 μA for optimum noise performance.

V_REF(max)

≈

∆

’

V_OUT

V_REF

R₁= R ₂

-1 , where

> 5 mA

R ₂

◊

(3)

If greater voltage accuracy is required, take into account the output voltage offset contribution resulting from the

feedback pin current (I_FB) and use 0.1%-tolerance resistors.

表 2 lists the resistor combination required to achieve a few of the most common rails using commercially-

available, 0.1%-tolerance resistors to maximize nominal voltage accuracy and also abiding to the formula given

in 公式 3.

TPS7A92

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

www.ti.com.cn

Application Information (接下页)

表 2. Recommended Feedback-Resistor Values

(1)

FEEDBACK RESISTOR VALUES

V_OUT(TARGET)

(V)

CALCULATED OUTPUT

VOLTAGE (V)

R₁(kΩ)

Short

2.55

5.9

R₂(kΩ)

Open

10.2

11.8

10.7

1.5

0.8

0.800

1.000

1.200

1.496

1.797

1.899

2.490

2.998

3.283

5.00

1.00

1.20

1.50

1.80

1.90

2.50

3.00

3.30

5.00

9.31

1.87

15.8

2.43

3.16

3.57

10.5

11.5

1.15

(1) R₁is connected from OUT to FB; R₂is connected from FB to GND; see 图 38.

8.1.2 Start-Up

8.1.2.1 Enable (EN) and Undervoltage Lockout (UVLO)

The TPS7A92 only turns on when EN and UVLO are above the respective voltage thresholds. The TPS7A92 has

an independent UVLO circuit that monitors the input voltage to allow a controlled and consistent turn on and off.

The UVLO has approximately 290 mV of hysteresis to prevent the device from turning off if the input drops

during turn on. The EN signal allows independent logic-level turn-on and shutdown of the LDO when the input

voltage is present. Connecting EN directly to IN is recommended if independent turn-on is not needed.

The TPS7A92 has an internal pulldown MOSFET that connects a discharge resistor from V_OUTto ground when

the device is disabled to actively discharge the output voltage.

8.1.2.2 Noise-Reduction and Soft-Start Capacitor (C_NR/SS

)

The C_NR/SScapacitor serves a dual purpose of both reducing output noise and setting the soft-start ramp during

turn-on.

8.1.2.2.1 Noise Reduction

For low-noise applications, the C_NR/SScapacitor forms an RC filter for filtering output noise that is otherwise

amplified by the control loop. For low-noise applications, a C_NR/SSof between 10 nF to 10 µF is recommended.

Larger values for C_NR/SScan be used; however, above 1 µF there is little benefit in lowering the output voltage

noise for frequencies above 10 Hz.

8.1.2.2.2 Soft-Start and Inrush Current

Soft-start refers to the gradual ramp-up characteristic of the output voltage after the EN and UVLO thresholds are

exceeded. Reducing how quickly the output voltage increases during startup also reduces the amount of current

needed to charge the output capacitor, referred to as inrush current. Inrush current is defined as the current

going into the LDO during start-up. Inrush current consists of the load current, the current used to charge the

output capacitor, and the ground pin current (that contributes very little to inrush current). This current is difficult

to measure because the input capacitor must be removed, which is not recommended. However, the inrush

current can be estimated by 公式 4:

≈

∆

’

◊

_OUTì dV_OUT(t)

V_OUT(t)

R_LOAD

≈

’

I_OUT(t) =

∆

◊

where:

•

V_OUT(t) is the instantaneous output voltage of the turn-on ramp

dV_OUT(t)/dt is the slope of the V_OUTramp and

R_LOADis the resistive load impedance

(4)

TPS7A92

www.ti.com.cn

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

The TPS7A92 features a monotonic, voltage-controlled soft-start that is set by the user with an external capacitor

(C_NR/SS). This soft-start helps reduce inrush current, minimizing load transients to the input power bus that can

cause potential start-up initialization problems when powering FPGAs, digital signal processors (DSPs), or other

high current loads.

To achieve a monotonic start-up, the TPS7A92 error amplifier tracks the voltage ramp of the external soft-start

capacitor until the voltage exceeds approximately 97% of the internal reference. The final 3% of V_NR/SSis

charged through the noise-reduction resistor (R_NR), creating an RC delay. R_NRis approximately 280 kΩ and

applications that require the highest accuracy when using a large value C_NR/SSmust take this RC delay into

account.

The soft-start ramp time depends on the soft-start charging current (I_NR/SS), the soft-start capacitance (C_NR/SS),

and the internal reference (V_REF). The approximate soft-start ramp time (t_SS) can be calculated with 公式 5:

t_SS= (V_REF× C_NR/SS) / I_NR/SS

(5)

The value for I_NR/SSis determined by the state of the SS_CTRL pin. When the SS_CTRL pin is connected to

GND, the typical value for the I_NR/SScurrent is 6.2 µA. Connecting the SS_CTRL pin to IN increases the typical

soft-start charging current to 100 µA. The larger charging current for I_NR/SSis useful if shorter start-up times are

needed (such as when using a large noise-reduction capacitor).

8.1.3 Capacitor Recommendation

The TPS7A92 is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the

input, output, and noise-reduction pin. Multilayer ceramic capacitors have become the industry standard for these

types of applications and are recommended, but must be used with good understanding of their limitations.

Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good

capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged precisely

because the capacitance varies so widely. In all cases, ceramic capacitors vary a great deal with operating

voltage and temperature and the design engineer must be aware of these characteristics. As a rule of thumb,

ceramic capacitors are recommended to be derated by 50%. The input and output capacitors recommended

herein account for a capacitance derating of 50%.

8.1.3.1 Input and Output Capacitor Requirements (C_INand C_OUT

)

The TPS7A92 is designed and characterized for operation with ceramic capacitors of 10 µF or greater at the

input and 22 µF or greater at the output. Locate the input and output capacitors as near as practical to the input

and output pins to minimize the trace inductance from the capacitor to the device.

Attention must be given to the input capacitance to minimize transient input droop during startup and load current

steps. Simply using very large ceramic input capacitances can cause unwanted ringing at the output if the input

capacitor (in combination with the wire-lead inductance) creates a high-Q peaking effect during transients, which

is why short, well-designed interconnect traces to the upstream supply are needed to minimize ringing. Damping

of unwanted ringing can be accomplished by using a tantalum capacitor, with a few hundred milliohms of ESR, in

parallel with the ceramic input capacitor. The UVLO circuit responds quickly to glitches on V_INand disables the

output of the device if this rail starts to collapse too quickly. Use an input capacitor that is large enough to slow

input transients to less then two volts per microsecond.

8.1.3.1.1 Load-Step Transient Response

The load-step transient response is the output voltage response by the LDO to a step change in load current.

The depth of charge depletion immediately after the load step is directly proportional to the amount of output

capacitance. However, although larger output capacitances decrease any voltage dip or peak occurring during a

load step, the control-loop bandwidth is also decreased, thereby slowing the response time.

The LDO cannot sink charge, therefore when the output load is removed or greatly reduced, the control loop

must turn off the pass-FET and wait for any excess charge to deplete.

8.1.3.2 Feed-Forward Capacitor (C_FF)

Although a feed-forward capacitor (C_FF), from the FB pin to the OUT pin is not required to achieve stability, a

10-nF, feed-forward capacitor improves the noise and PSRR performance. A higher capacitance C_FFcan be

used; however, the startup time is longer and the power-good signal can incorrectly indicate that the output

voltage has settled. For a detailed description, see the Pros and Cons of Using a Feedforward Capacitor with a

Low-Dropout Regulator application report.

TPS7A92

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

www.ti.com.cn

8.1.4 Power Dissipation (P_D)

Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit

on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator

must be as free as possible of other heat-generating devices that cause added thermal stresses.

To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference

and load conditions. P_Dcan be calculated using 公式 6:

P_D= (V_IN– V_OUT) × I_OUT

(6)

An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper

selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage necessary

for proper output regulation.

The primary heat conduction path for the DSK package is through the thermal pad to the PCB. Solder the

thermal pad to a copper pad area under the device. This pad area should contain an array of plated vias that

conduct heat to additional copper planes for increased heat dissipation.

The maximum power dissipation determines the maximum allowable ambient temperature (T_A) for the device.

Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance

(R_θJA) of the combined PCB and device package and the temperature of the ambient air (T_A), according to 公式

T_J= T_A+ (R_θJA× P_D)

(7)

Unfortunately, the thermal resistance (θ_JA) is highly dependent on the heat-spreading capability built into the

particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the

planes. The R_θJArecorded in the Thermal Information table is determined by the JEDEC standard, PCB, and

copper-spreading area and is only used as a relative measure of package thermal performance.

8.1.5 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal

resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics

are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JTand

Ψ_JB) are given in the Thermal Information table and are used in accordance with 公式 8.

Y_JT: T_J= T_T+ Y_JT´ P_D

Y_JB: T_J= T_B+ Y_JB´ P_D

where:

•

P_Dis the power dissipated as explained in 公式 6

T_Tis the temperature at the center-top of the device package and

T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

(8)

For a more detailed discussion on thermal metrics and how to use them, see the Semiconductor and IC Package

Thermal Metrics application report.

TPS7A92

www.ti.com.cn

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

8.2 Typical Application

This section discusses the implementation of the TPS7A92 to regulate from a 2-V input voltage to a 1.2-V output

voltages for noise-sensitive loads. The schematic for this application circuit is provided in 图 39.

2.0 V

OUT

1.2 V

C_OUT

22 ꢀF

C_IN

22 mF

R₁5.9 kW

SS_CTRL

NR/SS

C_FF10 nF

V_OUT

R₂

11.8 kW

C_NR/SS

100 nF

R_PG

20 kW

GND

图 39. Application Example

8.2.1 Design Requirements

For the design example shown in 图 39, use the parameters listed in 表 3 as the input parameters.

表 3. Design Parameters

PARAMETER

APPLICATION REQUIREMENTS

DESIGN RESULTS

2 V, ±3%, provided by the dc-dc converter

switching at 700 kHz

Input voltages (V_IN

)

1.4 V to 6.5 V

Maximum ambient operating

temperature

55°C

124°C junction temperature

Output voltages (V_OUT

)

1.2 V, ±1%

Output currents (I_OUT

)

1.5 A (max), 50 mA (min)

2.0 A (max), 5 mA (min)

4.8 µV_RMS, bandwidth = 10 Hz to 100 kHz

42 dB

RMS noise

< 5 µV_RMS, bandwidth = 10 Hz to 100 kHz

PSRR at 700 kHz

Startup time

> 40 dB

< 2 ms

800 µs (typ) 1.48 µs (max)

8.2.2 Detailed Design Procedure

The output voltage can be set to 1.2 V by selecting the correct values for R₁and R₂; see 公式 3.

Input and output capacitors are selected in accordance with the Capacitor Recommendation section. Ceramic

capacitances of 22 µF for both input and output are selected to help balance the charge needed during startup

when charging the output capacitor, thus reducing the input voltage drop.

To satisfy the required startup time (t_SS) and still maintain low-noise performance, a 0.1-µF C_NR/SSis selected for

with SS_CTRL connected to V_IN. This value is calculated with 公式 9. Using the I_NR/SS(MAX)and the smallest

C_NR/SScapacitance resulting from manufacturing variance (often ±20%) provides the fastest startup time,

whereas using the I_NR/SS(MIN)and the largest C_NR/SScapacitance resulting from manufacturing variance provides

the slowest startup time.

t_SS= (V_REF× C_NR/SS) / I_NR/SS

(9)

With a 1.5-A maximum load, the internal power dissipation is 1.2 W, corresponding to a 91°C junction

temperature rise. With a 55°C maximum ambient temperature, the junction temperature is at 124°C on the

JEDEC standard high-K board. Connecting the thermal pad to more metal on the PCB than the standard JEDEC

high-K board decreases the thermal resistance to the board and causes a decrease in the junction temperature

of the device for a given power dissipation. To minimize noise, a feed-forward capacitance (C_FF) of 10 nF is

selected.

See the Layout section for an example of how to layout the TPS7A92 to achieve best PSRR and noise.

TPS7A92

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

www.ti.com.cn

8.2.3 Application Curves

C_NR

100 nF, 4.8 mV_RMS

0.5

0.2

0.1

0.05

0.02

0.01

0.005

V_IN

0.002

0.001

2.0 V

100

10k

100k

10M

100

10k

100k

10M

Frequency (Hz)

图 40. PSRR vs Frequency

图 41. Output Noise vs Frequency

9 Power Supply Recommendations

The input of the TPS7A92 is designed to operate from an input voltage range between 1.4 V and 6.5 V and with

an input capacitor of 10 µF. The input voltage range must provide adequate headroom in order for the device to

have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input

capacitors can be used to improve the output noise performance.

10 Layout

10.1 Layout Guidelines

General guidelines for linear regulator designs are to place all circuit components on the same side of the circuit

board and as near as practical to the respective LDO pin connections. Place ground return connections to the

input and output capacitors, and to the LDO ground pin as close to each other as possible, connected by a wide,

component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly

discouraged and negatively affects system performance.

10.1.1 Board Layout

To maximize the ac performance of the TPS7A92, following the layout example illustrated in 图 42 is

recommended. This layout isolates the analog ground (AGND) from the noisy power ground. Components that

must be connected to the quiet analog ground are the noise reduction capacitor (C_NR/SS) and the lower feedback

resistor (R₂). These components must have a separate connection back to the power pad of the device for

optimal output noise performance. Connect the GND pin directly to the thermal pad and not to any external

plane.

To maximize the output voltage accuracy, the connection from the output voltage back to top output divider

resistors (R₁) must be made as close as possible to the load. This method of connecting the feedback trace

eliminates the voltage drop from the device output to the load.

To improve thermal performance, use an array of thermal vias to connect the thermal pad to the ground planes.

Larger ground planes improve the thermal performance of the device and lowering the operating temperature of

the device.

TPS7A92

www.ti.com.cn

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

10.2 Layout Example

Power Ground

Plane

C_OUT

C_IN

OUT

V_OUT

V_IN

C_FF

R₁

GND

NR/SS

C_NR/SS

R₂

To V_IN

SS_CTRL

To PG

Pullup Supply

Ground Plane for

Thermal Relief and

Signal Ground

PG Output

Denotes vias used for application purposes

图 42. TPS7A92 Example Layout

TPS7A92

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

www.ti.com.cn

11 器件和文档支持

11.1 器件支持

11.1.1 开发支持

11.1.1.1 评估模块

我们提供了一款评估模块 (EVM)，可与 TPS7A92 配套使用，帮助评估初始电路性能。表 4 显示了此装置的摘要信

息。

表 4. 设计套件与评估模块⁽¹⁾

名称

部件号

TPS7A92 低压降稳压器评估模块

TPS7A92EVM-776

(1) 欲获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者访问 www.ti.com.cn 查看器件产品文件夹。

可在德州仪器 (TI) 网站 (www.ti.com.cn) 上的 TPS7A92 产品文件夹下申请获取该 EVM。

11.1.1.2 Spice 模型

分析模拟电路和系统的性能时，使用 spice 模型对电路性能进行计算机仿真非常有用。可从 TPS7A92 产品文件夹

中的仿真模型下申请获取 TPS7A92 的 Spice 模型。

11.1.2 器件命名规则

表 5. 订购信息⁽¹⁾

产品

说明

YYY 为封装标识符。

TPS7A92xxYYYZ

XX 表示输出电压。01 为可调输出版本。

Z 为封装数量。

(1) 欲获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者访问 www.ti.com.cn 查看器件产品文件夹。

11.2 文档支持

11.2.1 相关文档

德州仪器 (TI)，《TPS37xx 双通道、低功耗、高精度电压检测器》数据表

德州仪器 (TI)，《TPS7A88 评估模块》用户指南

德州仪器 (TI)，《使用前馈电容器和低压降稳压器的优缺点》应用报告

德州仪器 (TI)，《如何测量 LDO 噪声》白皮书

11.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

TPS7A92

www.ti.com.cn

ZHCSGF3B –JULY 2017–REVISED JANUARY 2019

11.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.7 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS7A9201DSKR

TPS7A9201DSKT

ACTIVE

SON

DSK

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

1CFP

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7A9201DSKR

TPS7A9201DSKT

SON

DSK

3000

250

178.0

8.4

2.75

0.95

4.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS7A9201DSKR

TPS7A9201DSKT

SON

DSK

3000

250

205.0

200.0

33.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

DSK 10

2.5 x 2.5 mm, 0.5 mm pitch

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225304/A

PACKAGE OUTLINE

DSK0010A

WSON - 0.8 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

2.6

2.4

PIN 1 INDEX AREA

2.6

2.4

0.8

0.7

SEATING PLANE

0.08 C

0.05

0.00

(0.2) TYP

EXPOSED

THERMAL PAD

1.2 0.1

0.1

8X 0.5

0.3

10X

0.45

0.35

0.2

0.1

0.05

10X

PIN 1 ID

(OPTIONAL)

C A B

4218903/B 10/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DSK0010A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

10X (0.6)

(1.2)

10X (0.25)

SYMM

(2)

8X (0.5)

(0.75)

(R0.05) TYP

(0.35)

(

0.2) VIA

TYP

SYMM

(2.3)

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218903/B 10/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.

www.ti.com

EXAMPLE STENCIL DESIGN

DSK0010A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

10X (0.6)

SYMM

METAL

TYP

10X (0.25)

SYMM

8X (0.5)

(0.89)

(R0.05) TYP

(1.13)

(2.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 11

84% PRINTED SOLDER COVERAGE BY AREA

SCALE:20X

4218903/B 10/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS7A9201DSKT相关文章

配单直通车

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

深圳市中利达电子科技有限公司服务专线: 0755-13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

柒号芯城电子商务（深圳）有限公司服务专线: 18922803401 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

TPS7A9201DSKT产品参数

型号:	TPS7A9201DSKT
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
包装说明：	HVSON,
Reach Compliance Code：	compliant
Factory Lead Time：	1 week
风险等级：	1.63
可调性：	ADJUSTABLE
最大回动电压 1：	0.4 V
标称回动电压 1：	0.26 V
最大输入电压：	6.5 V
JESD-30 代码：	S-PDSO-N10
JESD-609代码：	e4
长度：	2.5 mm
湿度敏感等级：	2
功能数量：	1
输出次数：	1
端子数量：	10
工作温度TJ-Max：	125 °C
工作温度TJ-Min：	-40 °C
最大输出电流 1：	2 A
最大输出电压 1：	5.252 V
最小输出电压 1：	0.792 V
封装主体材料：	PLASTIC/EPOXY
封装代码：	HVSON
封装形状：	SQUARE
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED
调节器类型：	ADJUSTABLE POSITIVE SINGLE OUTPUT LDO REGULATOR
座面最大高度：	0.8 mm
表面贴装：	YES
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	2.5 mm
Base Number Matches：	1

电子百科

产品导航

产品型号TPS7A9201DSKT的概述

产品型号TPS7A9201DSKT的Datasheet PDF文件预览

TPS7A9201DSKT相关产品..

TPS7A9201DSKT相关文章

IC37:专业IC行业平台