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产品型号UCC27211DRMR的概述

UCC27211DRMR芯片概述 UCC27211DRMR是一款高性能的驱动器芯片,主要用于推动功率MOSFET和IGBT等开关器件。它是美国德州仪器(Texas Instruments)公司推出的优质产品之一,广泛应用于各种开关电源、变频器和电机驱动等领域。该芯片具有高驱动能力、快速上升和下降时间、低功耗以及能够在恶劣工作条件下稳定运行的显著特点。 UCC27211DRMR的设计旨在解决现代电源管理系统中对开关速度和驱动能力逐渐提高的需求。其独特的控制架构能够实现高达4A的输出驱动电流,配合小至20ns的边缘速度,确保系统在较高频率下有效工作。该芯片的设计还考虑到了诸如电压抖动、开关噪声和EMI(电磁干扰)等诸多因素,使其在高效能输出与信号完整性之间取得了良好的平衡。 UCC27211DRMR详细参数 ### 主要电气特性 1. 供电电压:该芯片支持的工作电压范围为4.5V到13.5...

产品型号UCC27211DRMR的Datasheet PDF文件预览

UCC27210  
UCC27211  
www.ti.com  
SLUSAT7B NOVEMBER 2011REVISED FEBRUARY 2012  
120-V Boot, 4-A Peak, High Frequency High-Side/Low-Side Driver  
Check for Samples: UCC27210, UCC27211  
1
FEATURES  
APPLICATIONS  
2
Drives Two N-Channel MOSFETs in  
Power Supplies for Telecom, Datacom, and  
High-Side/Low-Side Configuration with  
Independent Inputs  
Merchant  
Half-Bridge and Full-Bridge Converters  
Push-Pull Converters  
Maximum Boot Voltage 120-V DC  
4-A Sink, 4-A Source Output Currents  
0.9-Ω Pull-Up/Pull-Down Resistance  
High Voltage Synchronous-Buck Converters  
Two-Switch Forward Converters  
Active-Clamp Forward Converters  
Class-D Audio Amplifiers  
Input Pins can Tolerate -10 V to 20 V and are  
Independent of Supply Voltage Range  
TTL or Pseudo-CMOS Compatible Input  
Versions  
DESCRIPTION  
8-V to 17-V VDD Operating Range, (20 V ABS  
MAX)  
The UCC27210 and UCC27211 Drivers are based on  
the popular UCC27200 and UCC27201 MOSFET  
drivers, but offer several significant performance  
improvements. Peak output pull-up and pull-down  
current has been increased to 4-A source/4-A sink,  
and pull-up/pull-down resistance have been reduced  
to 0.9 Ω, thereby allowing for driving large power  
MOSFETs with minimized switching losses during the  
transition through the MOSFETs Miller Plateau. The  
input structure is now able to directly handle -10  
VDC, which increases robustness and also allows  
direct interface to gate-drive transformers without  
using rectification diodes. The inputs are also  
independent of supply voltage and have a 20-V  
maximum rating.  
7.2-ns Rise and 5.5-ns Fall Time with 1000-pF  
Load  
Fast Propagation Delay Times (18 ns typical)  
2-ns Delay Matching  
Symmetrical Under Voltage Lockout for  
High-Side and Low-Side Driver  
All Industry Standard Packages Available  
(SOIC-8, PowerPADSOIC-8, 4-mm x 4-mm  
SON-8 and 4-mm x 4-mm SON-10)  
Specified from -40 to 140 °C  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
PowerPAD is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 20112012, Texas Instruments Incorporated  
UCC27210  
UCC27211  
SLUSAT7B NOVEMBER 2011REVISED FEBRUARY 2012  
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
DESCRIPTION (CONT.)  
The UCC27210/1s switching node (HS pin) is able to handle -18 V maximum which allows the high-side channel  
to be protected from inherent negative voltages caused parasitic inductance and stray capacitance. The  
UCC27210 (Pseudo-CMOS inputs) and UCC27211 (TTL inputs) have increased hysteresis allowing for interface  
to analog or digital PWM controllers with enhanced noise immunity.  
The low-side and high-side gate drivers are independently controlled and matched to 2 ns between the turn on  
and turn off of each other.  
An on-chip 120-V rated bootstrap diode eliminates the external discrete diodes. Under-voltage lockout is  
provided for both the high-side and the low-side drivers providing symmetric turn-on/turn-off behavior and forcing  
the outputs low if the drive voltage is below the specified threshold.  
Both devices are offered in 8-pin SOIC (D), PowerPADSOIC-8 (DDA), 4-mm x 4-mm SON-8 (DRM) and  
SON-10 (DPR) packages.  
Typical Application Diagrams  
+12V  
+12V  
+100V  
SECONDARY  
SIDE  
SECONDARY  
SIDE  
VDD  
+100V  
VDD  
CIRCUIT  
HB  
CIRCUIT  
HB  
HI  
LI  
DRIVE  
HI  
HO  
HS  
HI  
LI  
DRIVE  
HI  
HO  
HS  
PWM  
CONTROLLER  
PWM  
CONTROLLER  
LO  
DRIVE  
LO  
LO  
DRIVE  
LO  
UCC27211  
UCC27210  
VSS  
VSS  
ISOLATION  
AND  
FEEDBACK  
+12V  
VDD  
+100V  
HB  
HI  
LI  
DRIVE  
HI  
HO  
HS  
LO  
DRIVE  
LO  
UCC27211  
(1)  
ORDERING INFORMATION  
PACKAGED DEVICES(1)  
INPUT  
COMPATIBILITY  
TEMPERATURE RANGE TA = TJ  
PowerPAD  
SOIC-8 (D)(2)  
SON-8 (DRM)(3) SON-10 (DPR)(4)  
SOIC-8 (DDA)(2)  
Pseudo CMOS  
TTL  
UCC27210D  
UCC27211D  
UCC27210DDA  
UCC27211DDA  
UCC27210DRM  
UCC27211DRM  
UCC27210DPR  
UCC27211DPR  
-40°C to 140°C  
(1) These products are packaged in Lead (Pb)-Free and green lead finish of PdNiAu which is compatible with MSL level 1 at 255°C to  
260°C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.  
(2) D (SOIC-8) and DDA (Power PadSOIC-8) packages are available taped and reeled. Add R suffix to device type (e.g.  
UCC27210ADR/UCC27211ADR) to order quantities of 2,500 devices per reel.  
(3) DRM (SON-8) package comes either in a small reel of 250 pieces as part number UCC27210ADRMT/UCC27211ADRMT, or larger reels  
of 3000 pieces as part number UCC27210ADRMR/UCC27211ADRMR.  
(4) DPR (SON-10) package comes either in a small reel of 250 pieces as part number UCC27210ADPRT/UCC27211ADPRT, or large reels  
of 3000 pieces as part number UCC27210ADPRR/UCC27211ADPRR.  
2
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UCC27210  
UCC27211  
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SLUSAT7B NOVEMBER 2011REVISED FEBRUARY 2012  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range (unless otherwise noted)  
MIN  
MAX  
UNIT  
Supply voltage range, VDD(1), VHB - VHS  
Input voltages on LI and HI, VLI, VHI  
-0.3  
-10  
-0.3  
-2  
20  
20  
DC  
Output voltage on LO, VLO  
VDD + 0.3  
VDD + 0.3  
VHB + 0.3  
VHB + 0.3  
115  
Repetitive pulse <100 ns(2)  
DC  
Output voltage on HO, VHO  
V
HS 0.3  
VHS - 2  
-1  
V
Repetitive pulse <100 ns(2)  
DC  
Voltage on HS, VHS  
Repetitive pulse <100 ns(2)  
-18  
115  
Voltage on HB, VHB  
-0.3  
120  
Human Body Model (HBM)  
2
ESD  
kV  
Field Induced Charged Device Model  
(FICDM)  
1
Operating virtual junction temperature range, TJ  
Storage temperature, TSTG  
-40  
-65  
150  
150  
300  
°C  
Lead temperature (soldering, 10 sec.)  
(1) All voltages are with respect to VSS unless otherwise noted. Currents are positive into, negative out of the specified terminal.  
(2) Verified at bench characterization.  
RECOMMENDED OPERATING CONDITIONS  
all voltages are with respect to VSS; currents are positive into and negative out of the specified terminal. 40°C < TJ = TA <  
140°C (unless otherwise noted)  
PARAMETER  
MIN  
TYP  
MAX  
UNIT  
Supply voltage range, VDD, VHB-VHS  
Voltage on HS, VHS  
8
-1  
12  
17  
105  
110  
V
Voltage on HS, VHS (repetitive pulse <100 ns)  
-15  
VHS +8,  
VHS +17,  
115  
Voltage on HB, VHB  
VDD 1  
Voltage slew rate on HS  
50  
V/ns  
Operating junction temperature range  
-40  
140  
°C  
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UCC27210  
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SLUSAT7B NOVEMBER 2011REVISED FEBRUARY 2012  
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UNITS  
THERMAL INFORMATION  
UCC27210/11(1)  
THERMAL METRIC  
D
DDA  
8 PINS  
37.7  
47.2  
9.6  
8 PINS  
111.8  
56.9  
53.0  
7.8  
θJA  
Junction-to-ambient thermal resistance(2)  
Junction-to-case (top) thermal resistance(3)  
Junction-to-board thermal resistance(4)  
θJCtop  
θJB  
°C/W  
ψJT  
Junction-to-top characterization parameter(5)  
Junction-to-board characterization parameter(6)  
Junction-to-case (bottom) thermal resistance(7)  
2.8  
ψJB  
52.3  
n/a  
9.4  
θJCbot  
3.6  
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.  
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as  
specified in JESD51-7, in an environment described in JESD51-2a.  
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific  
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.  
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB  
temperature, as described in JESD51-8.  
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted  
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).  
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted  
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).  
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific  
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.  
THERMAL INFORMATION  
UCC27210/11(1)  
THERMAL METRIC  
DRM  
8 PINS  
33.9  
33.2  
11.4  
0.4  
DPR  
10 PINS  
36.8  
UNITS  
θJA  
Junction-to-ambient thermal resistance(2)  
Junction-to-case (top) thermal resistance(3)  
Junction-to-board thermal resistance(4)  
Junction-to-top characterization parameter(5)  
Junction-to-board characterization parameter(6)  
Junction-to-case (bottom) thermal resistance(7)  
θJCtop  
θJB  
36.0  
14.0  
°C/W  
ψJT  
0.3  
ψJB  
11.7  
2.3  
14.2  
θJCbot  
3.4  
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.  
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as  
specified in JESD51-7, in an environment described in JESD51-2a.  
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific  
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.  
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB  
temperature, as described in JESD51-8.  
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted  
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).  
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted  
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).  
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific  
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.  
4
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UCC27210  
UCC27211  
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SLUSAT7B NOVEMBER 2011REVISED FEBRUARY 2012  
ELECTRICAL CHARACTERISTICS  
VDD = VHB = 12 V, VHS = VSS = 0 V, no load on LO or HO, TA = TJ = -40°C to 140°C, (unless otherwise noted)  
PARAMETER  
TEST CONDITION  
MIN  
TYP  
MAX UNITS  
Supply Currents  
IDD  
VDD quiescent current  
V(LI) = V(HI) = 0 V  
0.05  
2.4  
0.085  
2.6  
0.17  
4.3  
IDDO  
UCC27210  
UCC27211  
VDD operating current  
f = 500 kHz, CLOAD = 0  
2.4  
2.5  
4.3  
0.1  
4
mA  
IHB  
Boot voltage quiescent current  
Boot voltage operating current  
HB to VSS quiescent current  
HB to VSS operating current  
V(LI) = V(HI) = 0 V  
0.015  
1.5  
0.065  
2.5  
IHBO  
IHBS  
IHBSO  
Input  
VHIT  
VLIT  
VIHYS  
RIN  
f = 500 kHz, CLOAD = 0  
V(HS) = V(HB) = 115 V  
f = 500 kHz, CLOAD = 0  
0.0005  
0.07  
0.13  
0.9  
µA  
mA  
Input voltage threshold  
Input voltage threshold  
Input voltage hysteresis  
Input pulldown resistance  
Input voltage threshold  
Input voltage threshold  
Input voltage hysteresis  
Input pulldown resistance  
4.2  
2.4  
5.0  
3.2  
1.8  
102  
2.3  
1.6  
700  
68  
5.8  
4.0  
V
UCC27210  
UCC27211  
kΩ  
VHIT  
VLIT  
VIHYS  
RIN  
1.9  
1.3  
2.7  
1.9  
V
mV  
kΩ  
Under-Voltage Lockout (UVLO)  
VDDR VDD turn-on threshold  
VDDHYS Hysteresis  
6.2  
5.6  
7.0  
0.5  
6.7  
1.1  
7.8  
7.9  
V
VHBR  
VHB turn-on threshold  
VHBHYS Hysteresis  
Bootstrap Diode  
VF  
Low-current forward voltage  
IVDD-HB = 100 µA  
0.65  
0.85  
0.5  
0.8  
0.95  
0.85  
V
VFI  
RD  
High-current forward voltage  
IVDD-HB = 100 mA  
Dynamic resistance, ΔVF/ΔI  
IVDD-HB = 100 mA and 80 mA  
0.3  
Ω
LO Gate Driver  
VLOL  
VLOH  
Low-level output voltage  
ILO = 100 mA  
0.05  
0.1  
0.09  
0.16  
3.7  
0.15  
0.27  
V
A
High level output voltage  
Peak pull-up current(1)  
Peak pull-down current(1)  
ILO = -100 mA, VLOH = VDD - VLO  
VLO = 0 V  
VLO = 12 V  
4.5  
HO GATE Driver  
VHOL  
VHOH  
Low-level output voltage  
IHO = 100 mA  
0.05  
0.1  
0.09  
0.16  
3.7  
0.15  
0.27  
V
A
High-level output voltage  
Peak pull-up current(1)  
Peak pull-down current(1)  
IHO = -100 mA, VHOH = VHB - VHO  
VHO = 0 V  
VHO = 12 V  
4.5  
(1) Ensured by design.  
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SLUSAT7B NOVEMBER 2011REVISED FEBRUARY 2012  
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ELECTRICAL CHARACTERISTICS (continued)  
VDD = VHB = 12 V, VHS = VSS = 0 V, no load on LO or HO, TA = TJ = -40°C to 140°C, (unless otherwise noted)  
PARAMETER  
TEST CONDITION  
MIN  
TYP  
MAX UNITS  
Switching Parameters: Propagation Delays  
TDLFF  
TDHFF  
TDLRR  
TDHRR  
TDLFF  
TDHFF  
TDLRR  
TDHRR  
VLI falling to VLO falling  
VHI falling to VHO falling  
VLI rising to VLO rising  
VHI rising to VHO rising  
VLI falling to VLO falling  
VHI falling to VHO falling  
VLI rising to VLO rising  
VHI rising to VHO rising  
17  
17  
18  
18  
10  
10  
10  
10  
21  
21  
24  
24  
17  
17  
18  
18  
37  
37  
46  
UCC27210, CLOAD = 0  
46  
ns  
30  
30  
40  
40  
UCC27211, CLOAD = 0  
Switching Parameters: Delay Matching  
TJ = 25°C  
3
3
3
3
2
2
2
2
11  
ns  
14  
TMON  
TMOFF  
TMON  
TMOFF  
From HO OFF to LO ON  
From LO OFF to HO ON  
From HO OFF to LO ON  
From LO OFF to HO ON  
TJ = 40°C to 140°C  
TJ = 25°C  
UCC27210  
UCC27211  
11  
ns  
14  
TJ = 40°C to 140°C  
TJ = 25°C  
9.5  
ns  
TJ = 40°C to 140°C  
TJ = 25°C  
14  
9.5  
ns  
TJ = 40°C to 140°C  
14  
Switching Parameters: Output Rise and Fall Time  
tR  
tR  
tF  
tF  
tR  
tF  
LO rise time  
HO rise time  
LO fall time  
HO fall time  
LO, HO  
7.2  
7.2  
CLOAD = 1000 pF, from 10% to 90%  
CLOAD = 1000 pF, from 90% to 10%  
ns  
5.5  
5.5  
CLOAD = 0.1 µF, (3 V to 9 V)  
CLOAD = 0.1 µF, (9 V to 3 V)  
0.36  
0.15  
0.6  
µs  
LO, HO  
0.4  
Switching Parameters: Miscellaneous  
Minimum input pulse width that changes the  
output  
Bootstrap diode turn-off time(2)(3)  
50  
ns  
IF = 20 mA, IREV = 0.5 A(4)  
20  
(2) Ensured by design.  
(3) IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode.  
(4) Typical values for TA = 25°C.  
6
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SLUSAT7B NOVEMBER 2011REVISED FEBRUARY 2012  
Timing Diagrams  
LI  
Input  
HI  
(HI, LI)  
TDLRR, TDHRR  
LO  
Output  
(HO, LO)  
TDLFF, TDHFF  
HO  
TMON  
TMOFF  
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UCC27211  
SLUSAT7B NOVEMBER 2011REVISED FEBRUARY 2012  
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DEVICE INFORMATION  
Functional Block Diagram  
2
HB  
UVLO  
3
4
HO  
HS  
LEVEL  
SHIFT  
5
HI  
1
VDD  
UVLO  
LO  
8
7
6
VSS  
LI  
Power PadTM SOIC-8 (DDA)  
TOP VIEW  
SOIC-8 (D)  
TOP VIEW  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
LO  
VDD  
HB  
LO  
VSS  
LI  
VDD  
HB  
Exposed  
Thermal  
Die Pad  
VSS  
LI  
HO  
HS  
HO  
HS  
HI  
HI  
SON-10 (DPR)  
TOP VIEW  
SON-8 (DRM)  
TOP VIEW  
1
8
LO  
1
2
3
4
5
10  
9
VDD  
HB  
LO  
VDD  
HB  
Exposed  
Thermal  
Die Pad*  
VSS  
2
3
4
7
6
VSS  
8
HO  
HS  
LI  
LI  
HO  
HS  
7
HI  
NC  
5
HI  
6
NC  
8
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SLUSAT7B NOVEMBER 2011REVISED FEBRUARY 2012  
TERMINAL FUNCTIONS  
PIN  
PIN NAME  
DESCRIPTION  
D/DDA/DRM  
DPR  
Positive supply to the lower-gate driver. De-couple this pin to VSS (GND). Typical  
decoupling capacitor range is 0.22 µF to 1.0 µF.  
VDD  
HB  
1
1
High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap  
capacitor is required. Connect positive side of the bootstrap capacitor to this pin.  
Typical range of HB bypass capacitor is 0.022 µF to 0.1 µF. The capacitor value is  
dependant on the gate charge of the high-side MOSFET and should also be selected  
based on speed and ripple criteria  
2
2
HO  
HS  
3
4
3
4
High-side output. Connect to the gate of the high-side power MOSFET.  
High-side source connection. Connect to source of high-side power MOSFET.  
Connect the negative side of bootstrap capacitor to this pin.  
HI  
LI  
5
6
7
8
-
7
8
High-side input.  
Low-side input.  
VSS  
LO  
9
Negative supply terminal for the device which is generally grounded.  
Low-side output. Connect to the gate of the low-side power MOSFET.  
Not Connected.  
10  
5/6  
N/C  
Utilized on the DDA, DRM and DPR packages only. Electrically referenced to VSS  
(GND). Connect to a large thermal mass trace or GND plane to dramatically improve  
thermal performance.  
PowerPAD(1)  
Pad  
Pad  
(1) The PowerPADis not directly connected to any leads of the package. However it is electrically and thermally connected to the  
substrate which is the ground of the device.  
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UCC27210  
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SLUSAT7B NOVEMBER 2011REVISED FEBRUARY 2012  
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TYPICAL CHARACTERISTICS  
QUIESCENT CURRENT  
UCC27210 IDD OPERATING CURRENT  
vs  
vs  
SUPPLY VOLTAGE  
FREQUENCY  
100  
80  
60  
40  
20  
0
100  
10  
UCC27210, VDD = 12V  
T = 25°C  
1
CL=0pF, T=−40°C  
CL=0pF, T=25°C  
CL=0pF, T=140°C  
CL=1000pF, T=25°C  
CL=1000pF, T=140°C  
CL=4700pF, T=140°C  
0.1  
0.01  
UCC27210/1 IDD  
UCC27210/1 IHB  
0
10  
8
2
4
6
8
10  
12  
14  
16  
18  
20  
10  
100  
1000  
Frequency (kHz)  
VDD = VHB − Supply Voltage (V)  
G001  
G002  
Figure 1.  
Figure 2.  
UCC27211 IDD OPERATING CURRENT  
BOOT VOLTAGE OPERATING CURRENT  
vs  
vs  
FREQUENCY  
FREQUENCY (HB to HS)  
100  
10  
100  
10  
UCC27211, VDD = 12V  
UCC27210/1, VHB − VHS = 12V  
1
1
CL=0pF, T=−40°C  
CL=0pF, T=25°C  
CL=0pF, T=140°C  
CL=1000pF, T=25°C  
CL=1000pF, T=140°C  
CL=4700pF, T=140°C  
CL=0pF, T=−40°C  
CL=0pF, T=25°C  
CL=0pF, T=140°C  
CL=1000pF, T=25°C  
CL=1000pF, T=140°C  
CL=4700pF, T=140°C  
0.1  
0.01  
0.1  
0.01  
100  
1000  
10  
100  
1000  
Frequency (kHz)  
Frequency (kHz)  
G003  
G004  
Figure 3.  
Figure 4.  
UCC27210/11 INPUT THRESHOLD  
UCC27210/11 INPUT THRESHOLDS  
vs  
vs  
SUPPLY VOLTAGE  
TEMPERATURE  
6
5
6
5
VDD = 12V  
T = 25°C  
4
4
3
3
2
2
1
1
UCC27210, Rising  
UCC27210, Rising  
UCC27210, Falling  
UCC27211, Rising  
UCC27211, Falling  
UCC27210, Falling  
UCC27211, Rising  
UCC27211, Falling  
0
0
−1  
−1  
12  
16  
20  
−40 −20  
0
20  
40  
60  
80  
100 120 140  
Temperature (°C)  
VDD − Supply Voltage (V)  
G005  
G006  
Figure 5.  
Figure 6.  
10  
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SLUSAT7B NOVEMBER 2011REVISED FEBRUARY 2012  
TYPICAL CHARACTERISTICS (continued)  
LO AND HO HIGH LEVEL OUTPUT VOLTAGE  
LO AND HO LOW LEVEL OUTPUT VOLTAGE  
vs  
vs  
TEMPERATURE  
TEMPERATURE  
0.32  
0.2  
0.16  
0.12  
0.08  
0.04  
0
IHO=ILO= 100mA  
IHO=ILO= 100mA  
0.28  
0.24  
0.2  
0.16  
0.12  
0.08  
0.04  
0
UCC27210/1, VDD=VHB=8V  
UCC27210/1, VDD=VHB=12V  
UCC27210/1, VDD=VHB=16V  
UCC27210/1, VDD=VHB=20V  
UCC27210/1, VDD=VHB=8V  
UCC27210/1, VDD=VHB=12V  
UCC27210/1, VDD=VHB=16V  
UCC27210/1, VDD=VHB=20V  
−40 −20  
0
20  
40  
60  
80  
100 120 140  
−40 −20  
0
20  
40  
60  
80  
100 120 140  
Temperature (°C)  
Temperature (°C)  
G007  
G008  
Figure 7.  
Figure 8.  
UNDERVOLTAGE LOCKOUT THRESHOLD  
UNDERVOLTAGE LOCKOUT THRESHOLD HYSTERESIS  
vs  
vs  
TEMPERATURE  
TEMPERATURE  
8
7.6  
7.2  
6.8  
6.4  
6
1.5  
1.2  
0.9  
0.6  
0.3  
5.6  
5.2  
VDD Rising Threshold  
HB Rising Threshold  
VDD UVLO Hysteresis  
HB UVLO Hysteresis  
0
−40 −20  
−40 −20  
0
20  
40  
60  
80  
100 120 140  
0
20  
40  
60 80 100 120 140  
Temperature (°C)  
Temperature (°C)  
G009  
G010  
Figure 9.  
Figure 10.  
UCC27210 PROPAGATION DELAYS  
UCC27211 PROPAGATION DELAYS  
vs  
vs  
TEMPERATURE  
TEMPERATURE  
40  
36  
32  
28  
24  
20  
16  
12  
8
32  
24  
16  
8
UCC27210, VDD=VHB=12V  
UCC27211, VDD=VHB=12V  
TDLRR  
TDLFF  
TDHRR  
TDHFF  
TDLRR  
TDLFF  
TDHRR  
TDHFF  
4
0
0
−40 −20  
0
20  
40  
60  
80  
100 120 140  
−40 −20  
0
20  
40  
60  
80  
100 120 140  
Temperature (°C)  
Temperature (°C)  
G011  
G012  
Figure 11.  
Figure 12.  
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UCC27210  
UCC27211  
SLUSAT7B NOVEMBER 2011REVISED FEBRUARY 2012  
www.ti.com  
TYPICAL CHARACTERISTICS (continued)  
UCC27210 PROPAGATION DELAYS  
UCC27211 PROPAGATION DELAYS  
vs  
vs  
SUPPLY VOLTAGE  
SUPPLY VOLTAGE  
32  
28  
24  
20  
16  
12  
8
32  
28  
24  
20  
16  
12  
8
UCC27210, T=25°C  
UCC27211, T=25°C  
TDLRR  
TDLFF  
TDHRR  
TDHFF  
TDLRR  
TDLFF  
TDHRR  
TDHFF  
4
4
0
0
8
12  
16  
20  
8
12  
16  
20  
VDD=VHB − Supply Voltage (V)  
VDD=VHB − Supply Voltage (V)  
G012  
G014  
Figure 13.  
Figure 14.  
DELAY MATCHING  
vs  
OUTPUT CURRENT  
vs  
TEMPERATURE  
OUTPUT VOLTAGE  
10  
8
5
4
3
2
1
0
VDD=VHB=12V  
VDD=VHB=12V  
6
4
2
UCC27210, TMon  
UCC27210, TMoff  
UCC27211, TMon  
UCC27211, TMoff  
0
Pull Down Current  
Pull Up Current  
−2  
−40 −20  
0
20  
40  
60  
80  
100 120 140  
0
2
4
6
8
10  
12  
Temperature (°C)  
VLO, VHO − Output Voltage (V)  
G015  
G016  
Figure 15.  
Figure 16.  
12  
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UCC27210  
UCC27211  
www.ti.com  
SLUSAT7B NOVEMBER 2011REVISED FEBRUARY 2012  
TYPICAL CHARACTERISTICS (continued)  
DIODE CURRENT  
vs  
DIODE VOLTAGE  
NEGATIVE 10-V INPUT  
100  
10  
1
0.1  
0.01  
0.001  
500  
550  
600  
650  
700  
750  
800  
850  
Diode Voltage (mV)  
G017  
Figure 17.  
Figure 18.  
STEP INPUT  
SYMMETRICAL UVLO  
Figure 19.  
Figure 20.  
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UCC27210  
UCC27211  
SLUSAT7B NOVEMBER 2011REVISED FEBRUARY 2012  
www.ti.com  
APPLICATION INFORMATION  
Functional Description  
The UCC27210/11 represent Texas Instrumentslatest generation of high voltage gate drivers which are  
designed to drive both the high-side and low-side of N-Channel MOSFETs in a half-/full-bridge or synchronous  
buck configuration. The floating high-side driver is capable of operating with supply voltages of up to 120 V. This  
allows for N-Channel MOSFET control in half-bridge, full-bridge, push pull, two-switch forward and active clamp  
forward converters.  
The UCC27210/11 feature 4-A source/sink capability, industry best-in-class switching characteristics and a host  
of other features listed in the table below. These features combine to ensure efficient, robust and reliable  
operation in high-frequency switching power circuits.  
Table 1. UCC27210/11 Highlights  
FEATURE  
BENEFIT  
High peak current ideal for driving large power MOSFETs with  
minimal power loss (fast-drive capability at Miller plateau)  
4-A source and sink current with 0.9-Ω output resistance  
Increased robustness and ability to handle under/overshoot. Can  
interface directly to gate-drive transformers without having to use  
rectification diodes  
Input pins (HI and LI) can directly handle -10 VDC up to 20 VDC  
120-V internal boot diode  
Provides voltage margin to meet telecom 100-V surge requirements  
Allows the high-side channel to have extra protection from inherent  
negative voltages caused parasitic inductance and stray  
capacitance.  
Switch node (HS pin) able to handle -18 V maximum for 100 ns  
Robust ESD circuitry to handle voltage spikes  
Excellent immunity to large dV/dT conditions  
Best-in-class switching characteristics and extremely low-pulse  
transmission distortion  
18-ns propagation delay with 7.2-ns / 5.5-ns rise/fall Times  
2-ns (typ) delay matching between channels  
Symmetrical UVLO circuit  
Avoids transformer volt-second offset in bridge  
Ensures high-side and low-side shut down at the same time  
CMOS optimized threshold or TTL optimized thresholds with  
increased hysteresis  
Complementary to analog or digital PWM controllers. Increased  
hysteresis offers added noise immunity  
In UCC27210/11, the high side and low side each have independent inputs which allow maximum flexibility of  
input control signals in the application. The boot diode for the high-side driver bias supply is internal to the  
UCC27210 and UCC27211. The UCC27210 is the Pseudo-CMOS compatible input version and the UCC27211  
is the TTL or logic compatible version. The high-side driver is referenced to the switch node (HS) which is  
typically the source pin of the high-side MOSFET and drain pin of the low-side MOSFET. The low-side driver is  
referenced to VSS which is typically ground. The functions contained are the input stages, UVLO protection, level  
shift, boot diode, and output driver stages.  
14  
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SLUSAT7B NOVEMBER 2011REVISED FEBRUARY 2012  
Input Stages  
The input stages provide the interface to the PWM output signals. The input impedance of the UCC27210 is 100  
kΩ nominal and input capacitance is approximately 2 pF. The 100 kΩ is a pull-down resistance to VSS (ground).  
The UCC27210 Pseudo-CMOS input structure has been designed to provide large hysteresis and at the same  
time to allows interfacing to a multitude of analog or digital PWM controllers. In some CMOS designs, the input  
thresholds are determined as a percentage of VDD. By doing so, the high-level input threshold can become  
unreasonably high and unusable. The UCC27210 recognizes the fact that VDD levels are trending downward  
and it therefore provides a rising threshold with 5.0 V (typ) and falling threshold with 3.2 V (typ). The input  
hysteresis of the UCC27210 is 1.8 V (typ).  
The input stages of the UCC27211 have impedance of 70 kΩ nominal and input capacitance is approximately 2  
pF. Pull-down resistance to VSS (ground) is 70 kΩ. The logic level compatible input provides a rising threshold of  
2.3 V and a falling threshold of 1.6 V.  
Under Voltage Lockout (UVLO)  
The bias supplies for the high-side and low-side drivers have UVLO protection. VDD as well as VHB to VHS  
differential voltages are monitored. The VDD UVLO disables both drivers when VDD is below the specified  
threshold. The rising VDD threshold is 7.0 V with 0.5-V hysteresis. The VHB UVLO disables only the high-side  
driver when the VHB to VHS differential voltage is below the specified threshold. The VHB UVLO rising threshold is  
6.7 V with 1.1-V hysteresis.  
Level Shift  
The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to  
the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides  
excellent delay matching with the low-side driver.  
Boot Diode  
The boot diode necessary to generate the high-side bias is included in the UCC27210/11 family of drivers. The  
diode anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and the  
HS pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The boot  
diode provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and  
reliable operation.  
Output Stages  
The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance and  
high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The  
low-side output stage is referenced from VDD to VSS and the high side is referenced from VHB to VHS  
.
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SLUSAT7B NOVEMBER 2011REVISED FEBRUARY 2012  
www.ti.com  
Layout Recommendations  
To improve the switching characteristics and efficiency of a design, the following layout rules should be followed.  
Locate the driver as close as possible to the MOSFETs.  
Locate the VDD and VHB (bootstrap) capacitors as close as possible to the driver.  
Pay close attention to the GND trace. Use the thermal pad of the DDA and DRM package as GND by  
connecting it to the VSS pin (GND). The GND trace from the driver goes directly to the source of the  
MOSFET but should not be in the high current path of the MOSFET(S) drain or source current.  
Use similar rules for the HS node as for GND for the high-side driver.  
Use wide traces for LO and HO closely following the associated GND or HS traces. 60 to 100-mils width is  
preferable where possible.  
Use as least two or more vias if the driver outputs or SW node needs to be routed from one layer to another.  
For GND the number of vias needs to be a consideration of the thermal pad requirements as well as parasitic  
inductance.  
Avoid LI and HI (driver input) going close to the HS node or any other high dV/dT traces that can induce  
significant noise into the relatively high impedance leads.  
Keep in mind that a poor layout can cause a significant drop in efficiency versus a good PCB layout and can  
even lead to decreased reliability of the whole system.  
Example Component Placement  
Figure 21. UCC27210/11 Component Placement  
Additional References  
These references and links to additional information may be found at www.ti.com  
Additional layout guidelines for PCB land patterns may be found in, QFN/SON PCB Attachment, Application  
Brief (Texas Instrument's Literature Number SLUA271)  
Additional thermal performance guidelines may be found in, PowerPADThermally Enhanced Package  
Application Report, Application Report (Texas Instrument's Literature Number SLMA002A)  
Additional thermal performance guidelines may be found in, PowerPADMade Easy, Application Report  
(Texas Instrument's Literature Number SLMA004)  
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UCC27211  
www.ti.com  
SLUSAT7B NOVEMBER 2011REVISED FEBRUARY 2012  
REVISION HISTORY  
Changes from Revision A (November, 2011) to Revision B  
Page  
Changed ordering information notes to reflect corrected part number. ................................................................................ 2  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
3-Feb-2012  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
UCC27210D  
UCC27210DDA  
UCC27210DDAR  
UCC27210DPRR  
UCC27210DPRT  
UCC27210DR  
ACTIVE  
SOIC  
D
8
8
75  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
PREVIEW SO PowerPAD  
PREVIEW SO PowerPAD  
DDA  
DDA  
DPR  
DPR  
D
75  
Green (RoHS  
& no Sb/Br)  
CU NIPDAUAGLevel-1-260C-UNLIM  
CU NIPDAUAGLevel-1-260C-UNLIM  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAUAGLevel-1-260C-UNLIM  
CU NIPDAUAGLevel-1-260C-UNLIM  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
8
2500  
3000  
250  
Green (RoHS  
& no Sb/Br)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
WSON  
WSON  
SOIC  
10  
10  
8
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
2500  
3000  
250  
Green (RoHS  
& no Sb/Br)  
UCC27210DRMR  
UCC27210DRMT  
UCC27211D  
VSON  
VSON  
SOIC  
DRM  
DRM  
D
8
Green (RoHS  
& no Sb/Br)  
8
Green (RoHS  
& no Sb/Br)  
8
75  
Green (RoHS  
& no Sb/Br)  
UCC27211DDA  
UCC27211DDAR  
UCC27211DPRR  
UCC27211DPRT  
UCC27211DR  
PREVIEW SO PowerPAD  
PREVIEW SO PowerPAD  
DDA  
DDA  
DPR  
DPR  
D
8
75  
Green (RoHS  
& no Sb/Br)  
8
2500  
3000  
250  
Green (RoHS  
& no Sb/Br)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
WSON  
WSON  
SOIC  
10  
10  
8
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
2500  
3000  
250  
Green (RoHS  
& no Sb/Br)  
UCC27211DRMR  
UCC27211DRMT  
VSON  
VSON  
DRM  
DRM  
8
Green (RoHS  
& no Sb/Br)  
8
Green (RoHS  
& no Sb/Br)  
(1) The marketing status values are defined as follows:  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
3-Feb-2012  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
2-Feb-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
UCC27210DPRR  
UCC27210DPRT  
UCC27210DR  
WSON  
WSON  
SOIC  
DPR  
DPR  
D
10  
10  
8
3000  
250  
330.0  
180.0  
330.0  
330.0  
330.0  
180.0  
330.0  
330.0  
180.0  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
4.25  
4.25  
6.4  
4.25  
4.25  
5.2  
1.15  
1.15  
2.1  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
Q2  
Q2  
Q1  
Q2  
Q2  
Q2  
Q1  
Q2  
Q2  
2500  
3000  
3000  
250  
UCC27210DRMR  
UCC27211DPRR  
UCC27211DPRT  
UCC27211DR  
VSON  
WSON  
WSON  
SOIC  
DRM  
DPR  
DPR  
D
8
4.25  
4.25  
4.25  
6.4  
4.25  
4.25  
4.25  
5.2  
1.15  
1.15  
1.15  
2.1  
10  
10  
8
2500  
3000  
250  
UCC27211DRMR  
UCC27211DRMT  
VSON  
VSON  
DRM  
DRM  
8
4.25  
4.25  
4.25  
4.25  
1.15  
1.15  
8
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
2-Feb-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
UCC27210DPRR  
UCC27210DPRT  
UCC27210DR  
WSON  
WSON  
SOIC  
DPR  
DPR  
D
10  
10  
8
3000  
250  
346.0  
210.0  
346.0  
346.0  
346.0  
210.0  
346.0  
346.0  
210.0  
346.0  
185.0  
346.0  
346.0  
346.0  
185.0  
346.0  
346.0  
185.0  
29.0  
35.0  
29.0  
29.0  
29.0  
35.0  
29.0  
29.0  
35.0  
2500  
3000  
3000  
250  
UCC27210DRMR  
UCC27211DPRR  
UCC27211DPRT  
UCC27211DR  
VSON  
WSON  
WSON  
SOIC  
DRM  
DPR  
DPR  
D
8
10  
10  
8
2500  
3000  
250  
UCC27211DRMR  
UCC27211DRMT  
VSON  
VSON  
DRM  
DRM  
8
8
Pack Materials-Page 2  
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配单直通车
UCC27211DRMT产品参数
型号:UCC27211DRMT
Brand Name:Texas Instruments
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
IHS 制造商:TEXAS INSTRUMENTS INC
零件包装代码:SON
包装说明:VSON-8
针数:8
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
Factory Lead Time:6 weeks
风险等级:1.6
高边驱动器:YES
接口集成电路类型:HALF BRIDGE BASED MOSFET DRIVER
JESD-30 代码:S-PDSO-N8
JESD-609代码:e4
长度:4 mm
湿度敏感等级:1
功能数量:1
端子数量:8
最高工作温度:140 °C
最低工作温度:-40 °C
最大输出电流:4 A
标称输出峰值电流:4 A
输出极性:TRUE
封装主体材料:PLASTIC/EPOXY
封装代码:HVSON
封装等效代码:SOLCC8,.15,32
封装形状:SQUARE
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260
电源:12 V
认证状态:Not Qualified
座面最大高度:1 mm
子类别:MOSFET Drivers
最大压摆率:5.2 mA
最大供电电压:17 V
最小供电电压:8 V
标称供电电压:12 V
表面贴装:YES
温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD
端子节距:0.8 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
断开时间:0.4 µs
接通时间:0.6 µs
宽度:4 mm
Base Number Matches:1
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