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产品型号UPD789114AMC-XXX-5A4的Datasheet PDF文件预览

DATA SHEET  
MOS INTEGRATED CIRCUITS  
µPD789101A,102A,104A,111A,112A,114A,101A(A),  
102A(A),104A(A),111A(A),112A(A),114A(A)  
8-BIT SINGLE-CHIP MICROCONTROLLERS  
The µPD789101A, 789102A, and 789104A (µPD78910xA hereafter) are µPD789104A Subseries products of the  
78K/0S Series.  
The µPD789111A, 789112A, and 789114A (µPD78911xA hereafter) are µPD789114A Subseries products of the  
78K/0S Series.  
Besides an 8-bit CPU, these microcontrollers incorporate a variety of hardware such as I/O ports, timers, a serial  
interface, A/D converters, and interrupt control.  
A stricter quality assurance program (called special grade in NEC’s grade classification) is applied to the  
µPD789101A(A), 789102A(A), 789104A(A) (µPD78910xA(A) hereafter), and µPD789111A(A), 789112A(A),  
789114A(A) (µPD78911xA(A) hereafter), compared to the µPD78910xA and 78911xA, which are classified as  
standard grade.  
In addition, a flash memory version (µPD78F9116A) that can operate within the same power supply voltage range  
as the mask ROM version, and a range of development tools are also being prepared.  
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before  
designing.  
µPD789104A, 789114A, 789124A, 789134A Subseries User’s Manual: To be prepared  
78K/0S Series User's Manual Instruction: U11047E  
FEATURES  
On-chip multiplier: 8 bits × 8 bits = 16 bits  
ROM and RAM sizes  
Item  
Program Memory  
(ROM)  
Data Memory  
Package  
Part Number  
(Internal High-Speed RAM)  
µPD789101A, 789111A, 789101A(A), 789111A(A)  
µPD789102A, 789112A, 789102A(A), 789112A(A)  
µPD789104A, 789114A, 789104A(A), 789114A(A)  
2 Kbytes  
4 Kbytes  
8 Kbytes  
256 bytes  
30-pin plastic SSOP  
(7.62 mm (300))  
Minimum instruction execution time can be changed from high-speed (0.4 µs) to low-speed (1.6 µs) (@ 5.0-MHz  
operation with system clock)  
I/O ports: 20  
Serial interface: 1 channel: Switchable between 3-wire serial I/O and UART modes  
8-bit resolution A/D converter: 4 channels (µPD78910xA, 78910xA(A))  
10-bit resolution A/D converter: 4 channels (µPD78911xA, 78911xA(A))  
Timers: 3 channels  
16-bit timer: 1 channel  
8-bit timer/event counter: 1 channel  
Watchdog timer: 1 channel  
Power supply voltage: VDD = 1.8 to 5.5 V  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. U14590EJ1V0DS00 (1st edition)  
Date Published January 2000 N CP(K)  
Printed in Japan  
2000  
©
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
APPLICATIONS  
Cleaners, washing machines, and refrigerators  
ORDERING INFORMATION  
Part Number  
Package  
Quality grade  
Standard  
30-pin plastic SSOP (7.62 mm (300))  
30-pin plastic SSOP (7.62 mm (300))  
30-pin plastic SSOP (7.62 mm (300))  
30-pin plastic SSOP (7.62 mm (300))  
30-pin plastic SSOP (7.62 mm (300))  
µPD789101AMC-×××-5A4  
µPD789102AMC-×××-5A4  
µPD789104AMC-×××-5A4  
µPD789111AMC-×××-5A4  
µPD789112AMC-×××-5A4  
Standard  
Standard  
Standard  
Standard  
µPD789114AMC-×××-5A4  
µPD789101AMC(A)-×××-5A4  
µPD789102AMC(A)-×××-5A4  
µPD789104AMC(A)-×××-5A4  
µPD789111AMC(A)-×××-5A4  
µPD789112AMC(A)-×××-5A4  
µPD789114AMC(A)-×××-5A4  
30-pin plastic SSOP (7.62 mm (300))  
30-pin plastic SSOP (7.62 mm (300))  
30-pin plastic SSOP (7.62 mm (300))  
30-pin plastic SSOP (7.62 mm (300))  
30-pin plastic SSOP (7.62 mm (300))  
30-pin plastic SSOP (7.62 mm (300))  
30-pin plastic SSOP (7.62 mm (300))  
Standard  
Special  
Special  
Special  
Special  
Special  
Special  
Remark ××× indicates ROM code suffix.  
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by  
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.  
2
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
78K/0S SERIES LINEUP  
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.  
Products under mass production  
Products under development  
Y subseries supports SMB.  
Small, general-purpose  
µ
µ
µ
PD789046  
PD789026 with subsystem clock added  
44 pins  
42/44 pins  
28 pins  
PD789014 with timer reinforced and ROM and RAM expanded  
µ
µ
PD789026  
PD789014  
UART. Low-voltage (1.8-V) operation  
Small, general-purpose + A/D  
RC oscillation model of  
µ
PD789197AY  
44/48 pins  
44/48 pins  
µ
µ
PD789217AY  
PD789197AY  
µ
µ
µ
µ
µ
µ
PD789177 with internal EEPROMTM  
µ
PD789177  
44 pins  
44 pins  
30 pins  
30 pins  
30 pins  
30 pins  
30 pins  
30 pins  
PD789167 with improved A/D  
PD789104A with improved timer  
PD789146 with improved A/D  
PD789104A with EEPROM added  
PD789124A with improved A/D  
µ
µ
PD789177Y  
PD789167Y  
µ
µ
µ
µ
µ
µ
µ
PD789167  
PD789156  
PD789146  
PD789134A  
PD789124A  
PD789114A  
PD789104A  
RC oscillation model of PD789104A  
µ
µ
µ
PD789104A with improved A/D  
PD789026 with A/D and multiplier added  
For inverter control  
µ
PD789842  
Internal inverter control circuit and UART  
44 pins  
78K/0S  
series  
For driving LCD  
80 pins  
80 pins  
64 pins  
64 pins  
64 pins  
64 pins  
64 pins  
64 pins  
µ
µ
µ
µ
µ
µ
PD789407A with improved A/D  
PD789456 with improved I/O  
PD789446 with improved A/D  
PD789426 with improved display output  
PD789426 with improved A/D  
PD789306 with A/D added  
µ
µ
PD789417A  
PD789407A  
µ
µ
µ
µ
µ
µ
PD789456  
PD789446  
PD789436  
PD789426  
PD789316  
PD789306  
RC oscillation model ofµPD789306  
Basic subseries for driving LCD  
For driving Dot LCD  
µ
µ
PD789835  
Segment/common output: 96 pins  
Segment: 40 pins, common: 16 pins  
144 pins  
88 pins  
PD789830  
For ASSP  
µ
PD789327 with A/D added  
52 pins  
52 pins  
44 pins  
44 pins  
20 pins  
20 pins  
µ
µ
µ
PD789467  
PD789327  
PD789800  
For remote controller. Internal LCD controller/driver  
For PC keyboard. Internal USB function  
For key pad. Internal POC  
µ
µ
µ
PD789840  
PD789861  
PD789860  
µ
RC oscillation model of PD789860  
For keyless entry. Internal POC and key return circuit  
3
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
The major differences between subseries are shown below.  
VDD  
MIN  
Timer  
Function  
Subseries Name  
ROM  
8-bit 10-bit  
Serial Interface  
I/O  
Remark  
Capacity  
A/D  
A/D  
8-bit  
1 ch  
16-bit Watch WDT  
Value  
Small,  
µPD789046 16 K  
1 ch  
1 ch  
1 ch  
1 ch (UART:1 ch) 34 pins 1.8 V  
general-  
purpose  
µPD789026 4 K-16 K  
µPD789014 2 K-4 K  
2 ch  
22 pins  
Small,  
µPD789177 16 K-24 K 3 ch  
µPD789167  
1 ch  
1 ch  
1 ch  
8 ch 1 ch (UART: 1 ch) 31 pins 1.8 V  
general-  
purpose  
+ A/D  
8 ch  
µPD789156 8 K-16 K  
µPD789146  
1 ch  
4 ch  
20 pins  
Internal  
EEPROM  
4 ch  
µ
µ
µ
µ
PD789134A 2 K-8 K  
PD789124A  
4 ch  
RC oscillation  
version  
4 ch  
PD789114A  
4 ch  
PD789104A  
4 ch  
8 ch  
For  
µPD789842 8 K-16 K  
3 ch Note 1 ch  
1 ch  
1 ch  
1 ch (UART: 1 ch) 30 pins 4.0 V  
inverter  
control  
µ
µ
PD789417A  
PD789407A  
For LCD  
driving  
12 K-24 K 3 ch  
1 ch  
1 ch  
7 ch 1 ch (UART: 1 ch) 43 pins 1.8 V  
7 ch  
µPD789456 12 K-16 K 2 ch  
µPD789446  
6 ch  
30 pins  
40 pins  
6 ch  
µPD789436  
6 ch  
µPD789426  
6 ch  
µPD789316 8 K to  
2 ch (UART: 1 ch) 23 pins  
RC oscillation  
version  
16K  
µPD789306  
For Dot µPD789835 24 K-60 K 6 ch  
1 ch  
1 ch  
2 ch  
1 ch  
27 pins 1.8 V  
LCD  
µPD789830 24 K  
1 ch  
2 ch  
1 ch  
1 ch (UART: 1 ch) 30 pins 2.7 V  
driving  
ASSP  
µPD789467 4 K-24 K  
µPD789327  
1 ch  
1 ch  
1 ch  
1 ch  
18 pins 1.8 V Internal  
LCD  
1 ch  
2 ch (USB: 1 ch) 31 pins 4.0 V  
1 ch 29 pins 2.8 V  
21 pins  
µPD789800 8 K  
µPD789840  
2 ch  
1 ch  
4 ch  
µPD789861 4 K  
14 pins 1.8 V RC oscillation  
version,  
Internal  
EEPROM  
µPD789860  
Internal  
EEPROM  
Note 10-bit timer: 1 channel  
4
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
OVERVIEW OF FUNCTIONS  
Item  
µPD789101A  
µPD789111A  
µPD789102A  
µPD789112A  
µPD789104A  
µPD789114A  
µPD789101A(A)  
µPD789111A(A)  
µPD789102A(A)  
µPD789112A(A)  
µPD789104A(A)  
µPD789114A(A)  
Internal memory  
ROM  
High-speed RAM  
2 Kbytes  
256 bytes  
4 Kbytes  
8 Kbytes  
Minimum instruction execution time  
General-purpose registers  
Instruction set  
0.4/1.6 µs (@ 5.0-MHz operation with system clock)  
8 bits × 8 registers  
16-bit operations  
Bit manipulations (set, reset, and test)  
8 bits × 8 bits = 16 bits  
Multiplier  
I/O ports  
Total:  
20  
CMOS input:  
4
CMOS I/O:  
12  
4
N-ch open-drain (12-V withstand voltage):  
A/D converters  
8-bit resolution × 4 channels (µPD78910xA, 78910xA(A))  
10-bit resolution × 4 channels (µPD78911xA, 78911xA(A))  
Serial interface  
Timer  
Switchable between 3-wire serial I/O and UART modes  
16-bit timer: 1 channel  
8-bit timer/event counter: 1 channel  
Watchdog timer: 1 channel  
Timer output  
1 output (16-bit/8-bit timer alternate function)  
Internal: 6, External: 3  
Internal: 1  
Vectored interrupt  
sources  
Maskable  
Non-maskable  
Power supply voltage  
VDD = 1.8 to 5.5 V  
Operating ambient temperature  
Package  
TA = –40 to +85°C  
30-pin plastic SSOP (7.62 mm (300))  
5
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
CONTENTS  
1. PIN CONFIGURATION (TOP VIEW)..............................................................................................  
2. BLOCK DIAGRAM ...........................................................................................................................  
7
8
3. PIN FUNCTIONS...............................................................................................................................  
3.1 Port Pins..................................................................................................................................................  
9
9
3.2 Non-Port Pins.......................................................................................................................................... 10  
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins...................................................... 11  
4. MEMORY SPACE............................................................................................................................. 13  
5. PERIPHERAL HARDWARE FUNCTIONS...................................................................................... 14  
5.1 Ports ........................................................................................................................................................ 14  
5.2 Clock Generator...................................................................................................................................... 14  
5.3 Timer........................................................................................................................................................ 15  
5.4 A/D Converter ......................................................................................................................................... 17  
5.5 Serial Interface 20................................................................................................................................... 18  
5.6 Multiplier.................................................................................................................................................. 19  
6. INTERRUPT FUNCTION .................................................................................................................. 20  
7. STANDBY FUNCTION ..................................................................................................................... 22  
8. RESET FUNCTION........................................................................................................................... 22  
9. INSTRUCTION SET OVERVIEW..................................................................................................... 23  
9.1 Conventions............................................................................................................................................ 23  
9.2 Operations............................................................................................................................................... 25  
10. ELECTRICAL SPECIFICATIONS .................................................................................................... 30  
11. CHARACTERISTICS CURVES (REFERENCE VALUES)............................................................. 41  
12. PACKAGE DRAWING...................................................................................................................... 44  
13. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 45  
APPENDIX A DEVELOPMENT TOOLS .............................................................................................. 46  
APPENDIX B RELATED DOCUMENTS.............................................................................................. 48  
6
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
1. PIN CONFIGURATION (TOP VIEW)  
30-pin plastic SSOP (7.62 mm (300))  
µPD789101AMC-×××-5A4  
µPD789111AMC-×××-5A4  
µPD789101AMC(A)-×××-5A4  
µPD789111AMC(A)-×××-5A4  
µPD789102AMC-×××-5A4  
µPD789112AMC-×××-5A4  
µPD789104AMC-×××-5A4  
µPD789114AMC-×××-5A4  
µPD789102AMC(A)-×××-5A4 µPD789104AMC(A)-×××-5A4  
µPD789112AMC(A)-×××-5A4 µPD789114AMC(A)-×××-5A4  
P23/INTP0/CPT20/SS20  
1
P22/SI20/RXD20  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
P24/INTP1/TO80/TO20  
2
P21/SO20/TXD20  
P25/INTP2/TI80  
AVDD  
3
P20/SCK20/ASCK20  
4
P11  
P10  
VDD  
P60/ANI0  
P61/ANI1  
P62/ANI2  
P63/ANI3  
AVSS  
5
6
7
VSS  
8
X1  
9
X2  
IC0  
10  
11  
12  
13  
14  
15  
IC0  
P50  
IC0  
P51  
RESET  
P03  
P02  
P01  
P52  
P53  
P00  
Cautions 1. Connect the IC0 (Internally Connected) pin directly to VSS.  
2. Connect the AVDD pin to VDD.  
3. Connect the AVSS pin to VSS.  
ANI0 to ANI3:  
ASCK20:  
AVDD:  
Analog Input  
RESET:  
RXD20:  
SCK20:  
SI20:  
Reset  
Asynchronous Serial Input  
Analog Power Supply  
Analog Ground  
Capture Trigger Input  
Internally Connected  
Interrupt from Peripherals  
Port0  
Receive Data  
Serial Clock Input/Output  
AVSS:  
Serial Data Input  
Serial Data Output  
Chip Select Input  
Timer Input  
CPT20:  
SO20:  
SS20:  
IC0:  
INTP0 to INTP2:  
P00 to P03:  
P10, P11:  
P20 to P25:  
P50 to P53:  
P60 to P63:  
TI80:  
TO20, TO80:  
TXD20:  
VDD:  
Timer Output  
Transmit Data  
Power Supply  
Ground  
Port1  
Port2  
Port5  
VSS:  
Port6  
X1, X2:  
Crystal 1, 2  
7
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
2. BLOCK DIAGRAM  
TI80/INTP2/P25  
8-BIT TIMER/  
EVENT COUNTER 80  
P00 to P03  
P10, P11  
PORT 0  
PORT 1  
PORT 2  
PORT 5  
PORT 6  
TO80/TO20  
/INTP1/P24  
TO20/TO80  
/INTP1/P24  
16-BIT TIMER 20  
WATCHDOG TIMER  
CPT20/INTP0  
/SS20/P23  
P20 to P25  
P50 to P53  
P60 to P63  
78K/0S  
CPU CORE  
ROM  
SCK20/ASCK20  
/P20  
SERIAL  
INTERFACE 20  
SO20/TxD20/P21  
SI20/RxD20/P22  
SS20/INTP0  
/CPT20/P23  
RAM  
ANI0/P60 to  
ANI3/P63  
RESET  
X1  
A/D CONVERTER  
SYSTEM  
CONTROL  
AVDD  
AVSS  
X2  
INTP0/CPT20  
/P23/SS20  
INTERRUPT  
CONTROL  
INTP1/TO80  
/TO20/P24  
V
DD  
V
SS  
IC0  
INTP2/TI80/P25  
Remark The internal ROM capacity varies depending on the product.  
8
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
3. PIN FUNCTIONS  
3.1 Port Pins  
Pin Name  
I/O  
Function  
After Reset  
Input  
Alternate Function  
P00 to  
P03  
I/O  
I/O  
I/O  
Port 0  
4-bit input/output port  
Input/output can be specified in 1-bit units  
When used as an input port, an on-chip pull-up resistor can be  
specified by means of software.  
P10, P11  
Input  
Input  
Port 1  
2-bit input/output port  
Input/output can be specified in 1-bit units  
When used as an input port, an on-chip pull-up resistor can be  
specified by means of software.  
P20  
P21  
P22  
P23  
SCK20/ASCK20  
SO20/TxD20  
SI20/RxD20  
Port 2  
6-bit input/output port  
Input/output can be specified in 1-bit units  
When used as an input port, an on-chip pull-up resistor can be  
specified by means of software.  
INTP0/CPT20  
/SS20  
P24  
P25  
INTP1/TO80/TO20  
INTP2/TI80  
P50 to  
P53  
I/O  
Input  
Input  
Port 5  
4-bit N-ch open-drain input/output port  
Input/output can be specified in 1-bit units  
An on-chip pull-up resistor can be specified by the mask option.  
P60 to  
P63  
Input  
Port 6  
ANI0 to ANI3  
4-bit input-only port  
9
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
3.2 Non-Port Pins  
Pin Name  
INTP0  
I/O  
Function  
After Reset  
Input  
Alternate Function  
Input  
P23/CPT20/SS20  
External interrupt request input for which the valid edge  
(rising edge, falling edge, or both rising and falling edges) can  
be specified  
INTP1  
INTP2  
SI20  
P24/TO80/TO20  
P25/TI80  
Input  
Output  
I/O  
Serial interface serial data input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
P22/RxD20  
SO20  
SCK20  
ASCK20  
SS20  
RxD20  
TxD20  
TI80  
Serial interface serial data output  
P21/TxD20  
Serial interface serial clock input/output  
Serial clock input for asynchronous serial interface  
Chip select input for serial interface  
Serial data input for asynchronous serial interface  
Serial data output for asynchronous serial interface  
External count clock input to 8-bit timer/event counter 80  
8-bit timer/event counter 80 output  
P20/ASCK20  
Input  
Input  
Input  
Output  
Input  
Output  
Output  
Input  
Input  
-
P20/SCK20  
P23/CPT20/INTP0  
P22/SI20  
P21/SO20  
P25/INTP2  
TO80  
TO20  
CPT20  
ANI0 to ANI3  
AVDD  
P24/INTP1/TO20  
16-bit timer 20 output  
P24/INTP1/TO80  
Capture edge input  
P23/INTP0/SS20  
A/D converter analog input  
P60 to P63  
A/D converter analog power supply  
A/D converter ground potential  
AVSS  
-
X1  
Input  
-
Connecting crystal resonator for main system clock oscillation  
X2  
RESET  
VDD  
Input  
-
System reset input  
Input  
Positive power supply  
VSS  
-
Ground potential  
IC0  
-
Internally connected. Connect directly to VSS.  
10  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins  
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.  
For the input/output circuit configuration of each type, refer to Figure 3-1.  
Table 3-1. Types of Pin Input/Output Circuits  
Pin Name  
Input/Output  
Circuit Type  
I/O  
I/O  
Recommended Connection of Unused Pins  
P00 to P03  
5-A  
Input:  
Independently connect to VDD or VSS via a resistor.  
Output: Leave open  
P10, P11  
P20/SCK20/ASCK20  
P21/SO20/TXD20  
P22/SI20/RXD20  
P23/INTP0/CPT20/SS20  
P24/INTP1/TO80/TO20  
P25/INTP2/TI80  
P50 to P53  
8-A  
Input:  
Independently connect to VSS via a resistor.  
Output: Leave open  
13-W  
Input:  
Independently connect to VDD via a resistor.  
Output: Leave open  
P60/ANI0 to P63/ANI3  
9-C  
Input  
Connect directly to VDD or VSS.  
Connect to VDD.  
AVDD  
AVSS  
RESET  
IC0  
Connect to VSS.  
2
Input  
Connect directly to VSS.  
11  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
Figure 3-1. Pin Input/Output Circuits  
Type 2  
Type 9-C  
Comparator  
P-ch  
+
IN  
N-ch  
IN  
AVSS  
V
REF  
(Threshold voltage)  
Schmitt-triggered input with hysteresis characteristics  
Input  
enable  
Type 13-W  
Type 5-A  
VDD  
VDD  
Pull-up resistor  
(mask option)  
Pull-up  
enable  
P-ch  
IN/OUT  
V
DD  
Output data  
Output disable  
N-ch  
Data  
P-ch  
IN/OUT  
V
SS  
Output  
disable  
N-ch  
Input enable  
V
SS  
Middle-voltage input buffer  
Input  
enable  
Type 8-A  
VDD  
Pull-up  
enable  
P-ch  
VDD  
Data  
P-ch  
IN/OUT  
Output  
disable  
N-ch  
V
SS  
12  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
4. MEMORY SPACE  
Figure 4-1 shows the memory map of the µPD78910xA, 78911xA, 78910xA(A), and 78911xA(A).  
Figure 4-1. Memory Map  
F F F F H  
Special function registers  
256 × 8 bits  
F F 0 0 H  
F E F F H  
Internal high-speed RAM  
256 × 8 bits  
F E 0 0 H  
F D F F H  
Reserved  
Data memory space  
n n n n H  
n n n n H + 1  
n n n n H  
Program area  
0 0 8 0 H  
0 0 7 F H  
Program memory  
space  
Internal ROMNote  
CALLT table area  
0 0 4 0 H  
0 0 3 F H  
Program area  
0 0 1 6 H  
0 0 1 5 H  
Vector table area  
0 0 0 0 H  
0 0 0 0 H  
Note The internal ROM capacity depends on the product. (See the following table).  
Last Address of Internal ROM  
Part Number  
nnnnH  
µPD789101A, 789111A, 789101A(A), 789111A(A)  
µPD789102A, 789112A, 789102A(A), 789112A(A)  
µPD789104A, 789114A, 789104A(A), 789114A(A)  
07FFH  
0FFFH  
1FFFH  
13  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
5. PERIPHERAL HARDWARE FUNCTIONS  
5.1 Ports  
The following three types of I/O ports are available:  
CMOS Input (port 6):  
4
CMOS input/output (ports 0 to 2):  
N-ch open-drain input/output (port 5):  
12  
4
Total:  
20  
Table 5-1. Port Functions  
Port Name  
Port 0  
Pin Name  
Function  
P00 to P03  
Input/output port. Input/output can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be specified by means of software.  
Port 1  
Port 2  
Port 5  
Port 6  
P10, P11  
Input/output port. Input/output can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be specified by means of software.  
P20 to P25  
P50 to P53  
P60 to P63  
Input/output port. Input/output can be specified in 1-bit units.  
An on-chip pull-up resistor can be specified by means of software.  
N-channel open-drain input/output port. Input/output can be specified in 1-bit units.  
An on-chip pull-up resistor can be specified by the mask option.  
Input-only port  
5.2 Clock Generator  
An on-chip system clock generator is provided.  
The minimum instruction execution time can be changed.  
0.4 µs/1.6 µs (@ 5.0-MHz operation with system clock)  
Figure 5-1. Clock Generator Block Diagram  
Prescaler  
Clock to  
X1  
X2  
peripheral hardware  
System  
clock  
oscillator  
Prescaler  
f
X
f
X
22  
STOP  
Wait  
control  
circuit  
Standby  
control  
circuit  
CPU clock (fCPU  
)
14  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
5.3 Timer  
Three on-chip timers are provided.  
16-bit timer 20:  
1 channel  
1 channel  
1 channel  
8-bit timer/event counter 80:  
Watchdog timer:  
Table 5-2. Timer Operation  
16-Bit Timer 20  
8-Bit Timer/Event Counter 80  
Watchdog Timer  
Operation mode Interval timer  
External event counter  
Timer output  
1 channel  
1 channel  
1 output  
1 output  
1 output  
1 channel  
1
Function  
1 output  
PWM output  
Square wave output  
Capture  
1 input  
1
Interrupt request  
1
Figure 5-2. Block Diagram of 16-Bit Timer 20 (TM20)  
Internal bus  
Output  
16-bit compare register 20  
control  
TO20/P24/  
INTP1/TO80  
(CR20)  
circuit  
Match  
INTTM20  
f
f
X
/22  
/26  
16-bit timer counter 20  
OVF  
(TM20)  
X
CPT20/P23  
/INTP0/SS20  
Edge detection  
circuit  
16-bit counter  
read buffer  
16-bit capture register  
20 (TCP20)  
Internal bus  
15  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
Figure 5-3. Block Diagram of 8-Bit Timer/Event Counter 80 (TM80)  
Internal bus  
8-bit compare register 80  
(CR80)  
Match  
INTTM80  
fX  
OVF  
Clear  
8-bit timer counter 80  
(TM80)  
f
/23  
X
Output  
control circuit  
TO80/P24/  
INTP1/TO20  
TI80/P25/  
INTP2  
Internal bus  
Figure 5-4. Watchdog Timer Block Diagram  
f
X
Prescaler  
24  
f
X
f
X
f
X
26  
28  
210  
INTWDT  
maskable  
interrupt request  
Control  
circuit  
7-bit counter  
RESET  
INTWDT  
non-maskable  
interrupt request  
16  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
5.4 A/D Converter  
The conversion resolution of the A/D converter differs depending on the product as shown below.  
8-bit A/D converter × 4 channels.... µPD789101A, 789102A, 789104A, 789101A(A), 789102A(A), 789104A(A)  
10-bit A/D converter × 4 channels.. µPD789111A, 789112A, 789114A, 789111A(A), 789112A(A), 789114A(A)  
A/D conversion can be only started by software.  
Figure 5-5. A/D Converter Block Diagram  
INTAD0  
ANI0/P60  
ANI1/P61  
ANI2/P62  
ANI3/P63  
A/D conversion  
result register  
(ADCR0)  
A/D converter  
(8-/10-bits)  
Sample&  
hold circuit  
Internal bus  
17  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
5.5 Serial Interface 20  
A one-channel serial interface is incorporated.  
Serial interface 20 has following three modes:  
Operation stop mode:  
Asynchronous serial interface (UART) mode: A dedicated baud rate generator is incorporated.  
3-wire serial I/O mode: A function to select the clock phase or data phase is incorporated.  
Power consumption can be reduced.  
Figure 5-6. Block Diagram of Serial Interface 20  
Internal bus  
Reception buffer  
register 20  
(RXB20/SIO20)  
Transmission shift  
register 20  
(TXS20/SIO20)  
Reception shift register 20  
SI20/P22/RXD20  
SO20/P21/TXD20  
Selector  
Data phase  
control  
(RXS20)  
Transmission  
data counter  
INTST20  
Reception  
data counter  
INTSR20/INTCSI20  
SS20/P23  
/CPT20/INTP0  
Baud rate generator  
SCK20/P20  
/ASCK20  
Clock phase  
control  
fX/2 to fX/28  
18  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
5.6 Multiplier  
The calculation of 8 bits × 8 bits = 16 bits can be performed.  
Figure 5-7. Multiplier Block Diagram  
Internal bus  
Multiplication data  
register A0  
Multiplication data  
register B0  
(MRA0)  
(MRB0)  
Multiplier  
16-bit multiplication result  
storing register (MUL0)  
Internal bus  
19  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
6. INTERRUPT FUNCTION  
A total of 10 interrupt sources are provided, divided into the following two types.  
Non-maskable interrupts:  
Maskable interrupts:  
1 source  
9 sources  
Table 6-1. Interrupt Source List  
Interrupt Source  
Trigger  
Vector  
Table  
Basic  
Interrupt Type  
Non-maskable  
PriorityNote 1  
Internal/External  
Internal  
Configuration  
TypeNote 2  
Name  
Address  
INTWDT  
Watchdog timer overflow  
(with watchdog timer mode 1  
selected)  
0004H  
(A)  
(B)  
(C)  
Maskable  
0
INTWDT  
Watchdog timer overflow  
(with the interval timer mode  
selected)  
1
2
3
4
INTP0  
Pin input edge detection  
External  
Internal  
0006H  
0008H  
000AH  
000CH  
INTP1  
INTP2  
INTSR20  
End of serial interface 20 UART  
reception  
(B)  
INTCSI20  
INTST20  
INTTM80  
INTTM20  
INTAD0  
End of serial interface 20 3-wire  
SIO transfer reception  
5
6
7
8
End of serial interface 20 UART  
transmission  
000EH  
0010H  
0012H  
0014H  
Generation of matching signal of  
8-bit timer/event counter 80  
Generation of matching signal of  
16-bit timer 20  
A/D conversion completion  
signal  
Notes 1. Priority is the priority order when several maskable interrupt requests are generated at the same time. 0  
is the highest order and 8 is the lowest order.  
2. Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 6-1.  
Remark As the interrupt source of the watchdog timer (INTWDT), either a non-maskable interrupt or a maskable  
interrupt (internal) can be selected.  
20  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
Figure 6-1. Basic Configuration of Interrupt Function  
(A) Internal non-maskable interrupt  
Internal bus  
Vector table address  
generator  
Interrupt request  
Standby release signal  
(B) Internal maskable interrupt  
Internal bus  
MK  
IE  
Vector table address  
generator  
IF  
Interrupt request  
Standby release signal  
(C) External maskable interrupt  
Internal bus  
External interrupt mode  
register (INTM0)  
MK  
IE  
Vector table address  
generator  
Interrupt  
request  
Edge detection  
circuit  
IF  
Standby release  
signal  
IF: Interrupt request flag  
IE: Interrupt enable flag  
MK: Interrupt mask flag  
21  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
7. STANDBY FUNCTION  
The following two standby functions are available for further reduction of system current consumption.  
HALT mode: In this mode, the CPU operation clock is stopped. The average current consumption can be  
reduced by intermittent operation by combining this mode with the normal operation mode.  
STOP mode: In this mode, oscillation of the system clock is stopped. All the operations performed on the  
system clock are suspended, resulting in extremely small power consumption.  
Figure 7-1. Standby Function  
System clock operation  
HALT instruction  
STOP  
Interrupt  
request  
instruction  
Interrupt  
request  
HALT mode  
Clock supply to CPU  
halted, oscillation  
maintained  
STOP mode  
System clock  
oscillation stopped  
(
(
(
(
8. RESET FUNCTION  
The following two reset methods are available.  
External reset by RESET signal input  
Internal reset by watchdog timer runaway time detection  
22  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
9. INSTRUCTION SET OVERVIEW  
The instruction set for the µPD78910xA, 78911xA, 78910xA(A), 78911xA(A) is listed later.  
9.1 Conventions  
9.1.1 Operand identifiers and description methods  
Operands are described in the “Operand” column of each instruction in accordance with the description method of  
the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more  
description methods, select one of them. Alphabetic letters in capitals and the symbols, #, !, $, and [ ], are keywords  
and must be described as they are. Each symbol has the following meaning.  
#: Immediate data specification  
!: Absolute address specification  
$:  
Relative address specification  
[ ]: Indirect address specification  
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to  
describe the #,!, $, or [ ] symbols.  
For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in  
parentheses in the table below, R0, R1, R2, etc.) can be used for description.  
Table 9-1. Operand Identifiers and Description Methods  
Identifier  
Description Method  
r
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7),  
AX (RP0), BC (RP1), DE (RP2), HL (RP3)  
Special function register symbol  
rp  
sfr  
saddr  
FE20H to FF1FH immediate data or label  
saddrp  
FE20H to FF1FH immediate data or label (even address only)  
addr16  
addr5  
0000H to FFFFH immediate data or label  
(Only even addresses for 16-bit data transfer instructions)  
0040H to 007FH immediate data or label (even address only)  
word  
byte  
bit  
16-bit immediate data or label  
8-bit immediate data or label  
3-bit immediate data or label  
23  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
9.1.2 Descriptions of the operation field  
A:  
A register; 8-bit accumulator  
X:  
X register  
B:  
B register  
C:  
C register  
D:  
D register  
E:  
E register  
H:  
H register  
L:  
L register  
AX:  
BC:  
DE:  
HL:  
PC:  
SP:  
PSW:  
CY:  
AC:  
Z:  
AX register pair; 16-bit accumulator  
BC register pair  
DE register pair  
HL register pair  
Program counter  
Stack pointer  
Program status word  
Carry flag  
Auxiliary carry flag  
Zero flag  
IE:  
NMIS:  
( ):  
XH, XL:  
:
Interrupt request enable flag  
Non-maskable interrupt servicing flag  
Memory contents indicated by address or register contents in parentheses  
Higher 8 bits and lower 8 bits of 16-bit register  
Logical product (AND)  
:
Logical sum (OR)  
:
Exclusive OR  
:
Inverted data  
addr16: 16-bit immediate data or label  
jdisp8: Signed 8-bit data (displacement value)  
9.1.3 Description of the flag operation field  
(Blank): Not affected  
0:  
1:  
×:  
R:  
Cleared to 0  
Set to 1  
Set/cleared according to the result  
Previously saved value is restored  
24  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
9.2 Operations  
Mnemonic  
Operand  
Byte  
Clock  
Operation  
Flag  
Z AC CY  
MOV  
r, #byte  
3
3
3
2
2
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
2
2
2
1
1
2
3
2
2
1
1
1
6
6
6
4
4
4
4
4
4
8
8
6
4
4
6
6
6
6
6
6
4
6
6
6
8
8
8
6
6
8
4
4
8
r byte  
saddr , #byte  
sfr, #byte  
A, r  
(addr) byte  
sfr byte  
A r  
Note 1  
Note 1  
r, A  
r A  
A, saddr  
saddr, A  
A, sfr  
A (saddr)  
(saddr) A  
A sfr  
sfr, A  
sfr A  
A, !addr16  
!addr16, A  
PSW, #byte  
A, PSW  
PSW, A  
A, [DE]  
A (addr16)  
(addr16) A  
PSW byte  
A PSW  
PSW A  
A (DE)  
(DE) A  
A (HL)  
×
×
×
×
×
×
[DE], A  
A, [HL]  
[HL], A  
(HL) A  
A, [HL + byte]  
[HL + byte], A  
A, X  
A (HL + byte)  
(HL + byte) A  
A X  
XCH  
Note 2  
A, r  
A r  
A, saddr  
A, sfr  
A (saddr)  
A (sfr)  
A, [DE]  
A (DE)  
A, [HL]  
A (HL)  
A, [HL + byte]  
rp, #word  
AX, saddrp  
saddrp, AX  
AX, rp  
A (HL + byte)  
rp word  
AX (saddrp)  
(saddrp) AX  
AX rp  
MOVW  
Note 3  
Note 3  
Note 3  
rp, AX  
rp AX  
XCHW  
AX, rp  
AX rp  
Notes 1. Except r = A  
2. Except r = A or X  
3. Only when rp = BC, DE, HL  
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control  
register (PCC).  
25  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
Mnemonic  
ADD  
Operand  
Byte  
Clock  
Operation  
Flag  
Z AC CY  
A, #byte  
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
A, CY A + byte  
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
saddr, #byte  
A, r  
(saddr), CY (saddr) + byte  
A ,CY A + r  
A, saddr  
A, !addr16  
A, [HL]  
A, CY A + (saddr)  
A, CY A + (addr16)  
A, CY A + (HL)  
A, [HL + byte]  
A, #byte  
saddr, #byte  
A, r  
A, CY A + (HL + byte)  
A, CY A + byte + CY  
(saddr), CY (saddr) + byte + CY  
A, CY A + r + CY  
ADDC  
A, saddr  
A, !addr16  
A, [HL]  
A, CY A + (saddr) + CY  
A, CY A + (addr16) + CY  
A, CY A + (HL) + CY  
A, CY A + (HL + byte) + CY  
A, CY A – byte  
A, [HL + byte]  
A, #byte  
saddr, #byte  
A, r  
SUB  
(saddr), CY (saddr) – byte  
A, CY A – r  
A, saddr  
A, !addr16  
A, [HL]  
A, CY A – (saddr)  
A, CY A – (addr16)  
A, CY A – (HL)  
A, [HL + byte]  
A, #byte  
saddr, #byte  
A, r  
A, CY A – (HL + byte)  
A, CY A – byte – CY  
(saddr), CY (saddr) – byte – CY  
A, CY A – r – CY  
SUBC  
A, saddr  
A, !addr16  
A, [HL]  
A, CY A – (saddr) – CY  
A, CY A – (addr16) – CY  
A, CY A – (HL) – CY  
A, CY A – (HL + byte) – CY  
A A byte  
A, [HL + byte]  
A, #byte  
saddr, #byte  
A, r  
AND  
(saddr) (saddr) byte  
A A  
r
A, saddr  
A, !addr16  
A, [HL]  
A A (saddr)  
A A (addr16)  
A A (HL)  
A, [HL + byte]  
A A (HL + byte)  
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control  
register (PCC).  
26  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
Mnemonic  
Operand  
Byte  
Clock  
Operation  
Flag  
Z AC CY  
OR  
A, #byte  
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
3
3
3
2
2
2
2
1
1
1
1
1
1
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
6
6
6
4
4
4
4
4
4
2
2
2
2
A A byte  
(saddr) (saddr) byte  
A A  
×
×
×
×
×
×
×
×
×
×
×
×
×
×
saddr, #byte  
A, r  
r
A, saddr  
A, !addr16  
A, [HL]  
A, [HL + byte]  
A, #byte  
saddr, #byte  
A, r  
A A (saddr)  
A A (addr16)  
A A (HL)  
A A (HL + byte)  
A A byte  
XOR  
(saddr) (saddr) byte  
A A  
r
A, saddr  
A, !addr16  
A, [HL]  
A, [HL + byte]  
A, #byte  
saddr, #byte  
A, r  
A A (saddr)  
A A (addr16)  
A A (HL)  
A A (HL + byte)  
A – byte  
CMP  
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
(saddr) – byte  
A – r  
A, saddr  
A, !addr16  
A, [HL]  
A, [HL + byte]  
AX, #word  
AX, #word  
AX, #word  
r
A – (saddr)  
A – (addr16)  
A – (HL)  
A – (HL + byte)  
ADDW  
SUBW  
CMPW  
INC  
AX, CY AX + word  
AX, CY AX – word  
AX – word  
r r + 1  
saddr  
(saddr) (saddr) + 1  
r r – 1  
DEC  
r
saddr  
(saddr) (saddr) – 1  
rp rp + 1  
INCW  
DECW  
ROR  
rp  
rp  
rp rp – 1  
A, 1  
(CY, A7 A0, Am – 1 Am) × 1  
(CY, A0 A7, Am + 1 Am) × 1  
(CY A0, A7 CY, Am – 1 Am) × 1  
(CY A7, A0 CY, Am + 1 Am) × 1  
×
×
×
×
ROL  
A, 1  
RORC  
ROLC  
A, 1  
A, 1  
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control  
register (PCC).  
27  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
Mnemonic  
SET1  
Operand  
Byte  
Clock  
Operation  
Flag  
Z AC CY  
saddr. bit  
3
3
2
3
2
3
3
2
3
2
1
1
1
3
6
6
(saddr. bit) 1  
sfr. bit 1  
A. bit 1  
sfr. bit  
A. bit  
4
PSW. bit  
[HL]. bit  
saddr. bit  
sfr. bit  
A. bit  
6
PSW. bit 1  
(HL) . bit 1  
(saddr. bit) 0  
sfr. bit 0  
A. bit 0  
×
×
×
10  
6
CLR1  
6
4
PSW. bit  
[HL]. bit  
CY  
6
PSW. bit 0  
(HL) . bit 0  
CY 1  
×
×
×
10  
2
SET1  
CLR1  
NOT1  
CALL  
1
0
×
CY  
2
CY 0  
CY  
2
CY CY  
!addr16  
6
(SP – 1) (PC + 3)H,(SP – 2) (PC + 3)L,  
PC addr16, SP SP – 2  
CALLT  
[addr5]  
1
8
(SP – 1) (PC + 1)H,(SP – 2) (PC + 1)L,  
PCH (00000000, addr5 + 1),  
PCL (00000000, addr5),  
SP SP – 2  
RET  
1
1
6
8
PCH (SP + 1), PCL (SP),  
SP SP + 2  
RETI  
PCH (SP + 1), PCL (SP),  
PSW (SP + 2), SP SP + 3,  
NMIS 0  
R R R  
PUSH  
POP  
PSW  
rp  
1
1
2
4
(SP – 1) PSW, SP SP – 1  
(SP – 1) rpH, (SP – 2) rpL,  
SP SP – 2  
PSW  
rp  
1
1
4
6
PSW (SP), SP SP + 1  
R R R  
rpH (SP + 1), rpL (SP),  
SP SP + 2  
MOVW  
BR  
SP, AX  
AX, SP  
!addr16  
$addr16  
AX  
2
2
3
2
1
8
6
6
6
6
SP AX  
AX SP  
PC addr16  
PC PC + 2 + jdisp8  
PCH A, PCL X  
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control  
register (PCC).  
28  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
Mnemonic  
Operand  
Byte  
Clock  
Operation  
Flag  
Z AC CY  
BC  
$addr16  
2
2
2
2
4
6
6
PC PC + 2 + jdisp8 if CY = 1  
PC PC + 2 + jdisp8 if CY = 0  
PC PC + 2 + jdisp8 if Z = 1  
PC PC + 2 + jdisp8 if Z = 0  
BNC  
BZ  
$addr16  
$addr16  
6
BNZ  
BT  
$addr16  
6
saddr. bit, $addr16  
10  
PC PC + 4 + jdisp8  
if (saddr. bit) = 1  
sfr. bit, $addr16  
A. bit , $addr16  
4
3
4
4
10  
8
PC PC + 4 + jdisp8 if sfr. bit = 1  
PC PC + 3 + jdisp8 if A. bit = 1  
PC PC + 4 + jdisp8 if PSW. bit = 1  
PSW. bit, $addr16  
saddr. bit, $addr16  
10  
10  
BF  
PC PC + 4 + jdisp8  
if (saddr. bit) = 0  
sfr. bit, $addr16  
A. bit, $addr16  
PSW. bit, $addr16  
B, $addr16  
4
3
4
2
10  
8
PC PC + 4 + jdisp8 if sfr. bit = 0  
PC PC + 3 + jdisp8 if A. bit = 0  
PC PC + 4 + jdisp8 if PSW. bit = 0  
10  
6
DBNZ  
B B – 1, then  
PC PC + 2 + jdisp8 if B 0  
C, $addr16  
2
3
6
8
C C – 1, then  
PC PC + 2 + jdisp8 if C 0  
saddr, $addr16  
(saddr) (saddr) – 1, then  
PC PC + 3 + jdisp8 if(saddr) 0  
NOP  
EI  
1
3
3
1
1
2
6
6
2
2
No Operation  
IE 1(Enable Interrupt)  
IE 0(Disable Interrupt)  
Set HALT Mode  
DI  
HALT  
STOP  
Set STOP Mode  
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control  
register (PCC).  
29  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
10. ELECTRICAL SPECIFICATIONS  
Absolute Maximum Ratings (TA = 25°C)  
Parameter  
Supply voltage  
Symbol  
VDD, AVDD  
VI1  
Conditions  
Ratings  
–0.3 to +6.5  
–0.3 to VDD + 0.3  
–0.3 to +13  
–0.3 to VDD + 0.3  
–0.3 to VDD + 0.3  
–10  
Unit  
V
VDD = AVDD  
Pins other than P50 to P53  
Input voltage  
V
VI2  
P50 to P53  
With N-ch open drain  
V
With an on-chip pull-up resistor  
V
Output voltage  
VO  
IOH  
V
Output current, high  
Per pin  
µPD78910xA, 78911xA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
°C  
°C  
Total for all pins  
Per pin  
–30  
µPD78910xA(A),  
–7  
78911xA(A)  
Total for all pins  
Per pin  
–22  
Output current, low  
IOL  
µPD78910xA, 78911xA  
30  
Total for all pins  
Per pin  
160  
µPD78910xA(A),  
10  
78911xA(A)  
Total for all pins  
120  
Operating ambient temperature  
Storage temperature  
TA  
–40 to +85  
–65 to +150  
Tstg  
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for  
any parameter. That is, the absolute maximum ratings are rated values at which the product is  
on the verge of suffering physical damage, and therefore the product must be used under  
conditions that ensure that the absolute maximum ratings are not exceeded.  
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port  
pins.  
30  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
System Clock Oscillator Characteristics  
(TA = –40 to +85°C, VDD = 1.8 to 5.5 V)  
Recommended  
Resonator  
Circuit  
Parameter  
Conditions  
MIN. TYP. MAX. Unit  
Ceramic  
Oscillation frequency (fX)Note 1  
VDD = oscillation voltage  
range  
1.0  
5.0  
MHz  
IC0 X1  
C1  
X2  
resonator  
Oscillation stabilization  
timeNote 2  
After VDD reaches  
oscillation voltage range  
MIN.  
4
ms  
C2  
Oscillation frequency (fX)Note 1  
1.0  
5.0  
10  
30  
MHz  
ms  
IC0 X1  
X2  
Crystal  
resonator  
Oscillation stabilization  
timeNote 2  
VDD = 4.5 to 5.5 V  
C1  
X1  
C2  
External  
clock  
X1 input frequency (fX)Note 1  
1.0  
85  
5.0  
MHz  
ns  
X2  
X1 input high-/low-level  
width (tXH, tXL)  
500  
X1 input frequency (fX)Note 1  
VDD = 2.7 to 5.5 V  
1.0  
85  
5.0  
MHz  
ns  
X1  
X2  
X1 input high-/low-level  
width (tXH, tXL)  
500  
OPEN  
Notes 1. Indicates only oscillator characteristics. Refer to AC characteristics for instruction execution time.  
2. Time required to stabilize oscillation after a reset or STOP mode release. Use the resonator that  
stabilizes oscillation during the oscillation wait time.  
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines  
in the above figures to avoid an adverse effect from wiring capacitance.  
Keep the wiring length as short as possible.  
Do not cross the wiring with the other signal lines.  
Do not route the wiring near a signal line through which a high fluctuating current flows.  
Always make the ground point of the oscillator capacitor the same potential as VSS.  
Do not ground the capacitor to a ground pattern through which a high current flows.  
Do not fetch signals from the oscillator.  
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the  
oscillation themselves or apply to the resonator manufacturer for evaluation.  
31  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (1/2)  
Parameter  
Symbol  
IOH  
Conditions  
MIN.  
TYP.  
MAX.  
–1  
Unit  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
V
Output current, high  
Per pin  
µPD78910xA, 78911xA  
Total for all pins  
Per pin  
–15  
µPD78910xA(A), 78911xA(A)  
µPD78910xA, 78911xA  
–1  
Total for all pins  
Per pin  
–11  
Output current, low  
Input voltage, high  
IOL  
10  
Total for all pins  
Per pin  
80  
µPD78910xA(A), 78911xA(A)  
3
Total for all pins  
60  
VIH1  
Pins other than described  
below  
VDD = 2.7 to 5.5 V  
0.7 VDD  
0.9 VDD  
0.7 VDD  
0.9 VDD  
0.7 VDD  
0.9 VDD  
0.8 VDD  
0.9 VDD  
VDD–0.5  
VDD–0.1  
0
VDD  
VDD  
V
VIH2  
P50 to P53 With N-ch open VDD = 2.7 to 5.5 V  
drain  
12  
V
VDD  
V
With on-chip  
VDD = 2.7 to 5.5 V  
VDD = 2.7 to 5.5 V  
VDD = 4.5 to 5.5 V  
VDD = 2.7 to 5.5 V  
VDD = 2.7 to 5.5 V  
VDD = 2.7 to 5.5 V  
VDD = 4.5 to 5.5 V  
VDD  
V
pull-up resistor  
VDD  
V
VIH3  
VIH4  
VIL1  
VIL2  
VIL3  
VIL4  
RESET, P20 to P25  
VDD  
V
VDD  
V
X1, X2  
VDD  
V
VDD  
V
Input voltage, low  
Pins other than described  
below  
0.3 VDD  
0.1 VDD  
0.3 VDD  
0.1 VDD  
0.2 VDD  
0.1 VDD  
0.4  
V
0
V
P50 to P53  
0
V
0
V
RESET, P20 to P25  
X1, X2  
0
V
0
V
0
V
0
0.1  
V
Output voltage, high  
Output voltage, low  
VOH1  
VOH2  
VOL1  
VDD = 4.5 to 5.5 V, IOH = –1 mA  
VDD–1.0  
VDD–0.5  
V
VDD = 1.8 to 5.5 V, IOH = –100 µA  
V
Pins other  
than P50 to  
P53  
VDD = 4.5 to 5.5 V, IOL = 10 mA  
1.0  
1.0  
V
(µPD78910xA, 78911xA)  
VDD = 4.5 to 5.5 V, IOL = 3 mA  
V
(µPD78910xA(A), 78911xA(A))  
VDD = 1.8 to 5.5 V, IOL = 400 µA  
0.5  
1.0  
V
V
VOL2  
P50 to P53  
VDD = 4.5 to 5.5 V, IOL = 10 mA  
(µPD78910xA, 78911xA)  
VDD = 4.5 to 5.5 V, IOL = 3 mA  
1.0  
0.4  
V
V
(µPD78910xA(A), 78911xA(A))  
VDD = 1.8 to 5.5 V, IOL = 1.6 mA  
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port  
pins.  
32  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)  
Parameter  
Symbol  
ILIH1  
Conditions  
MIN.  
TYP.  
MAX.  
3
Unit  
Input leakage current,  
high  
Pins other than X1, X2,  
VIN = VDD  
µA  
or P50 to P53  
ILIH2  
ILIH3  
X1, X2  
20  
20  
µA  
µA  
P50 to P53 (N-ch open  
drain)  
VIN = 12 V  
VIN = 0 V  
Input leakage current,  
low  
ILIL1  
Pins other than X1, X2,  
or P50 to P53  
–3  
µA  
ILIL2  
ILIL3  
X1, X2  
–20  
µA  
µA  
P50 to P53 (N-ch open  
drain)  
–3Note 1  
µA  
µA  
kΩ  
kΩ  
Output leakage  
current, high  
ILOH  
VOUT = VDD  
3
Output leakage  
current, low  
ILOL  
VOUT = 0 V  
–3  
Software pull-up  
resistor  
R1  
VIN = 0 V, for pins other than P50 to P53  
VIN = 0 V, P50 to P53  
50  
10  
100  
30  
200  
60  
Mask option pull-up  
resistor  
R2  
Power supply  
current  
IDD1Note 2  
5.0-MHz crystal  
VDD = 5.0 V±10%Note 4  
1.8  
0.45  
0.25  
0.8  
3.2  
0.9  
0.45  
1.6  
0.6  
0.3  
10  
mA  
mA  
mA  
mA  
mA  
mA  
µA  
oscillation operating  
mode (C1 = C2 = 22pF)  
VDD = 3.0 V±10%Note 5  
VDD = 2.0 V±10%Note 5  
VDD = 5.0 V±10%Note 4  
VDD = 3.0 V±10%Note 5  
VDD = 2.0 V±10%Note 5  
VDD = 5.0 V±10%  
IDD2Note 2  
IDD3Note 2  
IDD4Note 3  
5.0-MHz crystal  
oscillation HALT mode  
(C1 = C2 = 22pF)  
0.3  
0.15  
0.1  
STOP mode  
µA  
VDD = 3.0 V±10%  
0.05  
0.05  
3.0  
5.0  
5.0  
5.5  
3.2  
2.7  
µA  
VDD = 2.0 V±10%  
5.0-MHz crystal  
VDD = 5.0 V±10%Note 4  
VDD = 3.0 V±10%Note 5  
VDD = 2.0 V±10%Note 5  
mA  
mA  
mA  
oscillation A/D operating  
mode (C1 = C2 = 22pF)  
1.65  
1.25  
Notes 1. When pull-up resistors are not connected to P50 to P53 (specified by the mask option) and when port 5  
is in input mode, a low-level input leakage current of –30 µA (MAX.) flows only for 1 cycle time after a  
read instruction has been executed to port 5.  
2. The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) and  
AVDD current are not included.  
3. The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) is not  
included.  
4. High-speed mode operation (when processor clock control register (PCC) is set to 00H.)  
5. Low-speed mode operation (when PCC is set to 02H).  
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port  
pins.  
33  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
AC Characteristics  
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)  
Parameter  
Cycle time  
Symbol  
TCY  
Conditions  
MIN.  
0.4  
TYP.  
MAX.  
8
Unit  
VDD = 2.7 to 5.5 V  
µs  
(minimum instruction  
execution time)  
1.6  
8
µs  
TI80 input high-/low-  
level width  
tTIH,  
tTIL  
VDD = 2.7 to 5.5 V  
VDD = 2.7 to 5.5 V  
INTP0 to INTP2  
0.1  
1.8  
0
µs  
µs  
MHz  
kHz  
TI80 input frequency  
fTI  
4
0
275  
Interrupt input high-  
/low-level width  
tINTH,  
tINTL  
10  
µs  
µs  
µs  
RESET low-level  
width  
tRSL  
10  
10  
CPT20 input high-  
/low-level width  
tCPH,  
tCPL  
TCY vs VDD  
60  
10  
µ
Guaranteed  
operation range  
2.0  
1.0  
0.5  
0.4  
0.1  
1
2
3
4
5
6
Supply voltage VDD [V]  
34  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
(2) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)  
(i) 3-wire serial I/O mode (SCK20...Internal clock output)  
Parameter  
Symbol  
tKCY1  
Conditions  
VDD = 2.7 to 5.5 V  
MIN.  
800  
TYP.  
MAX.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SCK20 cycle time  
3200  
tKCY1/2 – 50  
tKCY1/2 – 150  
150  
SCK20 high-/low-  
level width  
tKH1,  
tKL1  
VDD = 2.7 to 5.5 V  
VDD = 2.7 to 5.5 V  
VDD = 2.7 to 5.5 V  
SI20 setup time  
tSIK1  
tKSI1  
tKSO1  
(to SCK20)  
500  
SI20 hold time  
400  
(from SCK20)  
600  
SO20 output delay  
R = 1 k ,  
C = 100 pFNote  
VDD = 2.7 to 5.5 V  
0
250  
time from SCK20↓  
0
1000  
Note R and C are the load resistance and load capacitance of the SO output line.  
(ii) 3-wire serial I/O mode (SCK20...External clock input)  
Parameter  
Symbol  
tKCY2  
Conditions  
VDD = 2.7 to 5.5 V  
MIN.  
800  
3200  
400  
1600  
100  
150  
400  
600  
0
TYP.  
MAX.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SCK20 cycle time  
SCK20 high-/low-  
level width  
tKH2,  
tKL2  
VDD = 2.7 to 5.5 V  
VDD = 2.7 to 5.5 V  
VDD = 2.7 to 5.5 V  
SI20 setup time  
tSIK2  
tKSI2  
tKSO2  
(to SCK20)  
SI20 hold time  
(from SCK20)  
SO20 output delay  
R = 1 k,  
C = 100 pFNote  
VDD = 2.7 to 5.5 V  
300  
time from SCK20↓  
0
1000  
120  
ns  
ns  
SO20 setup time  
(for SS20when  
SS20 is used)  
tKAS2  
VDD = 2.7 to 5.5 V  
VDD = 2.7 to 5.5 V  
400  
240  
800  
ns  
ns  
ns  
SO20 disable time  
(for SS20when  
SS20 is used)  
tKDS2  
Note R and C are the load resistance and load capacitance of the SO output line.  
(iii) UART mode (Dedicated baud rate generator output)  
Parameter  
Transfer rate  
Symbol  
Conditions  
VDD = 2.7 to 5.5 V  
MIN.  
TYP.  
MAX.  
78125  
19531  
Unit  
bps  
bps  
35  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
(iv) UART mode (external clock input)  
Parameter  
Symbol  
tKCY3  
Conditions  
VDD = 2.7 to 5.5 V  
MIN.  
800  
TYP.  
MAX.  
Unit  
ns  
ASCK20 cycle time  
3200  
400  
ns  
ASCK20 high-/low-  
level width  
tKH3,  
tKL3  
VDD = 2.7 to 5.5 V  
VDD = 2.7 to 5.5 V  
ns  
1600  
ns  
Transfer rate  
39063  
9766  
1
bps  
bps  
µ s  
ASCK20 rise/fall time  
tR,  
tF  
36  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
AC Timing Test Points (excluding X1 input)  
0.8VDD  
0.2VDD  
0.8VDD  
0.2VDD  
Test points  
Clock Timing  
1/f  
X
t
XL  
t
XH  
V
IH4 (MIN.)  
IL4 (MAX.)  
X1 input  
V
TI Timing  
1/fTI  
t
TIL  
t
TIH  
TI80  
Interrupt Input Timing  
t
INTL  
t
INTH  
INTP0 to INTP2  
RESET Input Timing  
t
RSL  
RESET  
37  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
Serial Transfer Timing  
3-wire serial I/O mode:  
t
KCYm  
t
KLm  
t
KHm  
SCK20  
t
SIKm  
t
KSIm  
Input data  
SI20  
t
KSOm  
Output data  
SO20  
m = 1, 2  
3-wire serial I/O mode (when SS20 is used):  
SS20  
t
KAS2  
t
KDS2  
SO20  
Output data  
UART mode (external clock input):  
t
KCY3  
t
KL3  
t
KH3  
t
R
t
F
ASCK20  
38  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
8-Bit A/D Converter Characteristics (µPD78910xA, 78910xA(A))  
(TA = 40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)  
Parameter  
Resolution  
Symbol  
Conditions  
MIN.  
8
TYP.  
8
MAX.  
8
Unit  
bit  
Overall errorNote1,2  
VDD = 2.7 to 5.5 V  
VDD = 2.7 to 5.5 V  
±0.4  
±0.8  
±0.6  
±1.2  
100  
100  
AVDD  
%FSR  
%FSR  
µs  
Conversion time  
tCONV  
14  
28  
0
µs  
Analog input  
voltage  
VIAN  
V
Notes 1. Excludes quantization error (±0.2%).  
2. It is indicated as a ratio to the full-scale value (%FSR).  
10-Bit A/D Converter Characteristics (µPD78911xA, 78911xA(A))  
(TA = 40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)  
Parameter  
Resolution  
Symbol  
Conditions  
MIN.  
10  
TYP.  
10  
MAX.  
10  
Unit  
bit  
Overall errorNote1,2  
4.5 V VDD 5.5 V  
±0.2  
±0.4  
±0.8  
±0.4  
±0.6  
±1.2  
100  
%FSR  
%FSR  
%FSR  
µs  
2.7 V VDD < 4.5 V  
1.8 V VDD < 2.7 V  
2.7 V VDD 5.5 V  
1.8 V VDD < 2.7 V  
4.5 V VDD 5.5 V  
2.7 V VDD < 4.5 V  
1.8 V VDD < 2.7 V  
4.5 V VDD 5.5 V  
2.7 V VDD < 4.5 V  
1.8 V VDD < 2.7 V  
4.5 V VDD 5.5 V  
2.7 V VDD < 4.5 V  
1.8 V VDD < 2.7 V  
4.5 V VDD 5.5 V  
2.7 V VDD < 4.5 V  
1.8 V VDD < 2.7 V  
Conversion time  
tCONV  
14  
28  
100  
µs  
Zero-scale errorNote1,2  
±0.4  
±0.6  
±1.2  
±0.4  
±0.6  
±1.2  
±2.5  
±4.5  
±8.5  
±1.5  
±2.0  
±3.5  
AVDD  
%FSR  
%FSR  
%FSR  
%FSR  
%FSR  
%FSR  
LSB  
Full-scale errorNote1,2  
Non-integral linearity  
errorNote1  
INL  
LSB  
LSB  
Non-differential  
linearity errorNote1  
DNL  
VIAN  
LSB  
LSB  
LSB  
Analog input voltage  
0
V
Notes 1. Excludes quantization error (±0.05%).  
2. It is indicated as a ratio to the full-scale value (%FSR).  
39  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)  
Parameter  
Symbol  
VDDDR  
Conditions  
MIN.  
1.8  
TYP.  
MAX.  
5.5  
Unit  
V
Data retention  
supply voltage  
Release signal  
set time  
tSREL  
0
µs  
Oscillation  
tWAIT  
Release by RESET  
Release by interrupt request  
215/fX  
ms  
ms  
stabilization wait  
timeNote 1  
Note 2  
Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid  
unstable operation at the beginning of oscillation.  
2. Selection of 212/fX, 215/fX, or 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation  
stabilization time select register.  
Remark fX: System clock oscillation frequency  
Data Retention Timing (STOP mode release by RESET)  
Internal reset operation  
HALT mode  
STOP mode  
Operating mode  
Data retention mode  
VDD  
VDDDR  
tSREL  
STOP instruction execution  
RESET  
tWAIT  
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)  
HALT mode  
STOP mode  
Operating mode  
Data retention mode  
VDD  
VDDDR  
t
SREL  
STOP instruction execution  
Standby release signal  
(interrupt request)  
t
WAIT  
40  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
11. CHARACTERISTICS CURVES (REFERENCE VALUES)  
IDD vs VDD (System clock: 5.0-MHz crystal resonator)  
(T  
A = 25 ˚C)  
10  
5.0  
PCC = 00H  
PCC = 02H  
1.0  
0.5  
PCC = 00H (HALT mode)  
PCC = 02H (HALT mode)  
0.1  
0.05  
0.01  
X2  
X1  
0.005  
Crystal resonator  
5.0 MHz  
22 pF  
22 pF  
0.001  
7
5
6
8
3
4
0
1
2
Power supply voltage VDD (V)  
41  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
IDD vs VDD (System clock: 4.0-MHz crystal resonator)  
(TA = 25 ˚C)  
10  
5.0  
PCC = 00H  
PCC = 02H  
PCC = 00H (HALT mode)  
PCC = 02H (HALT mode)  
1.0  
0.5  
0.1  
0.05  
0.01  
X2  
X1  
0.005  
Crystal resonator  
4.0 MHz  
22 pF  
22 pF  
0.001  
7
5
6
8
3
4
0
1
2
Power supply voltage VDD (V)  
42  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
IDD vs VDD (System clock: 2.0-MHz crystal resonator)  
(T  
= 25 ˚C)  
A
10  
5.0  
1.0  
0.5  
PCC = 00H  
PCC = 02H  
PCC = 00H (HALT mode)  
PCC = 02H (HALT mode)  
0.1  
0.05  
0.01  
X2  
X1  
0.005  
Crystal resonator  
2.0 MHz  
47 pF  
47 pF  
0.001  
7
5
6
8
3
4
0
1
2
Power supply voltage VDD (V)  
43  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
12. PACKAGE DRAWING  
30-PIN PLASTIC SSOP (7.62 mm (300))  
30  
16  
detail of lead end  
F
G
T
P
L
1
15  
U
E
A
H
I
J
S
B
C
N
S
M
D
M
K
NOTE  
ITEM MILLIMETERS  
Each lead centerline is located within 0.13 mm of  
its true position (T.P.) at maximum material condition.  
A
B
C
9.85±0.15  
0.45 MAX.  
0.65 (T.P.)  
+0.08  
0.24  
D
0.07  
E
F
G
H
I
0.1±0.05  
1.3±0.1  
1.2  
8.1±0.2  
6.1±0.2  
1.0±0.2  
0.17±0.03  
0.5  
J
K
L
M
N
0.13  
0.10  
+5°  
3°  
P
3°  
T
0.25  
U
0.6±0.15  
S30MC-65-5A4-2  
44  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
13. RECOMMENDED SOLDERING CONDITIONS  
The µPD78910xA, 78911xA, 78910xA(A), and 78911xA(A) should be soldered and mounted under the following  
recommended conditions.  
For the details of the recommended soldering conditions, refer to the document Semiconductor Device  
Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended  
below, contact your NEC sales representative.  
Table 13-1. Surface Mounting Type Soldering Conditions  
µPD789101AMC-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))  
µPD789102AMC-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))  
µPD789104AMC-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))  
µPD789111AMC-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))  
µPD789112AMC-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))  
µPD789114AMC-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))  
µPD789101AMC(A)-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))  
µPD789102AMC(A)-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))  
µPD789104AMC(A)-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))  
µPD789111AMC(A)-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))  
µPD789112AMC(A)-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))  
µPD789114AMC(A)-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))  
Soldering Method  
Infrared reflow  
VPS  
Soldering Conditions  
Recommended  
Condition Symbol  
Package peak temperature: 235°C, Time: 30 sec. Max. (at 210°C or higher),  
Count: three times or less  
IR35-00-3  
VP15-00-3  
WS60-00-1  
Package peak temperature: 215°C, Time: 40 sec. Max. (at 200°C or higher),  
Count: three times or less  
Wave soldering  
Partial heating  
Solder bath temperature: 260°C Max., Time: 10 sec. Max., Count: once,  
Preheating temperature: 120°C Max. (package surface temperature)  
Pin temperature: 300°C Max., Time: 3 sec. Max. (per pin row)  
Caution Do not use different soldering methods together (except for partial heating).  
45  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
APPENDIX A DEVELOPMENT TOOLS  
The following development tools are available for system development using the µPD78910xA, µPD78911xA,  
µPD78910xA(A), and µPD78911xA(A).  
Language Processing Software  
RA78K0SNotes 1, 2, 3  
CC78K0SNotes 1, 2, 3  
DF789136Notes 1, 2, 3  
Assembler package common to 78K/0S Series  
C compiler package common to 78K/0S Series  
Device file for µPD789104A, 789114A Subseries  
Flash Memory Writing Tools  
Flashpro lIl  
(Model number: FL-PR3Note 4  
Dedicated flash programmer for on-chip flash memory  
,
PG-FP3)  
FA-30MCNote 4  
Flash memory writing adapter  
Debugging Tools (1/2)  
IE-78K0S-NS  
In-circuit emulator serves to debug hardware and software when developing application systems  
using a 78K/0S Series product. It supports the ID78K0S-NS integrated debugger. Used in  
combination with an AC adapter, emulation probe, and interface adapter connecting to the host  
machine.  
In-circuit emulator  
IE-70000-MC-PS-B  
AC adapter  
Adapter used to supply power from a power outlet of 100 V AC to 240 V AC.  
IE-70000-98-IF-C  
Interface adapter  
Adapter when PC-9800 series PC (except notebook type) is used as the IE-78K0S-NS host  
machine (C bus supported).  
IE-70000-CD-IF-A  
PC card interface  
PC card and interface cable when notebook PC is used as the IE-78K0S-NS host machine  
(PCMCIA socket supported).  
IE-70000-PC-IF-C  
Interface adapter  
Adapter when using an IBM PC/AT™ or compatible as the IE-78K0S-NS host machine.  
IE-70000-PCI-IF  
Interface adapter  
Adapter when using PC that includes a PCI bus as the IE-78K0S-NS host machine.  
IE-789136-NS-EM1  
Emulation board  
Board for emulation of the peripheral hardware peculiar to a device. Used in combination with  
an in-circuit emulator.  
NP-36GSNote 4  
Board used to connect the in-circuit emulator to the target system. For a 30-pin plastic SSOP  
(MC-5A4 type), used in combination with NGS-30.  
NGS-30Note 4  
Conversion socket used to connect the NP-36GS to the target system board designed to mount  
a 30-pin plastic SSOP (MC-5A4 type).  
Conversion socket  
Notes 1. PC-9800 series (Japanese Windows™) based  
2. IBM PC/AT or compatibles (Japanese/English Windows) based  
3. HP9000 series 700™ (HP-UX™), SPARCstation™ (SunOS™, Solaris™), or NEWS™ (NEWS-OS™)  
based.  
4. Products made by Naito Densei Machida Mfg. Co., Ltd. (Phone: +81-44-822-3813). Contact an NEC  
distributor regarding the purchase of these products.  
Remark RA78K0S, CC78K0S, and SM78K0S are used in combination with the DF789136.  
46  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
Debugging Tools (2/2)  
SM78K0SNotes 1, 2  
ID78K0S-NSNotes 1, 2  
DF789136Notes 1, 2  
System simulator common to 78K/0S Series  
Integrated debugger common to 78K/0S Series  
Device file for µPD789104A, 789114A Subseries  
Real-time OS  
MX78K0SNotes 1, 2  
OS for 78K/0S Series  
Notes 1. PC-9800 series (Japanese Windows) based.  
2. IBM PC/AT or compatibles (Japanese/English Windows) based.  
47  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
APPENDIX B RELATED DOCUMENTS  
Documents Related to Devices  
Document No.  
Japanese English  
Document Name  
µPD789101A, 102A, 104A, 111A, 112A, 114A, 101A(A), 102A(A), 104A(A), 111A(A),  
U14590J  
This manual  
112A(A), 114A(A) Data Sheet  
µPD78F9116A Data Sheet  
To be prepared  
To be prepared  
U11047J  
To be prepared  
To be prepared  
U11047E  
µPD789104A, 789114A, 789124A, 789134A Subseries User’s Manual  
78K/0S Series User’s Manual Instruction  
78K/0, 78K/0S Series Application Note Flash Memory Write  
U14458J  
U14458E  
Documents Related to Development Tools (User’s Manuals)  
Document No.  
English  
Document Name  
Japanese  
U11622J  
RA78K0S Assembler Package  
Operation  
U11622E  
Assembly Language  
U11599J  
U11599E  
U11623E  
Structured Assembly  
Language  
U11623J  
CC78K0S C Compiler  
Operation  
Language  
Reference  
U11816J  
U11817J  
U11489J  
U10092J  
U11816E  
U11817E  
U11489E  
U10092E  
SM78K0S System Simulator Windows Based  
SM78K Series System Simulator  
External Parts User Open  
Interface Specifications  
ID78K0S-NS Integrated Debugger Windows Based  
IE-78K0S-NS In-circuit Emulator  
Reference  
U12901J  
U13549J  
U14363J  
U12901E  
U13549E  
IE-789136-NS-EM1 Emulation Board  
To be prepared  
Documents Related to Embedded Software (User’s Manuals)  
Document No.  
Document Name  
Japanese  
U12938J  
English  
78K/0S Series OS MX78K0S  
Fundamental  
U12938E  
Caution The related documents listed above are subject to change without notice. Be sure to use the  
latest version of each document for designing.  
48  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
Other Related Documents  
Document No.  
Japanese English  
Document Name  
SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM)  
Semiconductor Device Mounting Technology Manual  
X13769X  
C10535J  
C11531J  
C10983J  
C11892J  
U11416J  
C10535E  
Quality Grades on NEC Semiconductor Devices  
C11531E  
C10983E  
C11892E  
NEC Semiconductor Device Reliability/Quality Control System  
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)  
Guide to Microcomputer-Related Products by Third Party  
Caution The related documents listed above are subject to change without notice. Be sure to use the  
latest version of each document for designing.  
49  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
NOTES FOR CMOS DEVICES  
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS  
Note:  
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and  
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity  
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control  
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using  
insulators that easily build static electricity. Semiconductor devices must be stored and transported  
in an anti-static container, static shielding bag or conductive material. All test and measurement  
tools including work bench and floor should be grounded. The operator should be grounded using  
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need  
to be taken for PW boards with semiconductor devices on it.  
2
HANDLING OF UNUSED INPUT PINS FOR CMOS  
Note:  
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided  
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence  
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels  
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused  
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of  
being an output pin. All handling related to the unused pins must be judged device by device and  
related specifications governing the devices.  
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES  
Note:  
Power-on does not necessarily define initial status of MOS device. Production process of MOS  
does not define the initial operation status of the device. Immediately after the power source is  
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does  
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the  
reset signal is received. Reset operation must be executed immediately after power-on for devices  
having reset function.  
EEPROM is a trademark of NEC Corporation.  
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or  
other countries.  
PC/AT is a trademark of International Business Machines Corporation.  
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.  
SPARCstation is a trademark of SPARC International, Inc.  
Solaris and SunOS are trademarks of Sun Microsystems, Inc.  
NEWS and NEWS-OS are trademarks of SONY Corporation.  
50  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
Regional Information  
Some information contained in this document may vary from country to country. Before using any NEC  
product in your application, pIease contact the NEC office in your country to obtain a list of authorized  
representatives and distributors. They will verify:  
Device availability  
Ordering information  
Product release schedule  
Availability of related technical literature  
Development environment specifications (for example, specifications for third-party tools and  
components, host computers, power plugs, AC supply voltages, and so forth)  
Network requirements  
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary  
from country to country.  
NEC Electronics Inc. (U.S.)  
Santa Clara, California  
Tel: 408-588-6000  
800-366-9782  
NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.  
Benelux Office  
Hong Kong  
Eindhoven, The Netherlands  
Tel: 040-2445845  
Tel: 2886-9318  
Fax: 2886-9022/9044  
Fax: 408-588-6130  
800-729-9288  
Fax: 040-2444580  
NEC Electronics Hong Kong Ltd.  
Seoul Branch  
Seoul, Korea  
Tel: 02-528-0303  
Fax: 02-528-4411  
NEC Electronics (France) S.A.  
Velizy-Villacoublay, France  
Tel: 01-30-67 58 00  
NEC Electronics (Germany) GmbH  
Duesseldorf, Germany  
Tel: 0211-65 03 02  
Fax: 01-30-67 58 99  
Fax: 0211-65 03 490  
NEC Electronics Singapore Pte. Ltd.  
United Square, Singapore 1130  
Tel: 65-253-8311  
NEC Electronics (France) S.A.  
Spain Office  
Madrid, Spain  
NEC Electronics (UK) Ltd.  
Milton Keynes, UK  
Tel: 01908-691-133  
Fax: 65-250-3583  
Tel: 91-504-2787  
Fax: 01908-670-290  
Fax: 91-504-2860  
NEC Electronics Taiwan Ltd.  
Taipei, Taiwan  
Tel: 02-2719-2377  
NEC Electronics Italiana s.r.l.  
Milano, Italy  
Tel: 02-66 75 41  
NEC Electronics (Germany) GmbH  
Scandinavia Office  
Taeby, Sweden  
Fax: 02-2719-5951  
Fax: 02-66 75 42 99  
Tel: 08-63 80 820  
NEC do Brasil S.A.  
Fax: 08-63 80 388  
Electron Devices Division  
Rodovia Presidente Dutra, Km 214  
07210-902-Guarulhos-SP Brasil  
Tel: 55-11-6465-6810  
Fax: 55-11-6465-6829  
J99.1  
51  
Data Sheet U14590EJ1V0DS00  
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)  
The related documents indicated in this publication may include preliminary versions. However, preliminary  
versions are not marked as such.  
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited  
without governmental license, the need for which must be judged by the customer. The export or re-export of this product  
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales  
representative.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
No part of this document may be copied or reproduced in any form or by any means without the prior written  
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in  
this document.  
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property  
rights of third parties by or arising from use of a device described herein or any other liability arising from use  
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other  
intellectual property rights of NEC Corporation or others.  
Descriptions of circuits, software, and other related information in this document are provided for illustrative  
purposes in semiconductor product operation and application examples. The incorporation of these circuits,  
software, and information in the design of the customer's equipment shall be done under the full responsibility  
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third  
parties arising from the use of these circuits, software, and information.  
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,  
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or  
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety  
measures in its design, such as redundancy, fire-containment, and anti-failure features.  
NEC devices are classified into the following three quality grades:  
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a  
customer designated "quality assurance program" for a specific application. The recommended applications of  
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device  
before using it in a particular application.  
Standard: Computers, office equipment, communications equipment, test and measurement equipment,  
audio and visual equipment, home electronic appliances, machine tools, personal electronic  
equipment and industrial robots  
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster  
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed  
for life support)  
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life  
support systems or medical equipment for life support, etc.  
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.  
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,  
they should contact an NEC sales representative in advance.  
M7 98. 8  
配单直通车
UPD789114AMC-XXX-5A4-A产品参数
型号:UPD789114AMC-XXX-5A4-A
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
IHS 制造商:RENESAS ELECTRONICS CORP
零件包装代码:SSOP
包装说明:LSSOP, SSOP30,.3
针数:30
Reach Compliance Code:compliant
HTS代码:8542.31.00.01
风险等级:5.45
具有ADC:YES
地址总线宽度:
位大小:8
CPU系列:UPD78K0
最大时钟频率:5 MHz
DAC 通道:NO
DMA 通道:NO
外部数据总线宽度:
JESD-30 代码:R-PDSO-G30
JESD-609代码:e6
长度:9.85 mm
I/O 线路数量:20
端子数量:30
最高工作温度:85 °C
最低工作温度:-40 °C
PWM 通道:YES
封装主体材料:PLASTIC/EPOXY
封装代码:LSSOP
封装等效代码:SSOP30,.3
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/5 V
认证状态:Not Qualified
RAM(字节):256
ROM(单词):8192
ROM可编程性:MROM
座面最大高度:1.4 mm
速度:10 MHz
子类别:Microcontrollers
最大压摆率:5.5 mA
最大供电电压:5.5 V
最小供电电压:1.8 V
标称供电电压:3 V
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子面层:TIN BISMUTH
端子形式:GULL WING
端子节距:0.65 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6.1 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLER
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