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产品型号USBLC6-4SC6的概述

芯片USBLC6-4SC6的概述 USBLC6-4SC6是一款专为USB接口设计的保护器件，通常用于防止静电放电（ESD）和电压浪涌对电子元件的损害。随着电子设备功能的复杂化和集成度的提升，电源管理和信号保护的需求越来越大。USBLC6-4SC6正是为满足这一需求而设计的先进保护器件，广泛用于消费电子、计算机、通信设备等领域。芯片USBLC6-4SC6的详细参数 USBLC6-4SC6具有多项技术参数，主要特色包括： 1. 工作电压范围：该芯片支持多种工作电压，一般在5V到28V之间，使其适用于不同的应用场景。 2. ESD保护等级：符合IEC 61000-4-2标准，具有±8kV的接触放电和±15kV的空气放电能力，能够有效防护外界静电对设备的损害。 3. 额定功率：USBLC6-4SC6的额定功率通常在2W到3W之间，确保在大部分工作负荷下均能稳定工作。 4. 串联电阻：根...

产品型号USBLC6-4SC6的Datasheet PDF文件预览

USBLC6-4SC6

VERY LOW CAPACITANCE

ESD PROTECTION

ASD

(Application Specific Devices)

MAIN APPLICATIONS

■

USB2.0 ports up to 480Mb/s (high speed)

Backwards compatible with USB1.1 low and

full speed

■

Ethernet port: 10/100Mb/s

SIM card protection

Video line protection

Portable electronics

DESCRIPTION

SOT23-6L

The USBLC6-4SC6 is a monolithic Application

Specific Discrete dedicated to ESD protection of

high speed interfaces, such as USB2.0, Ethernet

links and Video lines.

Its very low line capacitance secures a high level

of signal integrity without compromising in

protecting sensitive chips against the most

stringent characterized ESD strikes.

Figure 1: Functional Diagram

FEATURES

■

4 data lines protection

I/O1

I/O4

■

Protects V_BUS

■

Very low capacitance: 3pF typ.

SOT23-6L package

RoHS compliant

GND

I/O2

V_BUS

I/O3

BENEFITS

■

Very low capacitance between lines to GND for

optimized data integrity and speed

Low PCB space consuming, 9mm² maximum

foot print

■

Enhanced ESD protection

IEC61000-4-2 level 4 compliance guaranteed

at device level, hence greater immunity at

system level

Table 1: Order Code

Part Number

Marking

■

ESD protection of V_BUS. Allows ESD current

flowing to Ground when ESD event occurs on

data line

USBLC6-4SC6

UL46

■

High reliability offered by monolithic integration

Low leakage current for longer operation of

battery powered devices

■

Fast response time

COMPLIES WITH THE FOLLOWING STANDARDS:

Consistent D+ / D- signal balance:

- Best capacitance matching tolerance

I/O to GND = 0.015pF

■

IEC61000-4-2 level4:

15kV (air discharge)

8kV (contact discharge)

- Compliant with USB 2.0 requirements < 1pF

February 2005

REV. 2

1/10

USBLC6-4SC6

Table 2: Absolute Ratings

Symbol

Parameter

Value

Unit

At device level:

IEC61000-4-2 air discharge

IEC61000-4-2 contact discharge

MIL STD883C-Method 3015-6

V_PP

Peak pulse voltage

T_stg

T_j

Storage temperature range

-55 to +150

125

°C

Maximum junction temperature

T_L

Lead solder temperature (10 seconds duration)

260

Table 3: Electrical Characteristics (_Tamb= 25°C)

Value

Symbol

Parameter

Test Conditions

Unit

Min.

Typ. Max.

V_RM

I_RM

Reverse stand-off voltage

Leakage current

V_RM= 5V

µA

Breakdown voltage between V_BUS

and GND

V_BR

V_F

I_R= 1mA

I_R= 10mA

Forward voltage

0.86

I_PP= 1A, t_p= 8/20µs

Any I/O pin to GND

V_CL

Clamping voltage

I_PP= 5A, t_p= 8/20µs

Any I/O pin to GND

C_i/o-GND

∆C_i/o-GND

C_i/o-i/o

V_R= 1.65V

Capacitance between I/O and GND

Capacitance between I/O

0.015

1.85

0.04

V_R= 1.65V

2.7

∆C_i/o-i/o

2/10

USBLC6-4SC6

Figure 2: Capacitance versus voltage (typical

values)

Figure 3: Line capacitance versus frequency

(typical values)

C(pF)

5.0

V_OSC=30mV_RMS

T_j=25°C

F=1MHz

V_OSC=30mV_RMS

T_j=25°C

4.5

4.0

4.5

V_CC=0V

4.0

3.5

C_O=I/O-GND

V_CC=1.65V

3.0

2.5

2.0

1.5

1.0

C_j=I/O-I/O

2.0

1.5

1.0

0.5

Data line voltage (V)

F(MHz)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

100

1000

Figure 4: Relative variation of leakage current

versus junction temperature (typical values)

Figure 5: Frequency response

USBLC6-4SC6

(50Ω)

0.00

[T ] / I [T =25°C]

100

V_BUS=5V

S21(dB)

-5.00

-10.00

-15.00

T (°C)

F(Hz)

100

125

-20.00

100.0k

1.0M

10.0M

100.0M

1.0G

3/10

USBLC6-4SC6

TECHNICAL INFORMATION

1. SURGE PROTECTION

The USBLC6-4SC6 is particularly optimized to perform surge protection based on the rail to rail topology.

The clamping voltage V_CLcan be calculated as follow :

V_CL+ = V_BUS+ V_Ffor positive surges

_CL- = - V_Ffor negative surges

with: V_F= V_T+ R_d.I_p

(V_Fforward drop voltage) / (V_Tforward drop threshold voltage)

We assume that the value of the dynamic resistance of the clamping diode is typically:

R_d= 1.4Ω and V_T= 1.2V.

For an IEC61000-4-2 surge Level 4 (Contact Discharge: V_g=8kV, R_g=330Ω), V_BUS= +5V, and if in first

approximation, we assume that : I_p= V_g/ R_g= 24A.

So, we find:

_CL+ = +39V

_CL- = -34V

Note: the calculations do not take into account phenomena due to parasitic inductances.

2. SURGE PROTECTION APPLICATION EXAMPLE

If we consider that the connections from the pin V_BUSto V_CCand from GND to PCB GND are done by

two tracks of 10mm long and 0.5mm large; we assume that the parasitic inductances Lw of these tracks

are about 6nH. So when an IEC61000-4-2 surge occurs, due to the rise time of this spike (tr=1ns), the

voltage V_CLhas an extra value equal to Lw.dI/dt.

The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns

The overvoltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24 = 144V

By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping

voltage will be :

_CL+ = +39 + 144 = 183V

_CL- = -34 - 144 = -178V

We can reduce as much as possible these phenomena with simple layout optimization.

It’s the reason why some recommendations have to be followed (see paragraph “How to ensure a good

ESD protection”).

Figure 6: ESD behavior; parasitic phenomena due to unsuitable layout

183V

BUS

ESD

SURGE

POSITIVE

SURGE

V +V

CC F

I/O

tr=1ns

surge >0

surge <0

V + = V +V +Lw

CL BUS F

-V

VI/O

- = -V -Lw

CL F

NEGATIVE

SURGE

-Lw

GND

-178V

4/10

USBLC6-4SC6

3. HOW TO ENSURE A GOOD ESD PROTECTION

While the USBLC6-4SC6 provides a high immunity to ESD surge, an efficient protection depends on the

layout of the board. In the same way, with the rail to rail topology, the track from the V_BUSpin to the power

supply +V_CCand from the V_BUSpin to GND must be as short as possible to avoid overvoltages due to

parasitic phenomena (see figure 6).

It’s often harder to connect the power supply near to the USBLC6-4SC6 unlike the ground thanks to the

ground plane that allows a short connection.

To ensure the same efficiency for positive surges when the connections can’t be short enough, we

recommend to put close to the USBLC6-4SC6, between V_BUSand ground, a capacitance of 100nF to

prevent from these kinds of overvoltage disturbances (see figure 7).

The add of this capacitance will allow a better protection by providing during surge a constant voltage.

The figures 8, 9 and 10 show the improvement of the ESD protection according to the recommendations

described above.

Figure 7: ESD behavior: optimized layout and

add of a capacitance of 100nF

Figure 8: ESD behavior: measurements

conditions (with coupling capacitance)

ESD

SURGE

TEST BOARD

ESD

SURGE

POSITIVE

SURGE

REF2=+V

C=100nF

I/O

+5V

+ = V +V surge >0

VI/O

surge <0

- = -V

NEGATIVE

SURGE

REF1=GND

V -

C=100nF

Figure 9: Remaining voltage after the

USBLC6-4SC6 during positive ESD surge

Figure 10: Remaining voltage after the

USBLC6-4SC6 during negative ESD surge

IMPORTANT:

A main precaution to take is to put the protection device closer to the disturbance source (generally the

connector).

Note: The measurements have been done with the USBLC6-4SC6 in open circuit.

5/10

USBLC6-4SC6

4. CROSSTALK BEHAVIOR

4.1. Crosstalk phenomena

Figure 11: Crosstalk phenomena

R_G1

Line 1

Line 2

₁V_G1

₁₂V_G2

V_G1

R_L1

R_G2

V_G2

α₂

V_G2

₂₁V_G1

R_L2

DRIVERS

RECEIVERS

The crosstalk phenomena are due to the coupling between 2 lines. The coupling factor (β12 or β21)

increases when the gap across lines decreases, particularly in silicon dice. In the example above the

expected signal on load R_L2is α₂V_G2, in fact the real voltage at this point has got an extra value β₂₁V_G1

This part of the V_G1signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2.

This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency

analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage

signal or high load impedance (few kΩ).

Figure 12: Analog crosstalk measurements

TRACKING GENERATOR

SPECTRUM ANALYSER

TEST BOARD

50Ω

+5V

Vin

50Ω

Vout

C=100nF

Figure 12 gives the measurement circuit for the analog application. In usual frequency range of analog

signals (up to 240MHz) the effect on disturbed line is less than -55 dB (please see figure 13).

Figure 13: Analog crosstalk results

USBLC6-4SC6

As the USBLC6-4SC6 is designed to protect high

Aplac 7.70 User: ST Microelectronics Oct 29 2004

0.00

speed data lines, it must ensure a good transmis-

sion of operating signals. The frequency response

(figure 5) gives attenuation information and shows

-30.00

that the USBLC6-4SC6 is well suitable for data

line transmission up to 480 Mbit/s while it works

as a filter for undesirable signals like GSM

-60.00

(900MHz) frequencies, for instance.

-90.00

-120.00

100.0k

1.0M

10.0M

100.0M

1.0G

f/Hz

6/10

USBLC6-4SC6

5. APPLICATION EXAMPLES

Figure 14: USB2.0 port application diagram using USBLC6-4SC6

+ 3.3V

DEVICE-

HUB-

+ 5V

UPSTREAM

TRANSCEIVER

DOWNSTREAM

TRANSCEIVER

R_PU

Protecting

Bus Switch

USB

connector

SW₂

SW₁

BUS

V_BUS

D+

X LS/FS

X HS

X LS/FS -

X HS -

D-

X HS -

GND

R_S

USBLC6-2SC6

X LS/FS

X LS/FS -

R_PD

+ 3.3V

R_PU

DEVICE-

UPSTREAM

TRANSCEIVER

USB

connector

SW₂

SW₁

BUS

V_BUS

D+

X LS/FS

X HS

X LS/FS -

X HS -

X LS/FS -

X HS -

D-

X HS -

GND

R_S

GND

R_S

USBLC6-2P6

X LS/FS

USBLC6-4SC6

X LS/FS -

R_PD

Mode

Low Speed LS

Full Speed FS

High Speed HS

Open

Closed

Open

Closed

Closed then open Open

Figure 15: T1/E1/Ethernet protection

SMP75-8

+V_CC

DATA

100nF

TRANSCEIVER

SMP75-8

7/10

USBLC6-4SC6

6. PSPICE MODEL

Figure 16 shows the PSPICE model of one USBLC6-4SC6 cell. In this model, the diodes are defined by

the PSPICE parameters given in figure 17.

Figure 16: PSPICE model

Lbondsot 23 100m

Lpinsot 23

Lvcc

Rvcc

Vcc

MODEL = Dhigh

Lpinsot 23 Lbondsot 23 100m

io1

Lpinsot 23 Lbondsot 23 100m

io2

io3

io4

MODEL = Dzener

MODEL = Dlow

Lbondsot 23 100m

Lpinsot 23

Lgnd

Rgn d

Lbondsot 23 100m

Note: This simulation model is available only for an ambient temperature of 27°C.

Figure 17: PSPICE parameters

Figure 18: USBLC6-4SC6 PCB layout

considerations

Dlow

Dhigh

Dzener

7.3

Lbondsot23

Lpinsot23

Rgnd

0.564n

0.15n

350m

100p

CJ0

2.4p

20p

D+1

IBV

IKF

2.42

D-1

0.038

55.2p

0.018

2.27f

BUS

3.21p

Lgnd

C_BUS= 100nF

GND

D+2

D-2

ISR

100p

1.62

100p

1.13

100p

1.24

Rvcc

350m

100p

0.3333

Lvcc

0.38

0.6

0.63

0.6

0.42

0.6

USBLC6-4SC6

0.1u

8/10

USBLC6-4SC6

Figure 19: SOT23-6L Package Mechanical Data

DIMENSIONS

Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

REF.

0.90

1.45 0.035

0.10

0.057

0.004

0.051

0.02

0.90

0.35

0.09

2.80

1.50

1.30 0.035

0.50 0.014

0.20 0.004

3.05 0.110

1.75 0.059

0.008

0.120

0.069

0.95

0.037

2.60

0.10

0°

3.00 0.102

0.60 0.004

0.118

0.024

10°

0°

Figure 20: Foot Print Dimensions (in millimeters)

0.60

1.20

0.95

1.10

3.50

2.30

Table 4: Ordering Information

Ordering code

Marking

Package

Weight

16.7 mg

Base qty

Delivery mode

USBLC6-4SC6

UL46

SOT23-6L

3000

Tape & reel

Table 5: Revision History

Date

Revision

Description of Changes

10-Dec-2004

28-Feb-2005

First issue.

Minor layout update. No content change.

9/10

USBLC6-4SC6

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

10/10

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USBLC6-4SC6产品参数

型号:	USBLC6-4SC6
Brand Name：	STMicroelectronics
生命周期：	Active
包装说明：	R-PDSO-G6
针数：	6
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8541.10.00.50
风险等级：	1.38
其他特性：	HIGH RELIABILITY
最小击穿电压：	6 V
配置：	SINGLE
二极管元件材料：	SILICON
二极管类型：	TRANS VOLTAGE SUPPRESSOR DIODE
JESD-30 代码：	R-PDSO-G6
JESD-609代码：	e3
湿度敏感等级：	1
元件数量：	1
端子数量：	6
最高工作温度：	125 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
极性：	UNIDIRECTIONAL
认证状态：	Not Qualified
最大重复峰值反向电压：	5 V
子类别：	Transient Suppressors
表面贴装：	YES
技术：	AVALANCHE
端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
Base Number Matches：	1

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