VN5010AKTR-E全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

当前位置：IC37首页_>V字母起始型号索引_>V字母起始型号索引第268页更新时间：2024-10-25 17:35:56

产品型号VN5010AKTR-E的概述

芯片VN5010AKTR-E的概述 VN5010AKTR-E是一款高性能的集成电路，主要用于电源管理领域，其应用范围广泛，涵盖工业控制、汽车电子及智能家居等多个领域。作为一款N通道功率MOSFET，VN5010AKTR-E通过高效能和可靠性，满足了现代电子产品对功率品质和效率的需求。芯片VN5010AKTR-E的详细参数 VN5010AKTR-E的主要技术参数包括： - 工作电压范围：该芯片能够在60V的电压下稳定工作，适合高电压场合应用。 - 持续导通电流：VN5010AKTR-E的持续导通电流可达到10A，使其能够在高负载环境中稳定工作。 - 脉冲电流能力：此芯片可承受脉冲电流高达30A，适应瞬时高负载需求。 - RDS(on)：该芯片的导通电阻为0.4Ω（典型值），确保在工作时较低的能量损耗。 - 输入控制电压：VN5010AKTR-E支持从3V到15V的输入控制电压，灵活适应...

产品型号VN5010AKTR-E的Datasheet PDF文件预览

VN5010AK-E

High side driver with analog current sense

for automotive applications

Features

Max supply voltage

V_CC

41V

Operating voltage range

Max On-State resistance

Current limitation (typ)

Off state supply current (typ)

V_CC4.5 to 36V

PowerSSO-24

R_ON

I_LIMH

I_S

10 mΩ

65A

– Electrostatic discharge protection

2 µA

Application

■ Main features

■ All types of resistive, inductive and capacitive

– Inrush current active management by

power limitation

loads

– Very low stand-by current

Description

– 3.0v CMOS compatible input

– Optimized electromagnetic emission

– Very low electromagnetic susceptibility

– In compliance with the 2002/95/EC

European directive

The VN5010AK-E is a monolithic device made

using STMicroelectronics VIPower M0-5

technology. It is intended for driving resistive or

inductive loads with one side connected to

■ Diagnostic functions

ground. Active V pin voltage clamp protects the

– Proportional load current sense

– High current sense precision for wide range

currents

– Current sense disable

– Thermal shutdown indication

– Very low current sense leakage

device against low energy spikes (see ISO7637

transient compatibility table). This device

integrates an analog current sense which delivers

a current proportional to the load current

(according to a known ratio) when CS_DIS is

driven low or left open. When CS_DIS is driven

high, the CURRENT SENSE pin is in a high

impedance condition. Output current limitation

protects the device in overload condition. In case

of long overload duration, the device limits the

dissipated power to safe level up to thermal shut-

down intervention. Thermal shut-down with

automatic restart allows the device to recover

normal operation as soon as fault condition

disappears.

■ Protections

– Undervoltage shut-down

– Overvoltage clamp

– Load current limitation

– Self limiting of fast thermal transients

– Protection against loss of ground and loss

of V

– Thermal shut down

– Reverse battery protection (see Application

schematic )

Table 1.

Device summary

Package

Order codes

Tube

Tape and Reel

PowerSSO-24^TM

VN5010AK-E

VN5010AKTR-E

February 2008

Rev 4

1/31

www.st.com

Contents

VN5010AK-E

Contents

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1

2.2

2.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1

GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21

3.1.1

3.1.2

Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 21

Solution 2 : diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 22

3.2

3.3

3.4

Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Maximum demagnetization energy (V_CC=13.5V) . . . . . . . . . . . . . . . . . . . 23

Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1

PowerSSO-24^TMthermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1

5.2

ECOPACK^®packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/31

VN5010AK-E

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Switching (VCC=13V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Current sense (8V<VCC<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3/31

List of figures

VN5010AK-E

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Delay response time between rising edge of ouput current and rising edge of Current Sense

(CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6.

Figure 7.

Figure 8.

Figure 9.

vs. I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

OUT/ISENSE

OUT

Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 11. Off State output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12. High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 14. Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 17. On state resistance vs. T

Figure 18. On state resistance vs. V

case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 20. Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 21.

vs. T

LIMH case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 22. Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 23. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 24. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 25. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 26. Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 27. Maximum turn Off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 28. PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 29. Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 24

Figure 30. PowerSSO-24 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . 25

Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . 25

Figure 32. PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 33. PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 34. PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4/31

VN5010AK-E

Block diagram and pin description

Figure 1.

Block diagram

UNDERVOLTAGE

PwCLAMP

CLAMP

DRIVER

OUTPUT

GND

LIM

DSLIM

LOGIC

Pwr

LIM

INPUT

OVERTEMP.

OUT

CURRENT

SENSE

CS_DIS

Table 2.

Pin function

Name

V_CC

Function

Battery connection.

Power output.

OUTPUT

Ground connection. Must be reverse battery protected by an external

diode/resistor network.

GND

Voltage controlled input pin with hysteresis, CMOS compatible. Controls output

switch state.

INPUT

CURRENT

SENSE

Analog current sense pin, delivers a current proportional to the load current.

Active high CMOS compatible pin, to disable the current sense pin.

CS_DIS

5/31

Block diagram and pin description

Figure 2. Connection diagram (top view)

VN5010AK-E

V_CC

OUTPUT

GND

INPUT

OUTPUT

CURRENT SENSE

CS_DIS

V_CC

TAB = Vcc

Table 3.

Suggested connections for unused and N.C. pins

Connection / Pin

Current Sense

N.C.

Output

Input

CS_DIS

Floating

N.R.⁽¹⁾

Through 10kΩ

To Ground

Through 1kΩ resistor

N.R.

resistor

1. Not recommended.

6/31

VN5010AK-E

Electrical specifications

Figure 3.

Current and voltage conventions

I_S

V_CC

I_OUT

I_CSD

CS_DIS

INPUT

OUTPUT

V_OUT

V_CSD

I_IN

I_SENSE

CURRENT SENSE

GND

V_SENSE

V_IN

I_GND

Note:

= V

- V during reverse battery condition.

OUT CC

2.1

Absolute maximum ratings

Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Exposure to the conditions in this section for extended

periods may affect device reliability. Refer also to the STMicroelectronics SURE Program

and other relevant quality documents.

Table 4.

Symbol

Absolute maximum ratings

Parameter

Value

Unit

V_CC

DC supply voltage

-V_CC

Reverse DC supply voltage

0.3

- I_GNDDC reverse ground pin current

I_OUTDC output current

- I_OUTReverse DC output current

200

Internally

limited

I_IN

DC input current

-1 to 10

200

I_CSD

DC Current Sense disable input current

-I_CSENSEDC reverse CS pin current

7/31

Electrical specifications

VN5010AK-E

Table 4.

Symbol

Absolute maximum ratings (continued)

Parameter

Value

Unit

V_CC-41

+V_CC

V_CSENSECurrent Sense maximum voltage

Maximum switching energy (single pulse)

E_MAX

V_ESD

T_j

609

(L=1.25mH; R_L=0Ω; V_bat=13.5V; T_jstart=150ºC; I_OUT= I_limL(Typ.) )

Electrostatic discharge (Human Body Model: R=1.5KΩ; C=100pF)

- INPUT

4000

2000

Charge device model (CDM-AEC-Q100-011)

Junction operating temperature

Storage temperature

750

-40 to 150

-55 to 150

°C

T_stg

Table 5.

Symbol

Thermal data

Parameter

Max value

0.3

See Figure 29.

Unit

R_thj-caseThermal resistance junction-case (MAX)

R_thj-ambThermal resistance junction-ambient (MAX)

°C/W

8/31

VN5010AK-E

Electrical specifications

2.2

Electrical characteristics

Values specified in this section are for 8V< V < 36V; -40°C< T < 150°C, unless otherwise

stated (for each channel).

Table 6.

Symbol

Power section

Parameter

Test conditions

Min. Typ. Max. Unit

Operating supply

voltage

V_CC

V_USD

V_USDhyst

4.5

3.5

0.5

Undervoltage

shutdown

4.5

Undervoltage

shutdown hysteresis

_OUT= 6A; T_j= 25°C

mΩ

R_ON

On state resistance

I_OUT= 6A; T_j= 150°C

V_clampClamp voltage

I_CC= 20 mA

Off State; V_CC= 13V; T_j= 25°C;

V_IN=V_OUT=V_SENSE=V_CSD=0V

I_S

I_L(off)

V_F

Supply current

2⁽¹⁾

5⁽¹⁾

µA

V_IN=V_OUT=0V; V_CC= 13V; T_j= 25°C

V_IN=V_OUT=0V; V_CC= 13V; T_j= 125°C

0.01

Off state output

current

Output - V_CCdiode

voltage

-I_OUT= 10A; T_j= 150°C

0.7

1. PowerMOS leakage included.

Table 7.

Symbol

Switching (V =13V)

Parameter

Test conditions

R_L= 2.6Ω (see Figure 8.)

Min.

Typ.

Max. Unit

t_d(on)

t_d(off)

Turn-On delay time

Turn-Off delay time

µs

Turn-On voltage

slope

See

Figure 20

(dV_OUT/dt)_on

(dV_OUT/dt)_off

W_ON

R_L= 2.6Ω

V/ µs

Turn-Off voltage

slope

See

Figure 22

R_L= 2.6Ω

Switching energy

losses during t_won

R_L= 2.6Ω (see Figure 8.)

1.5

0.8

Switching energy

losses during t_woff

W_OFF

9/31

Electrical specifications

VN5010AK-E

Table 8.

Symbol

Logic input

Parameter

Test conditions

Min. Typ. Max. Unit

V_IL

I_IL

Input low level voltage

Low level input current

Input high level voltage

High level input current

0.9

µA

V_IN= 0.9V

V_IN= 2.1V

V_IH

I_IH

2.1

µA

V_I(hyst)Input hysteresis voltage

V_ICLInput clamp voltage

0.25

5.5

I_IN= 1mA

I_IN= -1mA

-0.7

V_CSDLCS_DIS low level voltage

I_CSDLLow level CS_DIS current

V_CSDHCS_DIS high level voltage

I_CSDHHigh level CS_DIS current

0.9

µA

V_CSD= 0.9V

V_CSD= 2.1V

2.1

µA

V_CSD(hyst)CS_DIS hysteresis voltage

0.25

5.5

_CSD= 1mA

V_CSCLCS_DIS clamp voltage

I_CSD= -1mA

-0.7

(1)

Table 9.

Symbol

Protections and diagnostics

Parameter

Test conditions

Min.

Typ.

Max. Unit

_CC= 13V

I_limH

Short circuit current

5V<V_CC<36V

V_CC= 13V;

Short circuit current during

thermal cycling

I_limL

T_R<T_j<T_TSD

T_TSDShutdown temperature

150

175

200

°C

T_R

Reset temperature

T_RS+1 T_RS+5

T_RS

Thermal reset of STATUS

135

T_HYSTThermal hysteresis (T_TSD-T_R)

V_DEMAGTurn-Off output voltage clamp I_OUT=2A; V_IN=0; L=6mH

V_CC

-41

V_CC

-46

V_CC

-52

Output voltage drop

limitation

I_OUT=0.5A (see Figure 9.);

V_ON

T_j= -40°C...+150°C

1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related

diagnostic signals must be used together with a proper software strategy. If the device is subjected to

abnormal conditions, this software must limit the duration and number of activation cycles.

10/31

VN5010AK-E

Electrical specifications

Table 10. Current sense (8V<V <16V)

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

I_OUT= 0.25A;

V_SENSE=0.5V;V_CSD=0V;

K₀

I_{OUT SENSE}

2770 5490 8220

T_j= -40°C...150°C

I_OUT= 6A; V_SENSE=0.5V; V_CSD=0V;

T_j= -40°C...150°C

3610 4580 5630

3930 4580 5230

K₁

I_OUT/I_SENSE

I_OUT= 6A; V_SENSE=0.5V; V_CSD=0V;

T_j= 25°C...150°C

I_OUT= 6A; V_SENSE= 0.5V;

V_CSD= 0V;

Current sense ratio

drift

(1)

dK₁/K₁

-8

T_J= -40 °C to 150 °C

I_OUT= 10A; V_SENSE=4V; V_CSD=0V;

T_j=-40°C...150°C

4000 4570 5220

4180 4570 4960

K₂

I_OUT/I_SENSE

I_OUT= 10A; V_SENSE=4V; V_CSD=0V;

T_j=25°C...150°C

I_OUT= 10A; V_SENSE= 4V;

V_CSD=0V;

Current sense ratio

drift

(1)

dK₂/K₂

-5

T_J= -40 °C to 150 °C

I_OUT= 25A; V_SENSE=4V; V_CSD=0V;

T_j= -40°C...150°C

4480 4660 4980

4500 4660 4820

K₃

I_OUT/I_SENSE

I_OUT= 25A; V_SENSE=4V; V_CSD=0V;

T_j= 25°C...150°C

I_OUT= 25A; V_SENSE= 4V;

V_CSD=0V;

Current sense ratio

drift

(1)

dK₃/K₃

-3

T_J= -40 °C to 150 °C

I_OUT= 0A; V_SENSE=0V;

V_CSD= 5V; V_IN=0V; T_j= -40°C...150°C

V_CSD= 0V; V_IN=5V; T_j= -40°C...150°C

µA

Analog sense

leakage current

I_SENSE0

I_OUT= 2A; V_SENSE=0V;

V_CSD=5V; V_IN=5V; T_j= -40°C...150°C

µA

Openload On state

current detection

threshold

I_OL

V_IN= 5V, I_SENSE= 5 µA

I_OUT=15A; V_CSD=0V;

Max analog sense

output voltage

V_SENSE

Analog sense output

voltage in

overtemperature

condition

V_SENSEH

V_CC= 13V; R_SENSE= 3.9KΩ

Analog sense output

current in

overtemperature

condition

I_SENSEH

V_CC= 13V; V_SENSE= 5V

11/31

Electrical specifications

Table 10. Current sense (8V<V <16V) (continued)

VN5010AK-E

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

V_SENSE<4V, 1.5A<Iout<25A

Delay response time

t_DSENSE1Hfrom falling edge of

CS_DIS pin

100

µs

I_SENSE= 90% of I_{SENSE max}

(see Figure 4.)

V_SENSE<4V, 1.5A<Iout<25A

Delay response time

t_DSENSE1Lfrom rising edge of

CS_DIS pin

I_SENSE= 10% of I_{SENSE max}

(see Figure 4.)

V_SENSE<4V, 1.5A<Iout<25A

Delay response time

t_DSENSE2Hfrom rising edge of

INPUT pin

270 500

I_SENSE= 90% of I_{SENSE max}

(see Figure 4.)

Delay response time

between rising edge

of output current and

rising edge of current

sense

V_SENSE< 4V,

I_SENSE= 90% of I_SENSEMAX,

I_OUT= 90% of I_OUTMAX

I_OUTMAX=15A (see Figure 5)

∆

310

µs

DSENSE2H

V_SENSE<4V, 1.5A<Iout<25A

Delay response time

t_DSENSE2Lfrom falling edge of

INPUT pin

100 250

I_SENSE=10% of I_{SENSE max}

(see Figure 4.)

1. Parameter guaranteed by design; it is not tested.

Figure 4.

Current sense delay characteristics

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

t_DSENSE2Ht_DSENSE1L

t_DSENSE1H

t_DSENSE2L

12/31

VN5010AK-E

Figure 5.

Electrical specifications

Delay response time between rising edge of ouput current and rising

edge of Current Sense (CS enabled)

∆t

DSENSE2H

OUT

OUTMAX

90% I

OUTMAX

SENSE

SENSEMAX

90% I

SENSEMAX

13/31

Electrical specifications

Figure 6.

VN5010AK-E

vs. I

(see Table 10. for details)

OUT SENSE

OUT

OUT SENSE

6000

5500

5000

max Tj = -40°C to 150°C

max Tj= 25°C to 150°C

min Tj= 25°C to 150°C

typical value

4500

4000

3500

3000

min Tj= -40°C to 150°C

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

(A)

OUT

Figure 7.

Maximum current sense ratio drift vs load current

dk/k(%)

-5

-10

-15

I_OUT(A)

Note:

Parameter guaranteed by design; it is not tested.

14/31

VN5010AK-E

Electrical specifications

Sense (V_CSD=0V) ⁽¹⁾

Table 11. Truth table

Conditions

Input

Output

Normal operation

Nominal

Overtemperature

Undervoltage

V_SENSEH

Short circuit to GND

0 if T_j< T_TSD

(R^sc≤10 mΩ)

V_SENSEHif T_j> T_TSD

Short circuit to V_CC

< Nominal

Negative output voltage clamp

1. If the V_CSDis high, the SENSE output is at a high impedance, its potential depends on leakage currents

and external circuit.

Figure 8.

Switching characteristics

OUT

t_Won

80%

Woff

90%

/dt

OUT (off)

OUT (on)

10%

INPUT

d(on)

d(off)

Figure 9.

Output voltage drop limitation

Vcc-Vout

Tj=150 C

Tj=25 C

Tj=-40 C

Von

Iout

Von/Ron(T)

15/31

Electrical specifications

Table 12. Electrical transient requirements

VN5010AK-E

Test levels ⁽¹⁾

ISO 7637-2:

2004(E)

Number of

pulses or

test times

Burst cycle/pulse

repetition time

Delays and

impedance

III

Test pulse

-75V

+37V

-100V

+75V

-6V

-100V

+50V

-150V

+100V

-7V

5000 pulses

0.5 s

0.2 s

5 s

2 ms, 10 Ω

50 µs, 2 Ω

5 s

90 ms

100 ms

0.1 µs, 50 Ω

100 ms, 0.01Ω

400 ms, 2 Ω

1 pulse

5b ⁽²⁾

+65V

+87V

Test level results⁽¹⁾

ISO 7637-2:

2004(E)

III

Test pulse

5b ⁽²⁾

1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.

2. Valid in case of external load dump clamp: 40V maximum referred to ground.

Class

Contents

All functions of the device are performed as designed after exposure to disturbance.

One or more functions of the device are not performed as designed after exposure to

disturbance and cannot be returned to proper operation without replacing the device.

16/31

VN5010AK-E

Figure 10. Waveforms

Electrical specifications

NORMAL OPERATION

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

UNDERVOLTAGE

USDhyst

USD

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

SHORT TO V

INPUT

CS_DIS

LOAD VOLTAGE

LOAD CURRENT

SENSE CURRENT

<Nominal

OVERLOAD OPERATION

TSD

INPUT

CS_DIS

LIMH

LIML

LOAD CURRENT

SENSE CURRENT

SENSEH

thermal cycling

SHORTED LOAD

current

limitation

power

limitation

NORMAL LOAD

17/31

Electrical specifications

VN5010AK-E

2.3

Electrical characteristics curves

Figure 11. Off State output current

Figure 12. High level input current

Iloff (uA)

0.7

Iih (uA)

4.5

0.6

Vin=2.1V

Off state

0.5

0.4

0.3

0.2

0.1

Vcc=13V

Vin=Vout=0V

3.5

2.5

1.5

0.5

-50

-25

100

125

150

175

-50

-25

100

125

150

175

Tc (°C )

Figure 13. Input clamp voltage

Figure 14. Input low level

Vicl (V)

Vil (V)

6.8

1.8

1.6

1.4

1.2

Iin=1mA

6.6

6.4

6.2

5.8

5.6

5.4

5.2

0.8

0.6

0.4

0.2

-50

-25

100

-50

-25

100

125

Tc (°C )

Figure 15. Input high level

Figure 16. Input hysteresis voltage

Vih (V)

Vihyst (V)

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

3.5

2.5

1.5

0.5

-50

-25

100

-50

-25

100

125

Tc (°C )

18/31

VN5010AK-E

Electrical specifications

Figure 17. On state resistance vs. T

Figure 18. On state resistance vs. V

case

Ron (mOhm)

Io ut=6A

Vcc=13V

Tc=150°C

Tc=125°C

Tc=25°C

Tc=-40°C

175

-50

-25

100

125

150

175

Vcc (V)

Tc (°C )

Figure 19. Undervoltage shutdown

Figure 20. Turn-On voltage slope

Vusd (V)

dVout/dt(on) (V/ms)

1000

900

Vcc=13V

RI=2.6Ohm

800

700

600

500

400

300

200

100

-50

-25

100

125

150

-50

-25

100

125

150

Tc (°C )

Figure 21. I

vs. T

Figure 22. Turn-Off voltage slope

LIMH

case

Ilimh (A)

dVout/dt(off) (V/ms)

1000

900

Vcc=13V

RI=2.6Ohm

Vcc=13V

800

700

600

500

400

300

200

100

-50

-25

100

125

150

-50

-25

100

125

150

Tc (°C )

19/31

Electrical specifications

VN5010AK-E

Figure 23. CS_DIS high level voltage

Figure 24. CS_DIS clamp voltage

Vcsdh (V)

Vcsdcl (V)

3.5

7.5

Ic s d =1mA

2.5

6.5

1.5

5.5

0.5

4.5

-50

-25

100

125

150

175

-50

-25

100

125

150

175

Tc (°C )

Figure 25. CS_DIS low level voltage

Vcsdl (V)

3.5

2.5

1.5

0.5

-50

-25

100

125

150

175

Tc (°C )

20/31

VN5010AK-E

Application information

Figure 26. Application schematic

+5V

prot

CS_DIS

IINPUT

prot

OUTPUT

CURRENT SENSE

prot

GND

SENSE

GND

ext

3.1

GND protection network against reverse battery

3.1.1

Solution 1 : resistor in the ground line (R

only)

GND

This can be used with any type of load.

The following is an indication on how to dimension the R

resistor.

GND

≤600mV / (I

GND

S(on)max

≥ (−V ) / (-I

)

GND

where -I

is the DC reverse ground pin current and can be found in the absolute

GND

maximum rating section of the device datasheet.

Power Dissipation in R

(when V <0: during reverse battery situations) is:

GND

P = (-V ) / R

GND

This resistor can be shared amongst several different HSDs. Please note that the value of

this resistor should be calculated with formula (1) where I

maximum on-state currents of the different devices.

becomes the sum of the

S(on)max

Please note that if the microprocessor ground is not shared by the device ground then the

will produce a shift (I * R ) in the input thresholds and the status output

GND

S(on)max

GND

values. This shift will vary depending on how many devices are ON in the case of several

high side drivers sharing the same R

GND

If the calculated power dissipation leads to a large resistor or several devices have to share

the same resistor then ST suggests to utilize Solution 2 (see below).

21/31

Application information

VN5010AK-E

3.1.2

Solution 2 : diode (D

) in the ground line

GND

A resistor (R

inductive load.

=1kΩ) should be inserted in parallel to D if the device drives an

GND

This small signal diode can be safely shared amongst several different HSDs. Also in this

case, the presence of the ground network will produce a shift (≈ 600mV) in the input

threshold and in the status output values if the microprocessor ground is not common to the

device ground. This shift will not vary if m_.ore than one HSD shares the same diode/resistor

network.

3.2

3.3

Load dump protection

D is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the

max DC rating. The same applies if the device is subject to transients on the V line

that are greater than the ones shown in the ISO 7637-2: 2004(E) table.

MCU I/Os protection

If a ground protection network is used and negative transient are present on the V line,

the control pins will be pulled negative. ST suggests to insert a resistor (R ) in line to

prot

prevent the µC I/Os pins to latch-up.

The value of these resistors is a compromise between the leakage current of µC and the

current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC

I/Os.

-V

≤R

≤(V

-V -V

) / I

CCpeak latchup

prot

OHµC IH GND IHmax

Calculation example:

For V

= - 100V and I

≥ 20mA; V

≥ 4.5V

CCpeak

latchup

OHµC

5kΩ ≤R

≤180kΩ

prot

Recommended values: R

=10kΩ, C

=10nF.

EXT

prot

22/31

VN5010AK-E

Application information

3.4

Maximum demagnetization energy (V_CC=13.5V)

Figure 27. Maximum turn Off current versus load inductance

100

0,1

L (mH)

100

A: T

= 150°C single pulse

jstart

B: T

C: T

= 100°C repetitive pulse

= 125°C repetitive pulse

jstart

V , I

Demagnetization

Note:

Values are generated with R =0 Ω.

In case of repetitive pulses, T

(at beginning of each demagnetization) of every pulse

jstart

must not exceed the temperature specified above for curves B and C.

23/31

Package and PCB thermal data

VN5010AK-E

Package and PCB thermal data

4.1

PowerSSO-24^TMthermal data

Figure 28. PowerSSO-24^TMPC board

Note:

Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4

th th

area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),

Copper areas: from minimum pad lay-out to 8cm ).

Figure 29. R

Vs. PCB copper area in open box free air condition

thj-amb

RTHj_amb(°C/W)

PCB Cu heatsink area (cm^2)

24/31

VN5010AK-E

Package and PCB thermal data

Figure 30. PowerSSO-24^TMthermal impedance junction ambient single pulse

ZTH (°C/W)

1000

Footprint

100

2 cm

8 cm

0,1

0,01

1E-04 0,001 0,01

0,1

100 1000

Time (s)

Equation 1: pulse calculation formula

= R

⋅ δ + Z

(1 – δ)

THδ

THtp

where δ = t /T

_TM(a)

Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24

a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded

protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

25/31

Package and PCB thermal data

VN5010AK-E

Table 13. Thermal parameters

Area/island (cm²)

Footprint

0.08

0.16

R1 (°C/W)

R2 (°C/W)

R3 (°C/W)

R4 (°C/W)

7.7

R5 (°C/W)

R6 (°C/W)

C1 (W.s/°C)

C2 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

C5 (W.s/°C)

C6 (W.s/°C)

0.002

0.025

0.75

2.2

26/31

VN5010AK-E

Package and packing information

5.1

ECOPACK^®packages

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a Lead-free second-level interconnect. The category of

Second-Level Interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

Figure 32. PowerSSO-24™ package dimensions

27/31

Package and packing information

VN5010AK-E

Table 14. PowerSSO-24™ mechanical data

Millimeters

Typ.

Symbol

Min.

2.15

Max.

2.47

2.40

0.075

0.51

0.32

10.50

7.6

0.33

0.23

10.10

7.4

0.8

8.8

0.1

0.06

10.5

0.4

10.1

0.55

0.85

10deg

4.7

4.1

6.5

7.1

28/31

VN5010AK-E

Package and packing information

5.2

Packing information

Figure 33. PowerSSO-24^TMtube shipment (no suffix)

Base Q.ty

Bulk Q.ty

Tube length ( 0.5)

1225

532

3.5

13.8

0.6

C ( 0.1)

All dimensions are in mm.

Figure 34. PowerSSO-24^TMtape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base Q.ty

1000

330

1.5

Bulk Q.ty

A (max)

B (min)

C ( 0.2)

G (+ 2 / -0)

N (min)

T (max)

20.2

24.4

100

30.4

TAPE DIMENSIONS

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb 1986

Tape width

Tape Hole Spacing

Component Spacing

Hole Diameter

Hole Position

P0 ( 0.1)

D ( 0.05)

D1 (min)

F ( 0.1)

K (max)

P1 ( 0.1)

1.55

1.5

11.5

2.85

Compartment Depth

Hole Spacing

End

All dimensions are in mm.

Start

Top

cover

tape

No components Components

500mm min

No components

500mm min

Empty components pockets

saled with cover tape.

User direction of feed

29/31

Revision history

VN5010AK-E

Revision history

Table 15. Document revision history

Date

Revision

Changes

24-Jan-2006

Initial release.

Reformatted and restructured.

09-Feb-2007

Added Contents, List of tables and List of figures.

Added Section 3.4: Maximum demagnetization energy (V_CC=13.5V).

Document reformatted and restructured.

Table 4: Absolute maximum ratings : corrected E_MAXvalue from 506

to 609 mJ.

Updated Table 10: Current sense (8V<VCC<16V) :

– changed t_DSENSE2Hmax value from 600 to 500 µs.

– added dk1/k1, dk2/k2, dk3/k3, ∆t_{DSEN 2H}, I_OLparameters.

Added Figure 5: Delay response time between rising edge of ouput

current and rising edge of Current Sense (CS enabled).

13-Dec-2007

Updated Figure 6: IOUT/ISENSE vs. IOUT (see Table 10. for

details).

Added Figure 7: Maximum current sense ratio drift vs load current.

Table 12: Electrical transient requirements : updated test level values

III and IV for test pulse 5b and notes.

Figure 31: Thermal fitting model of a double channel HSD in

PowerSSO-24^TM: added note.

Corrected typing error in Table 10: Current sense (8V<VCC<16V) :

12-Feb-2008

changed I_OLtest condition from V_IN= 0V to V_IN= 5V.

30/31

VN5010AK-E

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no

liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this

document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products

or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such

third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS

OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT

RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING

APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,

DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE

GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void

any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any

liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

31/31

VN5010AKTR-E相关文章

配单直通车

深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

柒号芯城电子商务（深圳）有限公司服务专线: 0755-83209937 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

深圳市中利达电子科技有限公司服务专线: 0755-83200645/13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

VN5010AKTR-E产品参数

型号:	VN5010AKTR-E
Brand Name：	STMicroelectronics
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	STMICROELECTRONICS
零件包装代码：	SOIC
包装说明：	POWERSSO-24
针数：	24
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	18 weeks
风险等级：	5.14
Is Samacsys：	N
内置保护：	TRANSIENT; OVER CURRENT; OVER VOLTAGE; THERMAL; UNDER VOLTAGE
驱动器位数：	1
接口集成电路类型：	BUFFER OR INVERTER BASED PERIPHERAL DRIVER
JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e3
长度：	10.3 mm
湿度敏感等级：	3
功能数量：	1
端子数量：	24
输出电流流向：	SINK
最大输出电流：	0.003 A
标称输出峰值电流：	65 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	HSSOP
封装等效代码：	SOP24,.4
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, SHRINK PITCH
峰值回流温度（摄氏度）：	260
电源：	8/36 V
认证状态：	Not Qualified
座面最大高度：	2.47 mm
子类别：	Peripheral Drivers
最大供电电压：	36 V
最小供电电压：	4.5 V
标称供电电压：	13 V
表面贴装：	YES
技术：	CMOS
端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING
端子节距：	0.8 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
断开时间：	65 µs
接通时间：	35 µs
宽度：	7.5 mm
Base Number Matches：	1

电子百科

产品导航

产品型号VN5010AKTR-E的概述

产品型号VN5010AKTR-E的Datasheet PDF文件预览

VN5010AKTR-E相关产品

VN5010AKTR-E相关文章

IC37:专业IC行业平台