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产品型号W133HTR的概述

W133HTR芯片概述 W133HTR是一款专为多种应用设计的高性能微控制器芯片。它结合高集成度和灵活性,适用于嵌入式系统、消费电子以及工业控制等多种领域。该芯片以其高度的计算能力和低功耗特性而著称,使其在特定应用中能够展现出优异的性能表现。 W133HTR的详细参数 W133HTR采用了现代化的微处理器架构,具有以下主要技术参数: - 工作频率:最高可达100 MHz,支持高效的数据处理能力。 - 存储容量: - FLASH存储:512 KB - SRAM存储:64 KB - 输入/output (I/O) 引脚:多达32个通用I/O引脚,可以用于多种外设连接。 - ADC(模数转换器):集成12位ADC,支持多通道输入,适合电压监测和传感器数据采集。 - PWM(脉宽调制)通道:4个独立PWM输出,广泛应用于马达控制和LED调光等领域。 - 通信接口:包含多个UART、SP...

产品型号W134的Datasheet PDF文件预览

W134M/W134S  
Direct Rambus™ Clock Generator  
Features  
Overview  
• Differential clock source for Direct Rambus™ memory  
subsystem for up to 800-MHz data transfer rate  
• Provide synchronizationflexibility: the Rambus®Chan-  
nel can optionally be synchronous to an external sys-  
tem or processor clock  
The Cypress W134M/W134S provides the differential clock  
signals for a Direct Rambus memory subsystem. It includes  
signals to synchronize the Direct Rambus Channel clock to an  
external system clock but can also be used in systems that do  
not require synchronization of the Rambus clock.  
• Power managed output allows Rambus Channel clock  
to be turned off to minimize power consumption for  
mobile applications  
• Works with Cypress CY2210, W133, W158, W159, W161,  
and W167 to support Intel® architecture platforms  
Key Specifications  
Supply Voltage:...................................... V = 3.3V±0.165V  
DD  
Operating Temperature: ................................... 0°C to +70°C  
Input Threshold: .................................................. 1.5V typical  
• Low-power CMOS design packaged in a 24-pin, 150-mil  
SSOP package  
Maximum Input Voltage:.........................................V +0.5V  
DD  
Maximum Input Frequency:..................................... 100 MHz  
Output Duty Cycle: .................................. 40/60% worst case  
Output Type:............................Rambus signaling level (RSL)  
Block Diagram  
Pin Configuration  
REFCLK  
VDDIR  
REFCLK  
VDD  
1
2
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
S0  
PLL  
MULT0:1  
S1  
3
VDD  
GND  
CLK  
NC  
GND  
4
GND  
5
PCLKM  
SYNCLKN  
GND  
6
7
CLKB  
GND  
VDD  
MULT0  
MULT1  
GND  
CLK  
Output  
Logic  
Phase  
Alignment  
PCLKM  
8
CLKB  
VDD  
9
SYNCLKN  
VDDIPD  
STOPB  
PWRDNB  
10  
11  
12  
Test  
Logic  
S0:1  
STOPB  
Direct Rambus is a trademark and Rambus is a registered trademark of Rambus Inc.  
Intel is a registered trademark of Intel Corporation.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
February 18, 2000, rev. *A  
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W134M/W134S  
Pin Definitions  
Pin  
No.  
Pin  
Type  
Pin Name  
Pin Description  
REFCLK  
2
I
I
Reference Clock Input: Reference clock input, normally supplied by a system  
frequency synthesizer (Cypress W133).  
PCLKM  
6
Phase Detector Input: The phase difference between this signal and SYNCLKN  
is used to synchronize the Rambus Channel Clock with the system clock. Both  
PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory con-  
troller. If Gear Ratio Logic is not used, this pin would be connected to Ground.  
SYNCLKN  
7
I
Phase Detector Input: The phase difference between this signal and PCLKM is  
used to synchronize the Rambus Channel Clock with the system clock. Both  
PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory con-  
troller. If Gear Ratio Logic is not used, this pin would be connected to Ground.  
STOPB  
11  
12  
I
I
Clock Output Enable: When this input is driven to active LOW, it disables the  
differential Rambus Channel clocks.  
PWRDNB  
Active LOW Power-Down: When this input is driven to active LOW, it disables the  
differential Rambus Channel clocks and places the W134M/W134S in power-down  
mode.  
MULT 0:1  
15, 14  
I
PLL Multiplier Select: These inputs select the PLL prescaler and feedback divid-  
ers to determine the multiply ratio for the PLL for the input REFCLK.  
W134S  
W134M  
PLL/REFCLK  
PLL/REFCLK  
MULT0  
MULT1  
4
6
8
4.5  
6
8
0
0
1
1
0
1
1
0
5.333  
5.333  
CLK, CLKB  
S0, S1  
20, 18  
24, 23  
O
I
Complementary Output Clock: Differential Rambus Channel clock outputs.  
Mode Control Input: These inputs control the operating mode of the  
W134M/W134S.  
MODE  
Normal  
S0  
0
S1  
0
Output Enable Test  
Bypass  
0
1
1
0
Test  
1
1
NC  
19  
1
-
No Connect  
VDDIR  
VDDIPD  
RefV  
RefV  
Reference for REFCLK: Voltage reference for input reference clock.  
10  
Reference for Phase Detector: Voltage reference for phase detector inputs and  
StopB.  
VDD  
GND  
3, 9, 16, 22  
P
Power Connection: Power supply for core logic and output buffers. Connected to  
3.3V supply.  
4, 5, 8, 13,  
17, 21  
G
Ground Connection: Connect all ground pins to the common system ground  
plane.  
2
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W134M/W134S  
W134M/W134S  
W133  
W158  
W159  
W161  
W167  
Refclk  
Phase  
PLL  
Busclk  
Align  
D
CY2210  
RAC  
RMC  
Pclk  
M
N
4
DLL  
Synclk  
Gear  
Ratio  
Logic  
Figure 1. DDLL System Architecture  
face of the RAC. The DDLL together with the Gear Ratio Logic  
enables users to exchange data directly from the Pclk domain  
to the Synclk domain without incurring additional latency for  
synchronization. In general, Pclk and Synclk can be of different  
frequencies, so the Gear Ratio Logic must select the appropri-  
ate M and N dividers such that the frequencies of Pclk/M and  
Synclk/N are equal. In one interesting example,  
Pclk=133 MHz, Synclk=100 MHz, and M=4 while N=3, giving  
Pclk/M=Synclk/N=33 MHz. This example of the clock wave-  
forms with the Gear Ratio Logic is shown in Figure 2.  
DDLL SystemArchitectureand GearRatio Logic  
Figure 1 shows the Distributed Delay Lock Loop (DDLL) sys-  
tem architecture, including the main system clock source, the  
Direct Rambus clock generator (DRCG), and the core logic  
that contains the Rambus Access Cell (RAC), the Rambus  
Memory Controller (RMC), and the Gear Ratio Logic. (This  
diagram abstractly represents the differential clocks as a sin-  
gle Busclk wire.)  
The purpose of the DDLL is to frequency-lock and phase-align  
the core logic and Rambus clocks (Pclk and Synclk) at the  
RMC/RAC boundary in order to allow data transfers without  
incurring additional latency. In the DDLL architecture, a PLL is  
used to generate the desired Busclk frequency, while a distrib-  
uted loop forms a DLL to align the phase of Pclk and Synclk at  
the RMC/RAC boundary.  
The output clocks from the Gear Ratio Logic, Pclk/M, and  
Synclk/N, are output from the core logic and routed to the  
DRCG Phase Detector inputs. The routing of Pclk/M and Syn-  
clk/N must be matched in the core logic as well as on the  
board.  
After comparing the phase of Pclk/M vs. Synclk/N, the DRCG  
Phase Detector drives a phase aligner that adjusts the phase  
of the DRCG output clock, Busclk. Since everything else in the  
distributed loop is fixed delay, adjusting Busclk adjusts the  
phase of Synclk and thus the phase of Synclk/N. In this man-  
ner the distributed loop adjusts the phase of Synclk/N to match  
that of Pclk/M, nulling the phase error at the input of the DRCG  
Phase Detector. When the clocks are aligned, data can be  
exchanged directly from the Pclk domain to the Synclk do-  
main.  
The main clock source drives the system clock (Pclk) to the  
core logic, and also drives the reference clock (Refclk) to the  
DRCG. For typical Intel architecture platforms, Refclk will be  
half the CPU front side bus frequency. A PLL inside the DRCG  
multiplies Refclk to generate the desired frequency for Busclk,  
and Busclk is driven through a terminated transmission line  
(Rambus Channel). At the mid-point of the channel, the RAC  
senses Busclk using its own DLL for clock alignment, followed  
by a fixed divide-by-4 that generates Synclk.  
Pclk is the clock used in the memory controller (RMC) in the  
core logic, and Synclk is the clock used at the core logic inter-  
Table 1 shows the combinations of Pclk and Busclk frequen-  
cies of greatest interest, organized by Gear Ratio.  
Pclk  
Synclk  
Pclk/M =  
Synclk/N  
Figure 2. Gear Ratio Timing Diagram  
3
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W134M/W134S  
Table 1. Supported Pclk and Busclk Frequencies, by Gear Ratio  
Gear Ratio and Busclk  
Pclk  
2.0  
1.5  
1.33  
1.0  
67 MHz  
267 MHz  
400 MHz  
100 MHz  
133 MHz  
150 MHz  
200 MHz  
300 MHz  
400 MHz  
267 MHz  
400 MHz  
356 MHz  
400 MHz  
StopB  
S0/S1  
W134M/W134S  
W133  
W158  
W159  
W161  
W167  
Refclk  
Phase  
PLL  
Busclk  
Align  
D
CY2210  
RAC  
RMC  
Pclk  
M
N
4
DLL  
Synclk  
Gear  
Ratio  
Logic  
Figure 3. DDLL Including Details of DRCG  
Figure 3 shows more details of the DDLL system architecture,  
including the DRCG output enable and bypass modes.  
directly, by bypassing the Phase Aligner. If PclkM and SynclkN  
are not used, those inputs must be grounded.  
Phase Detector Signals  
Selection Logic  
The DRCG Phase Detector receives two inputs from the core  
logic, PclkM (Pclk/M) and SynclkN (Synclk/N). The M and N  
dividers in the core logic are chosen so that the frequencies of  
PclkM and SynclkN are identical. The Phase Detector detects  
the phase difference between the two input clocks, and drives  
the DRCG Phase Aligner to null the input phase error through  
the distributed loop. When the loop is locked, the input phase  
error between PclkM and SynclkN is within the specification  
Table 2 shows the logic for selecting the PLL prescaler and  
feedback dividers to determine the multiply ratio for the PLL  
from the input Refclk. Divider A sets the feedback and divider  
B sets the prescaler, so the PLL output clock frequency is set  
by: PLLclk=Refclk*A/B.  
Table 2. PLL Divider Selection  
W134M  
W134S  
t
given in Table 14 after the lock time given in the State  
ERR,PD  
Mult0  
Mult1  
A
9
B
2
1
1
3
A
4
B
1
1
1
3
Transition Section.  
0
0
1
1
0
1
1
0
The Phase Detector aligns the rising edge of PclkM to the  
rising edge of SynclkN. The duty cycle of the phase detector  
6
6
input clocks will be within the specification DC  
given in  
IN,PD  
8
8
Table 13. Because the duty cycles of the two phase detector  
input clocks will not necessarily be identical, the falling edges  
of PclkM and SynclkN may not be aligned when the rising edg-  
es are aligned.  
16  
16  
Table 3 shows the logic for enabling the clock outputs, using  
the StopB input signal. When StopB is HIGH, the DRCG is in  
its normal mode, and Clk and ClkB are complementary out-  
puts following the Phase Aligner output (PAclk). When StopB  
is LOW, the DRCG is in the Clk Stop mode, the output clock  
drivers are disabled (set to Hi-Z), and the Clk and ClkB settle  
The voltage levels of the PclkM and SynclkN signals are de-  
termined by the controller. The pin VDDIPD is used as the  
voltage reference for the phase detector inputs and should be  
connected to the output voltage supply of the controller. In  
some applications, the DRCG PLL output clock will be used  
to the DC voltage V  
as given in Table 14. The level of  
X,STOP  
V
is set by an external resistor network.  
X,STOP  
4
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W134M/W134S  
Table 3. Clock Stop Mode Selection  
Table 5. Power-down Mode Selection  
Mode  
Normal  
Clk Stop  
StopB  
Clk  
ClkB  
Mode  
Normal  
PwrDnB  
Clk  
ClkB  
PAclkB  
GND  
1
0
PAclk  
PAclkB  
1
0
PAclk  
GND  
V
V
X,STOP  
X,STOP  
Power-down  
Table 4 shows the logic for selecting the Bypass and Test  
modes. The select bits, S0 and S1, control the selection of  
these modes. The Bypass mode brings out the full-speed PLL  
output clock, bypassing the Phase Aligner. The Test mode  
brings the Refclk input all the way to the output, bypassing both  
the PLL and the Phase Aligner. In the Output Test mode (OE),  
both the Clk and ClkB outputs are put into a high-impedance  
state (Hi-Z). This can be used for component testing and for  
board-level testing.  
Table of Frequencies and Gear Ratios  
Table 6 shows several supported Pclk and Busclk frequencies,  
the corresponding A and B dividers required in the DRCG PLL,  
and the corresponding M and N dividers in the gear ratio logic.  
The column Ratio gives the Gear Ratio as defined Pclk/Synclk  
(same as M and N). The column F@PD gives the divided down  
frequency (in MHz) at the Phase Detector, where  
F@PD=Pclk/M=Synclk/N.  
Table 4. Bypass and Test Mode Selection  
Bypclk  
State Transitions  
The clock source has three fundamental operating states. Fig-  
ure 4 shows the state diagram with each transition labelled A  
through H. Note that the clock source output may NOT be  
glitch-free during state transitions.  
Mode  
S0  
S1  
(int.)  
Gnd  
-
Clk  
PAclk  
Hi-Z  
ClkB  
PAclkB  
Hi-Z  
Normal  
0
0
Output Test (OE)  
Bypass  
0
1
Upon powering up the device, the device can enter any state,  
depending on the settings of the control signals, PwrDnB and  
StopB.  
1
0
PLLclk PLLclk PLLclkB  
Refclk Refclk RefclkB  
Test  
1
1
In Power-down mode, the clock source is powered down with  
the control signal, PwrDnB, equal to 0. The control signals S0  
and S1 must be stable before power is applied to the device,  
and can only be changed in Power-down mode (PwrDnB=0).  
The reference inputs, V  
be grounded during the Power-down mode.  
Table 5 shows the logic for selecting the Power-down mode,  
using the PwrDnB input signal. PwrDnB is active LOW (en-  
abled when 0). When PwrDnB is disabled, the DRCG is in its  
normal mode. When PwrDnB is enabled, the DRCG is put into  
a powered-off state, and the Clk and ClkB outputs are three-  
stated.  
and V  
, may remain on or may  
DDR  
DDPD  
Table 6. Examples of Frequencies, Dividers, and Gear Ratios  
Pclk  
67  
Refclk  
33  
Busclk  
267  
Synclk  
67  
A
8
6
8
4
6
B
1
1
1
1
1
M
2
8
4
4
8
N
2
6
4
2
6
Ratio  
1.0  
F@PD  
33  
100  
100  
133  
133  
50  
300  
75  
1.33  
1.0  
12.5  
25  
50  
400  
100  
67  
67  
267  
2.0  
33  
67  
400  
100  
1.33  
16.7  
V
Turn-On  
M
V
Turn-On  
G
DD  
DD  
J
L
Test  
Normal  
N
B
F
K
A
E
V
Turn-On  
V
Turn-On  
DD  
D
C
DD  
Power-Down  
Clk Stop  
H
Figure 4. Clock Source State Diagram  
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W134M/W134S  
The control signals Mult0 and Mult1 can be used in two ways.  
If they are changed during Power-down mode, then the Power-  
down transition timings determine the settling time of the  
DRCG. However, the Mult0 and Mult1 control signals can also  
be changed during Normal mode. When the Mult control sig-  
nals are hot swappedin this manner, the Mult transition tim-  
ings determine the settling time of the DRCG.  
Table 7. Control Signals for Clock Source States  
Clock  
Source  
Output  
State  
PwrDnB  
StopB  
Buffer  
Ground  
Disabled  
Enabled  
Power-down  
Clock Stop  
Normal  
0
1
1
X
0
1
OFF  
ON  
ON  
In Clock Stop mode, the clock source is on, but the output is  
disabled (StopB asserted). The V  
remain on or may be grounded during the Clk Stop mode. The  
reference input may  
DDPD  
Figure 5 shows the timing diagrams for the various transitions  
between states, and Table 8 specifies the latencies of each  
state transition. Note that these transition latencies assume  
the following:  
V
reference input must remain on during the Clock Stop  
DDR  
mode.  
In Normal mode, the clock source is on, and the output is en-  
abled.  
Refclk input has settled and meets specification shown in  
Table 13.  
Table 7 lists the control signals for each state.  
Mult0, Mult1, S0 and S1 control signals are stable.  
Timing Diagrams  
Figure 5. State Transition Timing Diagrams  
Power-Down Exit and Entry  
PwrDnB  
t
t
POWERDN  
POWERUP  
Clk/ClkB  
Output Enable Control  
t
ON  
t
STOP  
tCLKON  
StopB  
t
CLKOFF  
tCLKSETL  
Clk/ClkB  
Clock output settled within  
50 ps of the phase before  
disabled  
Clock enabled  
and glitch free  
Output clock  
not specified  
glitches may  
occur  
Figure 6. Multiply Transition Timing  
Mult0 and/or Mult1  
t
MULT  
Clk/ClkB  
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W134M/W134S  
Table 8. State Transition Latency Specifications  
Transition Latency  
Transition  
From  
To  
Symbol  
Max.  
Description  
Time from PwrDnB to Clk/ClkB output settled  
A
Power-down  
Normal  
t
t
t
t
t
3 ms  
3 ms  
3 ms  
3 ms  
3 ms  
POWERUP  
(excluding t ).  
DISTLOCK  
C
K
G
H
Power-down  
Power-down  
Clk Stop  
Test  
Time from PwrDnB until the internal PLL and  
clock has turned ON and settled.  
POWERUP  
POWERUP  
POWERUP  
POWERUP  
Time from PwrDnB to Clk/ClkB output settled  
(excluding t  
).  
DISTLOCK  
V
V
ON  
ON  
Normal  
Clk Stop  
Time from V is applied and settled until  
DD  
DD  
DD  
Clk/ClkB output settled (excluding t  
).  
DISTLOCK  
Time from V is applied and settled until  
DD  
internal PLL and clock has turned ON and  
settled.  
M
J
V
ON  
Test  
t
3 ms  
1 ms  
10 ns  
Time from V is applied and settled until  
internal PLL and clock has turned ON and  
settled.  
DD  
POWERUP  
DD  
Normal  
Normal  
t
Time from when Mult0 or Mult1 changed until  
Clk/ClkB output resettled (excluding  
MULT  
t
).  
DISTLOCK  
E
E
Clk Stop  
Clk Stop  
Normal  
Normal  
t
Time from StopB until Clk/ClkB provides  
glitch-free clock edges.  
CLKON  
t
20 cycles Time from StopB to Clk/ClkB output settled to  
within 50 ps of the phase before CLK/CLKB  
was disabled.  
CLKSETL  
F
L
Normal  
Test  
Clk Stop  
Normal  
t
5 ns  
Time from StopB Φ to Clk/ClkB output  
disabled.  
CLKOFF  
t
3 ms  
Time from when S0 or S1 is changed until  
CLK/CLKB output has resettled (excluding  
CTL  
CTL  
t
).  
DISTLOCK  
N
Normal  
Test  
t
3 ms  
1 ms  
Time from when S0 or S1 is changed until  
CLK/CLKB output has resettled (excluding  
t
).  
DISTLOCK  
B,D  
Normal or Clk Stop Power-down  
t
Time from PwrDnB Φ to the device in Power-  
POWERDN  
down.  
Figure 5 shows that the Clk Stop to Normal transition goes  
through three phases. During t , the clock output is not  
50 ps of the phase before the clock output was disabled. At this  
time, the clock output must also meet the voltage and timing  
specifications of Table 14. The outputs are in a high-imped-  
ance state during the Clk Stop mode.  
CLKON  
specified and can have glitches. For t  
< t< t  
, the  
CLKON  
CLKSETL  
clock output is enabled and must be glitch-free. For  
t>t , the clock output phase must be settled to within  
CLKSETL  
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W134M/W134S  
Table 9. Distributed Loop Lock Time Specification  
Symbol  
Min.  
Max.  
Units  
Description  
Time from when Clk/ClkB output is settled to when the phase error between  
t
5
ms  
DISTLOCK  
SynclkN and PclkM falls within the t  
spec in Table 14.  
ERR,PD  
Table 10. Supply and Reference Current Specification  
Parameter  
Description  
Min.  
--  
Max.  
250  
65  
Unit  
µA  
I
I
I
I
Supplycurrent in Power-down state (PwrDnB=0)  
Supplycurrent in Clk Stop state (StopB=0)  
Supplycurrent in Normal state (StopB=1,PwrDnB=1)  
POWERDOWN  
CLKSTOP  
--  
mA  
mA  
µA  
--  
100  
50  
NORMAL  
Current at VDDIR or VDDIPD reference pin in Power-down  
state (PwrDnB=0)  
--  
REF,PWDN  
I
Current at VDDIR or VDDIPD reference pin in Normal or Clk  
Stop state (PwrDnB=1)  
--  
2
mA  
REF,NORM  
Table 11 represents stress ratings only, and functional operation at the maximums is not guaranteed.  
Table 11. Absolute Maximum Ratings  
Parameter  
Description  
Min.  
0.5  
0.5  
Max.  
Unit  
V
V
V
Max. voltage on V with respect to ground  
4.0  
DD, ABS  
I, ABS  
DD  
Max. voltage on any pin with respect ground  
V
+0.5  
V
DD  
Table 12 gives the nominal values of the external components and their maximum acceptable tolerance, assuming Z =28.  
CH  
Table 12. External Component Values  
Parameter  
Description  
Min.  
39  
Max.  
±5%  
Unit  
R
R
C
C
Serial Resistor  
S
P
F
Parallel Resistor  
51  
±5%  
[1]  
Edge Rate Filter Capacitor  
AC Ground Capacitor  
415  
±10%  
0.1 µF  
pF  
470 pF  
±20%  
MID  
Note:  
1. Do not populate CF. Leave pads for future use.  
8
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W134M/W134S  
Table 13. Operating Conditions  
Parameter  
Description  
Min.  
3.135  
0
Max.  
3.465  
70  
Unit  
V
V
Supply Voltage  
DD  
T
Ambient Operating Temperature  
Refclk Input Cycle Time  
°C  
ns  
A
t
t
10  
-
40  
CYCLE,IN  
J,IN  
[2]  
Input Cycle-to-Cycle Jitter  
250  
60  
ps  
DC  
FM  
Input Duty Cycle over 10,000 Cycles  
40  
30  
--  
%t  
CYCLE  
IN  
IN  
Input Frequency of Modulation  
33  
kHz  
[3]  
PM  
Modulation Index for Triangular Modulation  
Modulation Index for Non-Triangular Modulation  
Phase Detector Input Cycle Time at PclkM & SynclkN  
Initial Phase error at Phase Detector Inputs  
Phase Detector Input Duty Cycle over 10,000 Cycles  
0.6  
%
%
ns  
IN  
[5]  
--  
0.5  
t
t
30  
0.5  
25  
1
100  
0.5  
75  
4
CYCLE,PD  
t
t
ERR,INIT  
CYCLE,PD  
DC  
IN,PD  
CYCLE,PD  
t
Input Slew Rate (measured at 20%-80% of input voltage) for PclkM,  
SynclkN, and Refclk  
V/ns  
I,SR  
[4]  
C
Input Capacitance at PclkM, SynclkN, and Refclk  
-
-
-
7
pF  
pF  
pF  
IN,PD  
[4]  
C  
Input Capacitance matching at PclkM and SynclkN  
0.5  
10  
IN,PD  
C
Input Capacitance at CMOS pins (excluding PclkM, SynclkN, and  
IN,CMOS  
[4]  
Refclk)  
V
V
V
V
V
V
V
V
Input (CMOS) Signal Low Voltage  
Input (CMOS) Signal High Voltage  
Refclk input Low Voltage  
-
0.7  
-
0.3  
VDD  
VDD  
IL  
-
0.3  
-
IH  
V
V
IL,R  
DDIR  
DDIR  
Refclk input High Voltage  
0.7  
-
IH,R  
IL,PD  
IH,PD  
DDIR  
DDIPD  
Input Signal Low Voltage for PD Inputs and StopB  
Input Signal High Voltage for PD Inputs and StopB  
Input Supply Reference for Refclk  
Input Supply Reference for PD Inputs  
0.3  
-
V
V
DDIPD  
0.7  
1.235  
1.235  
DDIPD  
3.465  
2.625  
V
V
Notes:  
2. Refclk jitter measured at VDDIR (nom)/2.  
3. If input modulation is used: input modulation is allowed but not required.  
4. Capacitance measured at Freq=1 MHz, DC bias=0.9V and VAC<100 mV.  
5. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which cannot exceed the skew  
generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.  
9
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Table 14. Device Characteristics  
Parameter  
Description  
Min.  
Max.  
3.75  
60  
Unit  
ns  
t
Clock Cycle Time  
2.5  
CYCLE  
J
[6]  
t
Cycle-to-Cycle Jitter at Clk/ClkB  
-
ps  
[6]  
Total Jitter over 2, 3, or 4 Clock Cycles  
-
100  
100  
160  
-
ps  
[7]  
266-MHz Cycle-to-Cycle Jitter  
-
ps  
[7]  
266-MHz Total Jitter over 2, 3, or 4 Clock Cycles  
Phase Aligner Phase Step Size (at Clk/ClkB)  
-
1
ps  
t
t
ps  
STEP  
Phase Detector Phase Error for Distributed Loop Measured at PclkM-  
SynclkN (rising edges) (does not include clock jitter)  
100  
100  
ps  
ERR,PD  
t
PLL Output Phase Error when Tracking SSC  
Output Voltage during Clk Stop (StopB=0)  
Differential Output Crossing-Point Voltage  
100  
1.1  
1.3  
0.4  
-
100  
2.0  
1.8  
0.6  
2.0  
-
ps  
V
ERR,SSC  
V
V
V
X,STOP  
X
V
[8]  
Output Voltage Swing (p-p single-ended)  
V
COS  
V
Output High Voltage  
Output Low voltage  
V
OH  
V
1.0  
12  
-
V
OL  
[9]  
r
Output Dynamic Resistance (at pins)  
50  
OUT  
I
I
Output Current during Hi-Z (S0 = 0, S1 = 1)  
Output Current during Clk Stop (StopB = 0)  
Output Duty Cycle over 10,000 Cycles  
50  
µA  
µA  
OZ  
-
500  
60  
OZ,STOP  
DC  
40  
-
%t  
CYCLE  
t
Output Cycle-to-Cycle Duty Cycle Error  
50  
ps  
DC,ERR  
t t  
Output Rise and Fall Times (measured at 20%80% of output voltage)  
250  
-
500  
100  
ps  
ps  
R, F  
t
Difference between Output Rise and Fall Times on the Same Pin of a  
CR,CF  
Single Device (20%80%)  
Notes:  
6. Output Jitter spec measured at tCYCLE = 2.5 ns.  
7. Output Jitter Spec measured at tCYCLE = 3.75 ns.  
8.  
VCOS = VOHVOL.  
9. rOUT = VO/ IO. This is defined at the output pins.  
Ordering Information  
Package  
Ordering Code  
W134M/W134S  
Name  
Package Type  
H
24-pin SSOP (150 mils)  
Document #: 38-00822-A  
10  
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W134M/W134S  
Layout Example  
+3.3V Supply  
FB  
10 µF  
C40.005 µF  
G
C3  
G
VDDIR  
G
1
2
3
24  
23  
22  
G
G
G
G
G
G
G
4
21  
20  
G
5
6
19  
7
18  
G
G
G
G
G
8
9
10  
11  
12  
17  
46  
15  
14  
G
G
G
VDDIPD  
G
13  
Internal Power Supply Plane  
FB = Dale ILB1206 - 300 (300@ 100 MHz)  
= VIA to GND plane layer  
G
All Bypass cap = 0.1 Ceramic XR7  
11  
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W134M/W134S  
Package Diagram  
24-Pin Small Shrink Outline Package (SSOP, 150 mils)  
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
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配单直通车
W134产品参数
型号:W134
是否Rohs认证: 不符合
生命周期:Transferred
Reach Compliance Code:unknown
风险等级:5.83
JESD-30 代码:R-PDSO-G24
JESD-609代码:e0
端子数量:24
最高工作温度:70 °C
最低工作温度:
封装主体材料:PLASTIC/EPOXY
封装代码:SSOP
封装等效代码:SSOP24,.3
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH
电源:3.3 V
认证状态:Not Qualified
子类别:Clock Generators
最大压摆率:100 mA
标称供电电压:3.3 V
表面贴装:YES
温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING
端子节距:0.635 mm
端子位置:DUAL
Base Number Matches:1
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