W256H供应商报价哪里找芯片批发报价原理和应用中文资料-中国IC网-芯三七

当前位置：IC37首页_>W字母起始型号索引_>W字母起始型号索引第62页更新时间：2024-10-24 09:00:02

产品型号W256H的概述

芯片W256H的概述 W256H是一款广泛应用的高速动态随机存取存储器（DRAM），其主要功能是作为各种电子设备中的存储介质。该芯片使用先进的工艺技术生产，旨在提升电子产品的性能和效率。W256H的设计使其能够在较低的电压下实现快速的数据读写，满足高性能计算设备的需求。由于其高密度和高速度，W256H特别适用于计算机、嵌入式系统及各种消费电子产品中。芯片W256H的详细参数 W256H的主要参数如下： 1. 存储容量：256MB 2. 数据总线宽度：16位 3. 工作电压：3.3V 4. 访问时间：60ns 5. 封装类型：SOJ、TSOP 6. 工作温度范围：-40°C至+85°C 7. 工作频率：最高可达66MHz 8. 功耗：待机功耗低，操作功耗适中 9. 存储技术：使用CMOS技术以减少功耗这些参数展示了W256H作为一款现代存储器芯片的能力，能够支持各种应用场景。芯片...

产品型号W256H的Datasheet PDF文件预览

W256

12 Output Buffer for 2 DDR and 3 SRAM DIMMS

Features

Functional Description

• One input to 12 output buffer/drivers

• Supports up to 2 DDR DIMMs or 3 SDRAM DIMMS

• One additional output for feedback

The W256 is a 3.3V/2.5V buffer designed to distribute

high-speed clocks in PC applications. The part has 12 outputs.

Designers can configure these outputs to support 3 unbuffered

standard SDRAM DIMMs and 2 DDR DIMMs. The W256 can

be used in conjunction with the W250-02 or similar clock

synthesizer for the VIA Pro 266 chipset.

• SMBus interface for individual output control

• Low skew outputs (< 100 ps)

The W256 also includes an SMBus interface which can enable

or disable each output clock. On power-up, all output clocks

are enabled (internal pull-up).

• Supports 266 MHz and 333 MHz DDR SDRAM

• Dedicated pin for power management support

• Space-saving 28-pin SSOP package

Block Diagram

Pin Configuration^[1]

VDD3.5_2.5

FBOUT

BUF_IN

SSOP

Top View

DDR0T_SDRAM0

DDR0C_SDRAM1

FBOUT

*PWR_DWN#

DDR0T_SDRAM0

DDR0C_SDRAM1

VDD3.3_2.5

SEL_DDR*

DDR5T_SDRAM10

DDR5C_SDRAM11

VDD3.3_2.5

GND

DDR4T_SDRAM8

DDR4C_SDRAM9

VDD3.3_2.5

GND

DDR3T_SDRAM6

DDR3C_SDRAM7

GND

SCLK

SDATA

DDR1T_SDRAM2

DDR1C_SDRAM3

GND

SMBus

Decoding

SDATA

DDR1T_SDRAM2

DDR1C_SDRAM3

VDD3.3_2.5

BUF_IN

GND

DDR2T_SDRAM4

DDR2C_SDRAM5

VDD3.3_2.5

DDR2T_SDRAM4

DDR2C_SDRAM5

SCLOCK

Powerdown

Control

PWR_DWN#

DDR3T_SDRAM6

DDR3C_SDRAM7

DDR4T_SDRAM8

DDR4C_SDRAM9

DDR5T_SDRAM10

DDR5C_SDRAM11

SEL_DDR

Note:

1. Internal 100K pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH.

Cypress Semiconductor Corporation

Document #: 38-07256 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised August 30, 2004

W256

Pin Summary

Name

Pins

Description

SEL_DDR

Input to configure for DDR-ONLY mode or STANDARD SDRAM mode.

1 = DDR-ONLY mode.

0 = STANDARD SDRAM mode.

When SEL_DDR is pulled HIGH or configured for DDR-ONLY mode, all the buffers

will be configured as DDR outputs.

Connect VDD3.3_2.5 to a 2.5V power supply in DDR-ONLY mode.

When SEL_DDR is pulled LOW or configured for STANDARD SDRAM output, all

the buffers will be configured as STANDARD SDRAM outputs.

Connect VDD3.3_2.5 to a 3.3V power supply in STANDARD SDRAM mode.

SCLK

SMBus clock input.

SMBus data input.

SDATA

BUF_IN

Reference input from chipset. 2.5V input for DDR-ONLY mode; 3.3V input for

STANDARD SDRAM mode.

FBOUT

Feedback clock for chipset. Output voltage depends on VDD3.3_2.5V.

PWR_DWN#

Active LOW input to enable Power Down mode; all outputs will be pulled LOW.

DDR[0:5]T_SDRAM 3, 7, 12, 19, 23, 27 Clock outputs. These outputs provide copies of BUF_IN. Voltage swing depends

[0,2,4,6,8,10] on VDD3.3_2.5 power supply.

DDR[0:5]C_SDRAM 4, 8, 13, 18, 22, 26 Clock outputs. These outputs provide complementary copies of BUF_IN when

[1,3,5,7,9, 11]

SEL_DDR is active. These outputs provide copies of BUF_IN when SEL_DDR is

inactive. Voltage swing depends on VDD3.3_2.5 power supply.

VDD3.3_2.5

5, 9, 14, 21, 25

6, 11, 17, 20, 24

Connect to 2.5V power supply when W256 is configured for DDR-ONLY mode.

Connect to 3.3V power supply, when W256 is configured for standard SDRAM

mode.

GND

Ground.

Document #: 38-07256 Rev. *C

Page 2 of 9

W256

Serial Configuration Map

Byte 7: Outputs Active/Inactive Register

(1 = Active, 0 = Inactive), Default = Active

• TheSerialbitswillbereadbytheclockdriverinthefollowing

order:

Bit

Bit 7

Bit 6

Pin #

Description

Default

Byte 0 — Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 1 — Bits 7, 6, 5, 4, 3, 2, 1, 0

.–

–

Reserved, drive to 0

19, 18 DDR3T_SDRAM6,

DDR3C_SDRAM7

Byte N — Bits 7, 6, 5, 4, 3, 2, 1, 0

Bit 5

12, 13 DDR2T_SDRAM4,

DDR2C_SDRAM5

• Reserved and unused bits should be programmed to “0”.

• SMBus Address for the W256 is:

Bit 4

Bit 3

Bit 2

–

Reserved, drive to 0

Table 1.

7, 8

DDR1T_SDRAM2,

DDR1C_SDRAM3

R/W

––

Bit 1

Bit 0

–

Reserved, drive to 0

Byte 6: Outputs Active/Inactive Register

(1 = Active, 0 = Inactive), Default = Active

3, 4

DDR0T_SDRAM0,

DDR0C_SDRAM1

Bit Pin #

Description

Reserved, drive to 0

Default

Bit 7

Bit 6

Bit 5

Bit 4

–

Reserved, drive to 0

FBOUT

Bit 3 27, 26 DDR5T_SDRAM10,

DDR5C_SDRAM11

Bit 2

–

Reserved, drive to 0

Bit 1 23, 22 DDR4T_SDRAM8,

DDR4C_SDRAM9

Bit 0

–

Reserved, drive to 0

Document #: 38-07256 Rev. *C

Page 3 of 9

W256

Maximum Ratings

Supply Voltage to Ground Potential..................–0.5 to +7.0V

DC Input Voltage (except BUF_IN)............–0.5V to V_DD+0.5

Storage Temperature ..................................–65°C to +150°C

Static Discharge Voltage............................................>2000V

(per MIL-STD-883, Method 3015)

Operating Conditions^[2]

Parameter

V_DD3.3

V_DD2.5

T_A

Description

Min.

3.135

2.375

Typ.

Max.

3.465

2.625

Unit

Supply Voltage

Operating Temperature (Ambient Temperature)

Output Capacitance

°C

C_OUT

C_IN

Input Capacitance

Electrical Characteristics Over the Operating Range

Parameter

V_IL

Description

Input LOW Voltage

Input HIGH Voltage

Input LOW Current

Input HIGH Current

Output HIGH Current

Test Conditions

Min.

Typ.

Max.

Unit

For all pins except SMBus

0.8

V_IH

I_IL

2.0

V_IN= 0V

µA

I_IH

V_IN= V_DD

I_OH

V_DD= 2.375V

_OUT= 1V

–18

–32

I_OL

Output LOW Current

V_DD= 2.375V

V_OUT= 1.2V

V_OL

V_OH

I_DD

Output LOW Voltage^[3]

Output HIGH Voltage^[3]

Supply Current^[3]

(DDR-Only mode)

I_OL= 12 mA, V_DD= 2.375V

I_OH= –12 mA, V_DD= 2.375V

Unloaded outputs, 133 MHz

0.6

1.7

400

500

I_DD

Supply Current

(DDR-Only mode)

Loaded outputs, 133 MHz

PWR_DWN# = 0

I_DDS

Supply Current

100

µA

V_OUT

Output Voltage Swing

See Test Circuity (Refer to

Figure 1)

0.7

V_DD+ 0.6

V_OC

Output Crossing Voltage

Input Clock Duty Cycle

(V_DD/2)

–0.1

V_DD/2

(V_DD/2)

+0.1

IN_DC

Notes:

2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

3. Parameter is guaranteed by design and characterization. Not 100% tested in production.

Document #: 38-07256 Rev. *C

Page 4 of 9

W256

Switching Characteristics^[4]

Parameter

Name

Operating Frequency

Duty Cycle^[4,5]= t₂÷ t₁

Test Conditions

Min.

Typ.

Max.

Unit

–

180

MHz

–

Measured at 1.4V for 3.3V outputs

Measured at VDD/2 for 2.5V outputs.

IN_DC

–5%

IN_DC+5%

t₃

SDRAM Rising Edge Rate^[4]

SDRAM Falling Edge Rate^[4]

DDR Rising Edge Rate^[4]

Measured between 0.4V and 2.4V

Measured between 2.4V and 0.4V

1.0

0.5

2.50

1.50

V/ns

t₄

t_3d

Measured between 20% to 80% of

output (Refer to Figure 1)

t_4d

DDR Falling Edge Rate^[4]

Output to Output Skew^[4]

Measured between 20% to 80% of

output (Refer to Figure 1)

0.5

1.50

V/ns

t₅

t₆

All outputs equally loaded

100

150

Output t4o Output Skew for

SDRAM^[2]

t₇

t₈

SDRAM Buffer HH Prop. Delay^[4]Input edge greater than 1 V/ns

SDRAM Buffer LLProp. Delay^[4]Input edge greater than 1 V/ns

Switching Waveforms

Duty Cycle Timing

All Outputs Rise/Fall Time

3.3V

2.4V

OUTPUT

0.4V

2.4V

0.4V

Output-Output Skew

OUTPUT

Notes:

4. All parameters specified with loaded outputs.

5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/ns.

Document #: 38-07256 Rev. *C

Page 5 of 9

W256

Switching Waveforms (continued)

SDRAM Buffer HH and LL Propagation Delay

1.5V

INPUT

1.5V

OUTPUT

t₆

t₇

Figure 1 shows the differential clock directly terminated by a

120 Ω resistor.

V_CC

VTR

60Ω

Device

Under

Test

)

Out

R_T=120Ω

Ω

Receiver

Out

VCP

Figure 1. Differential Signal Using Direct Termination Resistor

Document #: 38-07256 Rev. *C

Page 6 of 9

W256

Layout Example Single Voltage

+3.3V Supply or 2.5V Supply

VDD

10 µF

0.005 µF

FB = Dale ILB1206 – 300 (300Ω @ 100 MHz)

µF

C2 = 0.005

Cermaic CapsC1 = 10–22

= VIA to GND plane layer

V =VIA to respective supply plane layer

Note: Each supply plane or strip should have a ferrite bead and capacitors

All bypass caps = 0.1 µF ceramic

Ordering Information

Ordering Code

W256H

Package Type

Operating Range

Commercial

28-pin SSOP

W256HT

28-pin SSOP – Tape and Reel

Commercial

Lead Free

CYW256OXC

CYW256OXCT

28-pin SSOP

Commercial

28-pin SSOP – Tape and Reel

Document #: 38-07256 Rev. *C

Page 7 of 9

W256

Package Drawings and Dimension

28-Lead (5.3 mm) Shrunk Small Outline Package O28

51-85079-*C

Document #: 38-07256 Rev. *C

Page 8 of 9

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

W256

Document History Page

Document Title: W256 12 Output Buffer for 2 DDR and 3 SRAM DIMMS

Document Number: 38-07256

Orig. of

REV.

ECN NO. Issue Date Change

Description of Change

Change from Spec number: 38-01083 to 38-07256

Added 333 MHz for SDRAM

110521

112153

122858

258671

12/04/01

03/01/02

12/19/02

See ECN

SZV

IKA

RBI

Added power requirements to operating conditions information.

Added Lead Free Devices

RGL

Document #: 38-07256 Rev. *C

Page 9 of 9

W256H相关文章

配单直通车

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

柒号芯城电子商务（深圳）有限公司服务专线: 0755-83209937 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

深圳市中利达电子科技有限公司服务专线: 0755-83200645/13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

电子百科

产品导航

产品型号W256H的概述

产品型号W256H的Datasheet PDF文件预览

W256H相关产品

W256H相关文章

IC37:专业IC行业平台