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产品型号W27C020P-70的概述

芯片W27C020P-70的概述 W27C020P-70是一款广泛应用于嵌入式系统中的可编程只读存储器（EPROM）。它由Winbond Electronics Corporation制造，主要用于数据存储和代码存储等场合。由于其相对较低的容量和高可编程性，该芯片在早期计算机、嵌入式系统以及各种电子产品中得到了广泛应用。这款芯片的容量为256Kbit，通常以32K字节为单位划分。芯片的工作电压为5V，并且通常允许通过热编程或紫外线擦写的过程进行数据的重写。这种灵活性使得W27C020P-70在开发和测试阶段颇受欢迎，尤其是对于那些需要频繁更新代码的应用。芯片W27C020P-70的详细参数芯片W27C020P-70的主要技术参数如下： - 容量：256Kbit（32KB） - 数据总线宽度：8位 - 编程电压：12.75V - 擦写电压：UV（紫外线） - 工作电压：4.5V至5...

产品型号W27C020P-70的Datasheet PDF文件预览

Preliminary W27C020

256K ´ 8 ELECTRICALLY ERASABLE EPROM

GENERAL DESCRIPTION

The W27C020 is a high speed, low power Electrically Erasable and Programmable Read Only

Memory organized as 262144 ´ 8 bits that operates on a single 5 volt power supply. The W27C020

provides an electrical chip erase function.

FEATURES

· High speed access time:

70/90/120 nS (max.)

· +14V erase/+12V programming voltage

· Fully static operation

· Read operating current: 30 mA (max.)

· All inputs and outputs directly TTL/CMOS

· Erase/Programming operating current:

compatible

30 mA (max.)

· Three-state outputs

· Standby current: 1 mA (max.)

· Single 5V power supply

· Available packages: 32-pin 600 mil DIP and

PLCC

PIN CONFIGURATIONS

BLOCK DIAGRAM

PGM

Vcc

Vpp

A16

A15

A12

OUTPUT

BUFFER

CONTROL

PGM

A17

A14

A13

32-pin DIP

CORE

DECODER

A11

ARRAY

A17

A10

V_CC

GND

V_PP

GND

PIN DESCRIPTION

M 7

SYMBOL

DESCRIPTION

Address Inputs

Data Inputs/Outputs

A0- A17

Q0- Q7

A14

A13

A11

Chip Enable

32-pin PLCC

A10

Output Enable

Program Enable

PGM

VPP

Program/Erase Supply Voltage

Power Supply

G Q Q Q

3 4 5

VCC

GND

Ground

Publication Release Date: September 1998

Revision A1

- 1 -

Preliminary W27C020

FUNCTIONAL DESCRIPTION

Read Mode

Like conventional UVEPROMs, the W27C020 has two control functions, both of which produce data

at the outputs.

CE is for power control and chip select. OE controls the output buffer to gate data to the output pins.

When addresses are stable, the address access time (TACC) is equal to the delay from CE to output

(TCE), and data are available at the outputs TOE after the falling edge of OE, if TACC and TCE timings

are met.

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,

which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half

an hour), the W27C020 uses electrical erasure. Generally, the chip can be erased within 100 mS by

using an EPROM writer with a special erase algorithm.

Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE = VIL, (0.8V or below

but higher than GND), OE = VIH (2V or above but lower than VCC), A9 = VID (14V), A0 = VIL, and all

other address pins equal VIL and data input pins equal VIH. Pulsing PGM low starts the erase

operation.

Erase Verify Mode

After an erase operation, all of the bytes in the chip must be verified to check whether they have been

successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase

margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE = VIL, and OE =

VIL, PGM = VIH.

Program Mode

Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only

way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP

(12V), VCC = VCP (5V), CE = VIL, OE = VIH, the address pins equal the desired addresses, and the

input pins equal the desired inputs. Pulsing PGM low starts the programming operation.

Program Verify Mode

All of the bytes in the chip must be verified to check whether they have been successfully

programmed with the desired data or not. Hence, after each byte is programmed, a program verify

operation should be performed. The program verify mode automatically ensures a substantial

program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE = VIL,

OE = VIL, and PGM = VIH.

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different

data. When CE = VIH, erasing or programming of non-target chips is inhibited, so that except for the

CE, the W27C020 may have common inputs.

- 2 -

Preliminary W27C020

Standby Mode

The standby mode significantly reduces VCC current. This mode is entered when CE = VIH. In

standby mode, all outputs are in a high impedance state, independent of OE and PGM.

Two-line Output Control

Since EPROMs are often used in large memory arrays, the W27C020 provides two control inputs for

multiple memory connections. Two-line control provides for lowest possible memory power

dissipation and ensures that data bus contention will not occur.

System Considerations

EPROM power switching characteristics require careful device decoupling. System designers are

concerned with three supply current issues: standby current levels (ISB), active current levels (ICC),

and transient current peaks produced by the falling and rising edges of CE. Transient current

magnitudes depend on the device output's capacitive and inductive loading. Two-line control and

proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have

a 0.1 mF ceramic capacitor connected between its VCC and GND. This high frequency, low inherent-

inductance capacitor should be placed as close as possible to the device. Additionally, for every eight

devices, a 4.7 mF electrolytic capacitor should be placed at the array's power supply connection

between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace

inductances.

TABLE OF OPERATING MODES

VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, VCE = 5V, VID = 14V, X = VIH or VIL

MODE

PINS

VCC

VPP

OUTPUTS

PGM

Read

VIL

VIH

VCC VCC DOUT

VCC VCC High Z

Output Disable

Standby (TTL)

Standby (CMOS)

Program

VIH

VCC ±0.3V

VIL

VIH

VIL

VIH

VCP

VCC

VPP DIN

Program Verify

Program Inhibit

Erase

VIL

VPP DOUT

VIH

VCP VPP High Z

VIL

VIH

VIL

VIH

VIL

VID

VCE VPE FF (Hex)

Erase Verify

Erase Inhibit

VIL

VCC

VPE DOUT

VIH

VCE VPE High Z

Product Identifier-

manufacturer

VIL

VHH VCC VCC DA (Hex)

Product Identifier-device

VIL

VIH

VHH VCC VCC 85 (Hex)

Publication Release Date: September 1998

Revision A1

- 3 -

Preliminary W27C020

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER

RATING

-55 to +125

UNIT

°C

Ambient Temperature with Power Applied

Storage Temperature

-65 to +125

°C

Voltage on all Pins with Respect to Ground Except VCC, VPP

and A9 Pins

-0.5 to VCC +0.5

Voltage on VCC Pin with Respect to Ground

Voltage on VPP Pin with Respect to Ground

Voltage on A9 Pin with Respect to Ground

-0.5 to +7

-0.5 to +14.5

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

DC Erase Characteristics

(TA = 25° C ±5° C, VCC = 5.0V ±5%, VHH = 14V)

PARAMETER

SYM.

CONDITIONS

LIMITS

UNI

MIN.

-10

TYP. MAX.

Input Load Current

VCC Erase Current

ILI

VIN = VIL or VIH

ICP

CE = VIL, OE = VIH,

PGM = VIL, A9 = VHH

VPP Erase Current

IPP

CE = VIL, OE = VIH,

PGM = VIL, A9 = VHH

Input Low Voltage

VIL

-0.3

2.4

0.8

5.5

Input High Voltage

VIH

Output Low Voltage (Verify)

Output High Voltage (Verify)

A9 Erase Voltage

VOL

VOH

VID

IOL = 2.1 mA

0.45

IOH = -0.4 mA

2.4

13.75

4.5

14.0

5.0

14.25

5.5

VPP Erase Voltage

VPE

VCE

VCC Supply Voltage (Erase)

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

- 4 -

Preliminary W27C020

CAPACITANCE

(VCC = 5V, TA = 25° C, f = 1 MHz)

PARAMETER

Input Capacitance

SYMBOL

CIN

CONDITIONS

VIN = 0V

MAX.

UNIT

Output Capacitance

COUT

VOUT = 0V

AC CHARACTERISTICS

AC Test Conditions

PARAMETER

CONDITIONS

70 nS

90/120 nS

Input Pulse Levels

0 to 3.0V

5 nS

0.45V to 2.4V

10 nS

Input Rise and Fall Times

Input and Output Timing Reference Level 1.5V/1.5V

0.8V/2.0V

Output Load

CL = 30 pF,

CL = 100 pF,

IOH/IOL = -0.4 mA/2.1 mA IOH/IOL = -0.4 mA/2.1 mA

AC Test Load and Waveforms

+1.3V

(IN914)

3.3K ohm

OUT

100 pF for 90/120 nS (Including Jig and Scope)

30 pF for 70 nS (Including Jig and Scope)

Input/Output

Test Points

2.4V

For 90/120 nS

0.45V

2.0V

0.8V

2.0V

0.8V

Test Point

1.5V

Test Point

3.0V

For 70 nS

1.5V

Publication Release Date: September 1998

Revision A1

- 5 -

Preliminary W27C020

READ OPERATION DC CHARACTERISTICS

(Vcc = 5.0V ±5%)

PARAMETER

SYM.

CONDITIONS

LIMITS

UNIT

MIN.

-5

TYP.

MAX.

Input Load Current

ILI

VIN = 0V to VCC

Output Leakage Current

ILO

ISB

VOUT = 0V to VCC

-10

Standby VCC Current

(TTL input)

1.0

CE = VIH

Standby VCC Current

(CMOS input)

ISB1

ICC

100

CE = VCC ±0.2V

VCC Operating Current

CE = VIL

IOUT = 0 mA

f = 5 MHz

VPP Operating Current

Input Low Voltage

IPP

VPP = VCC

-0.3

2.2

0.8

VIL

Input High Voltage

Output Low Voltage

Output High Voltage

VPP Operating Voltage

VIH

VOL

VOH

VPP

IOL = 2.1 mA

IOH = -0.4 mA

VCC +0.5

0.45

2.4

VCC -0.7

VCC

READ OPERATION AC CHARACTERISTICS

(VCC = 5.0V ±5%, for 70, 90 and 120 nS; TA = 0 to 70° C)

PARAMETER

SYM.

W27C020-70

W27C020-90

W27C020-12

UNIT

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Read Cycle Time

TRC

TCE

TACC

TOE

120

Chip Enable Access Time

Address Access Time

120

Output Enable Access

Time

TDF

TOH

OE High to High-Z Output

Output Hold from Address

Change

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

- 6 -

Preliminary W27C020

DC PROGRAMMING CHARACTERISTICS

(VCC = 5.0V ±5%, TA = 25° C ±5° C)

PARAMETER

SYM.

CONDITIONS

LIMITS

UNIT

MIN.

TYP. MAX.

Input Load Current

ILI

VIN = VIL or VIH

±10

VCC Program Current

ICP

CE = VIL, OE = VIH,

PGM = VIL

VPP Program Current

IPP

CE = VIL, OE = VIH,

PGM = VIL

Input Low Voltage

VIL

-0.3

2.4

0.8

5.5

0.45

Input High Voltage

VIH

Output Low Voltage (Verify)

Output High Voltage (Verify)

A9 Silicon I. D. Voltage

VPP Program Voltage

VOL

VOH

VID

IOL = 2.1 mA

IOH = -0.4 mA

2.4

11.5

11.75

4.5

12.0

12.5

VPP

VCP

12.0 12.25

VCC Supply Voltage (Program)

5.0

5.5

AC PROGRAMMING/ERASE CHARACTERISTICS

(VCC = 5.0V ±5%, TA = 25° C ±5° C)

PARAMETER

SYM.

LIMITS

UNIT

MIN.

2.0

TYP.

MAX.

VPP Setup Time

TVPS

TAS

Address Setup Time

Data Setup Time

TDS

TPWP

TPWE

TDH

100

105

PGM Program Pulse Width

100

105

PGM Erase Pulse Width

Data Hold Time

TOES

TOEV

TDFP

TAH

OE Setup Time

150

Data Valid from OE

OE High to Output High Z

130

Address Hold Time after PGM High

Address Hold Time (Erase)

TAHE

TCES

2.0

CE Setup Time

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

Publication Release Date: September 1998

Revision A1

- 7 -

Preliminary W27C020

TIMING WAVEFORMS

AC Read Waveform

Address

Address Valid

TCE

ACC

High Z

Outputs

Valid Output

High Z

Erase Waveform

Read

Manufacturer

Read

Device

Blank Check

Read Verify

Erase Verify

SID

A9 = 12.0V

SID

Chip Erase

A9 = 14.0V

Others = V

Address

Stable

Address

Stable

A0=V

Address

Stable

Address

Data

A0 = V

Others=V

AHC

ACC

DFP

OUT

Data All One

14.0V

5.0V

VPS

OES

OEV

PWE

CES

PGM

- 8 -

Preliminary W27C020

Timing Waveforms, continued

Programming Waveform

Program

Verify

Read

Verify

Program

Address Stable

Address Valid

Address Stable

Address

Data

DFP

ACC

OUT

Data In Stable

12.0V

5.0V

VPS

CES

OES

OEV

PWP

PGM

Publication Release Date: September 1998

Revision A1

- 9 -

Preliminary W27C020

SMART PROGRAMMING ALGORITHM

Start

Address = First Location

Vcc = 5V

Vpp = 12V

X = 0

Program One 100 S Pulse

Increment X

Yes

X = 25?

Fail

Verify

One Byte

Fail

Verify

One Byte

Pass

Last

Address?

Increment

Address

Yes

Vcc = 5V

Vpp = 5V

Compare

All Bytes to

Fail

Original Data

Pass

Fail

Device

Pass

Device

- 10 -

Preliminary W27C020

SMART ERASE ALGORITHM

Start

X = 0

Vcc = 5V

Vpp = 14V

A9 = 14V; A0 = V

Chip Erase 100 mS Pulse

Address = First Location

Increment X

Fail

Erase

Verify

X = 20?

Pass

Yes

Increment

Address

Last

Address?

Yes

Vcc = 5V

Vpp = 5V

Compare

All Bytes to

FFs (HEX)

Fail

Pass

Device

Fail

Device

Publication Release Date: September 1998

Revision A1

- 11 -

Preliminary W27C020

ORDERING INFORMATION

PART NO.

ACCESS

TIME

POWER SUPPLY

CURRENT MAX.

(mA)

STANDBY VCC

CURRENT MAX.

PACKAGE

(nS)

(mA)

W27C20-70

100

600 mil DIP

32-pin PLCC

W27C020-90

W27C020-12

W27C020P-70

W27C020P-90

W27C020P-12

120

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in

applications where personal injury might occur as a consequence of product failure.

- 12 -

Preliminary W27C020

PACKAGE DIMENSIONS

32-pin P-DIP

Dimension in mm

Min. Nom. Max. Min. Nom. Max.

Dimension in Inches

Symbol

5.33

0.210

0.010

0.150

0.25

3.81

0.41

1.22

0.20

A₁

A₂

0.155 0.160

3.94

0.46

1.27

0.25

41.91

4.06

0.56

0.016 0.018

0.050

0.022

0.054

1.37

0.048

0.36

0.008 0.010 0.014

1.650 1.660

42.16

15.49

0.590 0.600 0.610 14.99 15.24

13.84 13.97 14.10

0.555

0.110

0.545 0.550

0.090 0.100

2.29

3.05

2.54

3.30

2.79

e ₁

E₁

0.140

0.120 0.130

3.56

0.630

0.670 16.00

0.085

17.02

0.650

16.51

e_A

2.16

Notes:

1. Dimensions D Max. & S include mold flash or tie bar burr

2. Dimension E1 does not include interlead flash.

3. Dimensions D & E1 include mold mismatch and are

determined at the mold parting line.

A₁

Base Plane

4. Dimension B1 does not include dambar protrusion/intrusi

5. Controlling dimension: Inches.

6. General appearance spec. should be based on final visu

inspection spec.

Seating Plane

e _A

32-Lead PLCC

H _E

Dimension in Inches

Dimension in mm

Symbol

Min. Nom. Max. Min. Nom. Max.

0.140

3.56

G_D

H_D

0.020

0.105

0.026

0.016

0.008

0.50

2.67

0.66

0.41

0.20

0.110

0.028

0.018

0.010

0.550

0.450

0.050

0.510

0.410

0.590

0.490

0.090

0.115

0.032

0.022

0.014

2.80

0.71

2.93

0.81

0.56

0.35

0.46

0.25

0.547

0.447

0.044

0.490

0.390

0.585

0.485

0.075

0.553

0.453

0.056

0.530

0.430

0.595

0.495

0.095

0.004

13.89

11.35

1.12

14.05

11.51

1.42

13.97

11.43

1.27

12.95

12.45

9.91

13.46

10.92

15.11

12.57

2.41

10.41

14.99

12.45

2.29

14.86

12.32

1.91

0.10

Notes:

1. Dimensions D & E do not include interlead flash.

2. Dimension b1 does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches.

4. General appearance spec. should be based on final

visual inspection sepc.

b ₁

Seating Plane

Publication Release Date: September 1998

Revision A1

- 13 -

Preliminary W27C020

VERSION HISTORY

VERSION

DATE

Sep. 1998

PAGE

DESCRIPTION

Initial Issued

Winbond Electronics (H.K.) Ltd.

Winbond Electronics North America Corp.

Headquarters

Rm. 803, World Trade Square, Tower II, Winbond Memory Lab.

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5796096

123 Hoi Bun Rd., Kwun Tong,

Winbond Microelectronics Corp.

Winbond Systems Lab.

2727 N. First Street, San Jose,

CA 95134, U.S.A.

Kowloon, Hong Kong

TEL: 852-27513100

FAX: 852-27552064

http://www.winbond.com.tw/

Voice & Fax-on-demand: 886-2-7197006

TEL: 408-9436666

FAX: 408-5441798

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

Taipei, Taiwan

TEL: 886-2-7190505

FAX: 886-2-7197502

Note: All data and specifications are subject to change without notice.

- 14 -

W27C020P-70相关文章

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W27C020P-70产品参数

型号:	W27C020P-70
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	WINBOND ELECTRONICS CORP
零件包装代码：	QFJ
包装说明：	PLASTIC, LCC-32
针数：	32
Reach Compliance Code：	not_compliant
ECCN代码：	3A991.B.1.B.1
HTS代码：	8542.32.00.51
风险等级：	5.86
Is Samacsys：	N
最长访问时间：	70 ns
命令用户界面：	NO
数据轮询：	NO
JESD-30 代码：	R-PQCC-J32
JESD-609代码：	e0
长度：	13.97 mm
内存密度：	2097152 bit
内存集成电路类型：	EEPROM
内存宽度：	8
功能数量：	1
端子数量：	32
字数：	262144 words
字数代码：	256000
工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	256KX8
封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ
封装等效代码：	LDCC32,.5X.6
封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V
编程电压：	12 V
认证状态：	Not Qualified
座面最大高度：	3.56 mm
最大待机电流：	0.0001 A
子类别：	EEPROMs
最大压摆率：	0.03 mA
最大供电电压 (Vsup)：	5.25 V
最小供电电压 (Vsup)：	4.75 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	J BEND
端子节距：	1.27 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
切换位：	NO
宽度：	11.43 mm
Base Number Matches：	1

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