W40S11-02H原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

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产品型号W40S11-02H的概述

芯片W40S11-02H的概述 W40S11-02H是一款集成电路（IC），广泛应用于电子设备中，其设计旨在满足对高效能、低功耗的要求。随着科技进步，市场对于信号处理、信息存储、和控制功能的需求日益增长，W40S11-02H的推出正是顺应这一趋势。该芯片可在多种应用场景中发挥重要作用，特别是在工业自动化、智能家居和消费电子等领域。其多功能集成特性，使得W40S11-02H成为开发者和工程师首选的解决方案之一。芯片W40S11-02H的详细参数 W40S11-02H的参数涵盖了中心频率、工作电压、引脚配置、功耗以及接口标准等多个方面，具体参数如下： - 中心频率： W40S11-02H的中心频率为2.4GHz，适合无线通信和数据传输。 - 工作电压：工作电压范围为2.7V至5.5V，能够适应多种电源环境。 - 功耗：静态功耗极低，不超过10μA，动态功耗依赖于负载情况，确保了设备的...

产品型号W40S11-02H的Datasheet PDF文件预览

W40S11-02

SDRAM Buffer - 2 DIMM (Mobile)

Key Specifications

Features

• Ten skew-controlled CMOS outputs (SDRAM0:9)

• Supports two SDRAM DIMMs

Supply Voltages:...........................................V_DD= 3.3V 5ꢀ

Operating Temperature:.................................... 0°C to +70°C

Input Threshold:...................................................1.5V typical

Maximum Input Voltage: ...................................... V_DD+ 0.5V

Input Frequency:...............................................0 to 133 MHz

BUF_IN to SDRAM0:9 Propagation Delay:........ 1.0 to 5.0 ns

Output Edge Rate:................................................. >1.5 V/ns

Output Skew: ............................................................ 250 ps

Output Duty Cycle:...................................45/55ꢀ worst case

Output Impedance: ....................................... 15 ohms typical

Output Type: ............................................... CMOS rail-to-rail

• Ideal for high-performance systems designed around

Intel®’s latest mobile chip set

• SMBus serial configuration interface

• Skew between any two outputs is less than 250 ps

• 1 to 5 ns propagation delay

• DC to 133-MHz operation

• Single 3.3V supply voltage

• Low power CMOS design packaged in a 28-pin, 209-mil

SSOP (Shrink Small Outline Package)

Overview

The Cypress W40S11-02 is a low-voltage, ten-output clock

buffer. Output buffer impedance is approximately 15:, which

is ideal for driving SDRAM DIMMs.

Pin Configuration

Block Diagram

SDATA

Serial Port

Device Control

VDD

SDRAM0

SDRAM1

GND

VDD

SCLOCK

SDRAM7

SDRAM6

GND

SDRAM0

SDRAM1

SDRAM2

SDRAM3

SDRAM4

SDRAM5

SDRAM6

VDD

SDRAM2

SDRAM3

GND

BUF_IN

VDD

SDRAM8

GND

VDD

SDRAM5

SDRAM4

GND

VDD

[1]

SDRAM9

GND

SDATA

[1]

SCLOCK

[1]

SDRAM7

SDRAM8

SDRAM9

BUF_IN

Note:

1. Internal pull-up resistor of 250K on SDATA, SCLOCK, and OE in-

puts (should not be relied upon for pulling up to V ).

Rev 1.0, Dec. 01, 2006

2200 Laurelwood Road, Santa Clara, CA 95054

Page 1 of 9

Tel:(408) 855-0555 Fax:(408) 855-0550

www.SpectraLinear.com

W40S11-02

Pin Definitions

No.

Type

Pin Name

Pin Description

SDRAM0:9

2, 3, 6, 7,

22, 23, 26,

27, 11, 18

SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a

rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled

to within 250 ps of each other.

BUF_IN

SDATA

Clock Input: This clock input has an input threshold voltage of 1.5V (typ).

I/O

SMBus Data Input: Data should be presented to this input as described in the SMBus

section of this data sheet. Internal 250-k: pull-up resistor.

SCLOCK

VDD

SMBus Clock Input: The SMBus Data clock should be presented to this input as

described in the SMBus section of this data sheet. Internal 250-k: pull-up resistor.

1,5,10,13,

19, 24, 28

Power Connection: Power supply for core logic and output buffers. Connected to

3.3V supply.

GND

4,8,12,16,

17, 21, 25

Ground Connection: Connect all ground pins to the common system ground plane.

Output Enable: Internal 250-k: pull-up resistor. Three-states outputs when LOW.

Output Drivers

Functional Description

The W40S11-02 output buffers are CMOS type which deliver

a rail-to-rail (GND to V_DD) output voltage swing into a nominal

Output Control Pins

Outputs three-stated when OE = 0, and toggle when OE = 1.

Outputs are in phase with BUF_IN but are phase delayed by

1 to 5 ns. Outputs can also be controlled via the SMBus

interface.

capacitive load. Thus, output signaling is both TTL and CMOS

level compatible. Nominal output buffer impedance is 15

ohms.

Operation

Data is written to the W40S11-02 in ten bytes of eight bits

each. Bytes are written in the order shown in Table 1.

Table 1. Byte Writing Sequence

Byte

Sequence

Byte Name

Bit Sequence

Byte Description

Slave Address

11010010

Commands the W40S11-02 to accept the bits in Data Bytes 0–6 for

internal register configuration. Since other devices may exist on the same

common serial data bus, it is necessary to have a specific slave address

foreach potential receiver. The slave receiveraddress forthe W40S11-02

is 11010010. Register setting will not be made if the Slave Address is not

correct (or is for an alternate slave receiver).

Command

Code

“Don’t Care”

Unused by the W40S11-02, therefore bit values are ignored (“Don’t

Care”). This byte must be included in the data write sequence to maintain

proper byte allocation. The Command Code Byte is part of the standard

serial communication protocol and may be used when writing to another

addressed slave receiver on the serial data bus.

Byte Count

Unused by the W40S11-02, therefore bit values are ignored (“Don’t

Care”). This byte must be included in the data write sequence to maintain

proper byte allocation. The Byte Count Byte is part of the standard serial

communication protocol and may be used when writing to another

addressed slave receiver on the serial data bus.

Data Byte 0

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Refer to Table 2 The data bits in these bytes set internal W40S11-23 registers that control

device operation. The data bits are only accepted when the Address Byte

bit sequence is 11010010, as noted above. For description of bit control

functions, refer to Table 2, Data Byte Serial Configuration Map.

Don’t Care

Refer to Cypress clock drivers.

Rev 1.0,Dec. 01, 2006

Page 2 of 9

W40S11-02

Writing Data Bytes

Table 2 gives the bit formats for registers located in Data Bytes

0–6.

Each bit in the data bytes control a particular device function.

Bits are written most significant bit (MSB) first, which is bit 7.

Table 2. Data Bytes 0–2 Serial Configuration Map^[2]

Affected Pin

Bit Control

Bit(s)

Pin No.

Pin Name

Control Function

Data Byte 0 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)

N/A

Reserved

SDRAM3

SDRAM2

SDRAM1

SDRAM0

(Reserved)

Clock Output Disable

Low

Active

Data Byte 1 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)

SDRAM7

SDRAM6

SDRAM5

SDRAM4

Reserved

Clock Output Disable

(Reserved)

Low

Active

N/A

(Reserved)

Data Byte 2 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)

SDRAM9

SDRAM8

Reserved

Clock Output Disable

(Reserved)

Low

Active

N/A

(Reserved)

Note:

2. At power-up all SDRAM outputs are enabled and active. It is recommended to program Bits 4–7 of Byte0 and Bits 0–3 of Byte1 to a “0” to save power and reduce

noise.

Rev 1.0,Dec. 01, 2006

Page 3 of 9

W40S11-02

a default logic 1. All bus devices generally have logic inputs to

receive data.

How To Use the Serial Data Interface

Electrical Requirements

Although the W40S11-02 is a receive-only device (no data

write-back capability), it does transmit an “acknowledge” data

pulse after each byte is received. Thus, the SDATA line can

both transmit and receive data.

Figure 1 illustrates electrical characteristics for the serial

interface bus used with the W40S11-02. Devices send data

over the bus with an open drain logic output that can (a) pull

the bus line LOW, or (b) let the bus default to logic 1. The

pull-up resistor on the bus (both clock and data lines) establish

The pull-up resistor should be sized to meet the rise and fall

times specified in AC parameters, taking into consideration

total bus line capacitance.

VDD

~ 2k

~ 2k:

SERIAL BUS DATA LINE

SERIAL BUS CLOCK LINE

SDCLK

SDATA

SCLOCK

SDATA

CLOCK IN

DATA IN

CLOCK IN

DATA IN

DATA OUT

CLOCK OUT

DATA OUT

CHIP SET

(SERIAL BUS MASTER TRANSMITTER)

CLOCK DEVICE

(SERIAL BUS SLAVE RECEIVER)

Figure 1. Serial Interface Bus Electrical Characteristics

Rev 1.0,Dec. 01, 2006

Page 4 of 9

W40S11-02

Signaling Requirements

Sending Data to the W40S11-02

As shown in Figure 2, valid data bits are defined as stable logic

0 or 1 condition on the data line during a clock HIGH (logic 1)

pulse. A transitioning data line during a clock HIGH pulse may

be interpreted as a start or stop pulse (it will be interpreted as

a start or stop pulse if the start/stop timing parameters are

met).

The device accepts data once it has detected a valid start bit

and address byte sequence. Device functionality is changed

upon the receipt of each data bit (registers are not double

buffered). Partial transmission is allowed meaning that a trans-

mission can be truncated as soon as the desired data bits are

transmitted (remaining registers will be unmodified). Trans-

mission is truncated with either a stop bit or new start bit

(restart condition).

A write sequence is initiated by a “start bit” as shown in Figure

1. A “stop bit” signifies that a transmission has ended.

As stated previously, the W40S11-02 sends an “acknowledge”

pulse after receiving eight data bits in each byte as shown in

Figure 2.

SDATA

SCLOCK

Valid

Data

Bit

Change

of Data Allowed

Figure 2. Serial Data Bus Valid Data Bit

SDATA

SCLOCK

Start

Bit

Stop

Bit

Figure 1. Serial Data Bus Start and Stop Bit

Rev 1.0,Dec. 01, 2006

Page 5 of 9

W40S11-02

Signaling from System Core Logic

Start Condition

Stop C

Slave Address

(First Byte)

Command Code

(Second Byte)

Byte Count

(Third Byte)

Last Data Byte

(Last Byte)

LSB

MSB

SDATA

SCLOCK

SDATA

MSB

LSB

MSB

Acknowledgment Bit

from Clock Device

Signaling by Clock Device

Figure 2. Serial Data Bus Write Sequence

SDATA

SPF

DHD

LOW

DSU

STHD

SCLOCK

STHD

HIGH

SPSU

Figure 3. Serial Data Bus Timing Diagram

Absolute Maximum Ratings

Stresses greater than those listed in this table may cause

permanent damage to the device. These represent a stress

rating only. Operation of the device at these or any other condi-

tions above those specified in the operating sections of this

specification is not implied. Maximum conditions for extended

periods may affect reliability.

Parameter

V_DD, V_IN

T_STG

T_A

Description

Voltage on any pin with respect to GND

Storage Temperature

Rating

Unit

–0.5 to +7.0

–65 to +150

0 to +70

°C

Operating Temperature

T_B

Ambient Temperature under Bias

–55 to +125

Rev 1.0,Dec. 01, 2006

Page 6 of 9

W40S11-02

DC Electrical Characteristics: T_A= 0°C to +70°C, V_DD= 3.3V 5ꢀ

Parameter

I_DD

Description

3.3V Supply Current

Test Condition/Comments

at 66 MHz

Min

Typ

120

185

Max

160

220

Unit

I_DD

at 100 MHz

I_{DD Tristate}

3.3V Supply Current in

Three-State

Logic Inputs

V_IL

Input Low Voltage

V_SS– 0.3

2.0

0.8

V_DD+ 0.5

V_IH

Input High Voltage

I_ILEAK

Input Leakage Current, BUF_IN

Input Leakage Current^[3]

–5

µA

I_ILEAK

–20

Logic Outputs (SDRAM0:9)^[4]

V_OL

V_OH

I_OL

Output Low Voltage

Output High Voltage

Output Low Current

Output High Current

I_OL= 1 mA

I_OH= –1 mA

V_OL= 1.5V

V_OH= 1.5V

3.1

110

100

185

160

I_OH

Pin Capacitance/Inductance

C_INInput Pin Capacitance

C_OUT

Output Pin Capacitance

Input Pin Inductance

L_IN

Note:

3. OE, SDATA, and SCLOCK logic pins have a 250-k: internal pull-up resistor (V – 0.8V).

4. All SDRAM outputs loaded by 6" transmission lines with 22-pF capacitors on ends.

AC Electrical Characteristics: T_A= 0°C to +70°C, V_DD= 3.3V 5ꢀ (Lump Capacitance Test Load = 30 pF)

Parameter

f_IN

Description

Input Frequency

Test Condition

Min

Typ

Max

133

4.0

250

8.0

5.0

Unit

MHz

V/ns

t_R

Output Rise Edge Rate

Output Fall Edge Rate

Output Skew, Rising Edges

Output Skew, Falling Edges

Output Enable Time

Measured from 0.4V to 2.4V

Measured from 2.4V to 0.4V

1.5

t_F

t_SR

t_SF

t_EN

t_DIS

t_PR

t_PF

t_D

1.0

Output Disable Time

Rising Edge Propagation Delay

Falling Edge Propagation Delay

Duty Cycle

Measured at 1.5V

ꢀ

Z_o

AC Output Impedance

Rev 1.0,Dec. 01, 2006

Page 7 of 9

W40S11-02

Layout Example

+3.3V Supply

DDQ3

10PF

.005PF

FB = Dale ILB1206 - 300 (300:ꢀ@ 100 MHz)

µF

C4 = 0.005

V = VIA to respective supply plane layer

µF

Ceramic Caps C3 = 10–22

= VIA to GND plane layer

Note: Each supply plane or strip should have a ferrite bead and capacitors

All V_DDs have –1 mF low ESR bypass at pin to ground

All bypass caps = 0.1 PF ceramic

Rev 1.0,Dec. 01, 2006

Page 8 of 9

W40S11-02

Ordering Information

Ordering Code

Freq. Mask Code

Package Name

Package Type

W40S11

-02

28-pin SSOP (209-mil)

28-pin TSSOP (173-mil)

Package Diagrams

28-Lead Thin Shrunk Small Outline Package (4.40-mm Body)

PIN 1 ID

DIMENSIONS IN MM[INCHES] MIN.

MAX.

REFERENCE JEDEC MO-153

PACKAGE WEIGHT 0.16 gms

6.25[0.246]

6.50[0.256]

PART #

4.30[0.169]

4.50[0.177]

Z28.173 STANDARD PKG.

ZZ28.173 LEAD FREE PKG.

0.65[0.025]

BSC.

1.10[0.043] MAX.

0.25[0.010]

BSC

0.19[0.007]

0.30[0.012]

GAUGE

PLANE

0°-8°

0.076[0.003]

0.50[0.020]

0.70[0.027]

0.05[0.002]

0.15[0.006]

0.85[0.033]

0.95[0.037]

0.09[[0.003]

0.20[0.008]

SEATING

PLANE

9.60[0.378]

9.80[0.386]

Ordering Information

Freq. Mask

Code

Package

Name

Ordering Code

Package Type

W40S11

-02

28-pin SSOP (209-mil)

28-pin TSSOP (173-mil)

While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-

cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in

normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-

tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional

processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any

circuitry or specification without notice.

Rev 1.0, Dec. 01, 2006

Page 9 of 9

W40S11-02H相关文章

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W40S11-02H产品参数

型号:	W40S11-02H
是否Rohs认证：	不符合
生命周期：	Transferred
Reach Compliance Code：	unknown
风险等级：	5.82
JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e0
端子数量：	28
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP
封装等效代码：	SSOP28,.3
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH
电源：	3.3 V
Prop。Delay @ Nom-Sup：	5 ns
认证状态：	Not Qualified
子类别：	Clock Drivers
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.635 mm
端子位置：	DUAL
Base Number Matches：	1

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产品型号W40S11-02H的概述

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