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    产品型号W83176R-735的Datasheet PDF文件预览

    W83176R-735  
    Data Sheet  
    WINBOND  
    3 DIMM DDR ZERO  
    DELAY BUFFER  
    FOR  
    SIS CHIPSET  
    Publication Release Date: April 13, 2005  
    Revision 1.1  
    - I -  
    W83176R-735  
    Table of Contents-  
    1.  
    2.  
    3.  
    4.  
    5.  
    GENERAL DESCRIPTION ......................................................................................................... 1  
    FEATURES................................................................................................................................. 1  
    PIN CONFIGURATION............................................................................................................... 1  
    BLOCK DIAGRAM ...................................................................................................................... 2  
    PIN DESCRIPTION..................................................................................................................... 2  
    5.1  
    5.2  
    Clock Outputs ................................................................................................................. 3  
    Power Pins...................................................................................................................... 3  
    6.  
    7.  
    REGISTER 0 ~ REGISTER 4 RESERVED ................................................................................ 4  
    6.1  
    6.2  
    Register 5: Output Control (1 = Active, 0 = Inactive) (Default = FFH)............................ 4  
    Register 6: Output Control (1 = Active, 0 = Inactive) (Default = FFH)............................ 4  
    ACCESS INTERFACE................................................................................................................ 5  
    7.1  
    7.2  
    7.3  
    7.4  
    Block Write Protocol ....................................................................................................... 5  
    Block Read Protocol ....................................................................................................... 5  
    Byte Write Protocol......................................................................................................... 5  
    Byte Read Protocol......................................................................................................... 5  
    8.  
    SPECIFICATIONS ...................................................................................................................... 6  
    8.1  
    8.2  
    8.3  
    Absolute Maximum Ratings............................................................................................ 6  
    A.C. Characteristics........................................................................................................ 6  
    D.C. Characteristics........................................................................................................ 6  
    9.  
    ORDERING INFORMATION....................................................................................................... 6  
    HOW TO READ THE TOP MARKING........................................................................................ 7  
    PACKAGE DRAWING AND DIMENSIONS................................................................................ 8  
    REVISION HISTORY.................................................................................................................. 9  
    10.  
    11.  
    12.  
    - II -  
    W83176R-735  
    1. GENERAL DESCRIPTION  
    The W83176R-735 is a 2.5V Zero-delay D.D.R. Clock buffer designed for SiS system. W83176R-735  
    can support 3 D.D.R. DRAM DIMMs.  
    The W83176R-735 provides I2C serial bus interface to program the registers to enable or disable each  
    clock outputs. The W83176R-735 accepts a reference clock as its input and runs on 2.5V supply.  
    2. FEATURES  
    •
    •
    •
    •
    •
    •
    •
    •
    Zero-delay clock outputs  
    Feedback pins for synchronous  
    Supports up to 3 D.D.R. DIMMs  
    One pairs of additional outputs for feedback  
    Low Skew outputs (<100 pS)  
    Supports 400 MHz D.D.R. SDRAM  
    I2C 2-Wire serial interface and supports Byte or Block Date RW  
    Packaged in 48-pin SSOP  
    3. PIN CONFIGURATION  
    GND 1  
    CLKC0 2  
    CLKT0 3  
    VDD 4  
    48 GND  
    47 CLKC5  
    46 CLKT5  
    45 VDD  
    CLKT1 5  
    CLKC1 6  
    GND 7  
    44 CLKT6  
    43 CLKC6  
    42 GND  
    GND 8  
    41 GND  
    CLKC2 9  
    CLKT2 10  
    VDD 11  
    * SCLK 12  
    40 CLKC7  
    39 CLKT7  
    38 VDD  
    37 SDATA *  
    36 N/C  
    CLK_INT 13  
    N/C 14  
    35 FB_INT  
    34 VDD  
    VDD 15  
    AVDD 16  
    AGND 17  
    GND 18  
    33 FB_OUTT  
    32 NC  
    31 GND  
    CLKC3 19  
    CLKT3 20  
    VDD 21  
    30 CLKC8  
    29 CLKT8  
    28 VDD  
    CLKT4 22  
    CLKC4 23  
    GND 24  
    27 CLKT9  
    26 CLKC9  
    25 GND  
    *: Internal pull-up resistor 120K to VDD  
    Publication Release Date: April 13, 2005  
    Revision 1.1  
    - 1 -  
    W83176R-735  
    4. BLOCK DIAGRAM  
    5. PIN DESCRIPTION  
    IN - Input  
    OUT - Output  
    I/O - Bi-directional Pin  
    *- Internal 120KΩ pull-up  
    - 2 -  
    W83176R-735  
    5.1 Clock Outputs  
    SYMBOL  
    PIN  
    I/O  
    FUNCTION  
    26, 30, 40, 43, 47,  
    23, 19, 9, 6, 2  
    CLKC[9:0]  
    OUT  
    Complementory Clocks of differential pair outputs  
    27, 29, 39, 44, 46,  
    22, 20, 10, 5, 3  
    CLKT[9:0]  
    SDATA *  
    OUT  
    I/O  
    True Clocks of differential pair outputs  
    Serial data of I2C 2-wire control interface  
    Internal pull-up resistor 120K to Vdd  
    Serial clock of I2C 2-wire control interface  
    Internal pull-up resistor 120K to Vdd  
    37  
    12  
    SCLK *  
    IN  
    IN  
    CLK_INT  
    NC  
    13  
    True reference clock input, 3.3V tolerant input  
    14, 32, 36  
    NONE Not connected  
    True Feedback output, dedicated for external feedback.  
    FB_OUTT  
    FB_INT  
    33  
    35  
    OUT  
    IN  
    It switches at the same frequency as the CLK. This  
    output must be wired to FB_INT.  
    True Feedback input, provides feedback signal to the  
    internal PLL for synchronization with CLK_INT to  
    eliminate phase error.  
    5.2 Power Pins  
    SYMBOL  
    PIN  
    FUNCTION  
    1, 7, 8, 18, 24, 25,  
    GND  
    VDD  
    Ground  
    31, 41, 42, 48  
    4, 11, 15, 21, 28,  
    34, 38, 45  
    Power Supply 2.5V  
    16  
    17  
    AVDD  
    AGND  
    Analog power supply, 2.5V  
    Analog ground  
    Publication Release Date: April 13, 2005  
    Revision 1.1  
    - 3 -  
    W83176R-735  
    6. REGISTER 0 ~ REGISTER 4 RESERVED  
    6.1 Register 5: Output Control (1 = Active, 0 = Inactive) (Default = FFH)  
    BIT  
    @POWERUP  
    PIN  
    DESCRIPTION  
    7
    6
    5
    4
    3
    2
    1
    0
    1
    1
    1
    1
    1
    1
    1
    1
    2, 3  
    6, 5  
    CLKC0, CLKT0 output control  
    CLKC1, CLKT1 output control  
    CLKC2, CLKT2 output control  
    CLKC3, CLKT3 output control  
    CLKC4, CLKT4 output control  
    CLKC9, CLKT9 output control  
    Reserved  
    9, 10  
    19, 20  
    23, 22  
    26, 27  
    -
    -
    Reserved  
    6.2 Register 6: Output Control (1 = Active, 0 = Inactive) (Default = FFH)  
    BIT  
    @POWERUP  
    PIN  
    DESCRIPTION  
    7
    6
    5
    4
    3
    2
    1
    0
    1
    1
    1
    1
    1
    1
    1
    1
    -
    -
    -
    Reserved  
    Reserved  
    Reserved  
    CLKC8, CLKT8 output control  
    CLKC7, CLKT7 output control  
    CLKC6, CLKT6 output control  
    CLKC5, CLKT5 output control  
    Reserved  
    30, 29  
    40, 39  
    43, 44  
    47, 46  
    -
    - 4 -  
    W83176R-735  
    7. ACCESS INTERFACE  
    The W83176R-735 provides I2C Serial Bus for microprocessor to read/write internal registers. In the  
    W83176R-735 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C write  
    address is defined at 0xD4. The I2C read address is defined at 0xD5.  
    Block Read and Block Write Protocol  
    7.1 Block Write Protocol  
    7.2 Block Read Protocol  
    ## In block mode, the command code must filled 00H  
    7.3 Byte Write Protocol  
    7.4 Byte Read Protocol  
    Publication Release Date: April 13, 2005  
    - 5 -  
    Revision 1.1  
    W83176R-735  
    8. SPECIFICATIONS  
    8.1 Absolute Maximum Ratings  
    Stresses greater than those listed in this table may cause permanent damage to the device.  
    Precautions should be taken to avoid application of any voltage higher than the maximum rated  
    voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs  
    must always be tied to an appropriate logic voltage level (Ground or VDD).  
    SYMBOL  
    VDD, AVDD  
    PARAMETER  
    Voltage on any pin with respect to GND  
    Storage Temperature  
    Ambient Temperature  
    Operating Temperature  
    RATING  
    -0.5V to +3.6V  
    -65°C to +150°C  
    -55°C to +125°C  
    0°C to +70°C  
    TSTG  
    TB  
    TA  
    8.2 A.C. Characteristics  
    VDD = AVDD = 2.5V ±5 %, TA = 0°C to +70°C, Test load = 10 pF  
    PARAMETER  
    SYM.  
    MIN.  
    100  
    40  
    TYP.  
    MAX.  
    UNITS  
    TEST CONDITIONS  
    Operating Clock  
    FIN  
    200  
    MHz  
    Frequency  
    Input Clock Duty Cycle  
    Dynamic Supply Current  
    Dtin  
    Idd  
    60  
    300  
    %
    mA  
    Fin =100 to 200 MHz  
    Fout =100 to 200 MHz  
    C-  
    Cycle to Cycle Jitter  
    200  
    pS  
    Cjitter  
    Output to Output Skew  
    Output Clock Rise Time  
    Output Clock Fall Time  
    Output Clock Duty Cycle  
    Tskew  
    Tor  
    Tof  
    100  
    950  
    950  
    55  
    pS  
    pS  
    pS  
    %
    Fout =100 to 200 MHz  
    Fout =100 to 200 MHz  
    Fout =100 to 200 MHz  
    Fout =100 to 200 MHz  
    650  
    650  
    45  
    Dtot  
    Output Differential-pair  
    (VDD/2) VDD/ (VDD/2)  
    Voc  
    V
    Fout =100 to 200 MHz  
    Crossing Voltage  
    -0.2 + 0.2  
    2
    8.3 D.C. Characteristics  
    VDD = AVDD = 2.5V ±5%, TA = 0°C to +70°C  
    PARAMETER  
    SYM. MIN. TYP. MAX. UNITS  
    TEST CONDITIONS  
    SDATA, SCLK Input Low Voltage  
    SDATA, SCLK Input High Voltage  
    CLKIN, FBIN Input Voltage Low  
    CLKIN, FBIN Input Voltage High  
    Input Pin Capacitance  
    1.0  
    Vdc  
    Vdc  
    Vdc  
    Vdc  
    pF  
    pF  
    nH  
    SVIL  
    SVIH  
    VIL  
    VIH  
    CIN  
    2.2  
    2.1  
    0.4  
    Fin = 100 to 200 MHz  
    Fin = 100 to 200 MHz  
    5
    6
    7
    Output Pin Capacitance  
    Input Pin Inductance  
    COUT  
    LIN  
    9. ORDERING INFORMATION  
    - 6 -  
    W83176R-735  
    PART NUMBER  
    PACKAGE TYPE  
    PRODUCTION FLOW  
    W83176R_735  
    48-pin SSOP  
    Commercial, 0°C to +70°C  
    10. HOW TO READ THE TOP MARKING  
    W83176R-735  
    28051234  
    342GB  
    1st line: Winbond logo and the type number: W83176R-735  
    2nd line: Tracking code 2 8051234  
    2: wafers manufactured in Winbond FAB 2  
    8051234: wafer production series lot number  
    3rd line: Tracking code 342 G B  
    342: packages made in '2003, week 42  
    G: assembly house ID; O means OSE, G means GR  
    B: IC revision  
    All the trade marks of products and companies mentioned in this data sheet belong to their  
    respective owners.  
    Publication Release Date: April 13, 2005  
    - 7 -  
    Revision 1.1  
    W83176R-735  
    11. PACKAGE DRAWING AND DIMENSIONS  
    - 8 -  
    W83176R-735  
    12. REVISION HISTORY  
    VERSION  
    DATE  
    PAGE  
    DESCRIPTION  
    All of the versions before 0.50 are for internal  
    use.  
    n.a.  
    Correction IC version, add register default  
    value and correction some description and  
    default value  
    0.5  
    12/18/03  
    3.7  
    1.0  
    1.1  
    05/06/04  
    04/13/2005  
    Update to web  
    Add disclaimer  
    Important Notice  
    Winbond products are not designed, intended, authorized or warranted for use as components  
    in systems or equipment intended for surgical implantation, atomic energy control  
    instruments, airplane or spaceship instruments, transportation instruments, traffic signal  
    instruments, combustion control instruments, or for other applications intended to support or  
    sustain life. Further more, Winbond products are not intended for applications wherein failure  
    of Winbond products could result or lead to a situation wherein personal injury, death or  
    severe property or environmental damage could occur.  
    Winbond customers using or selling these products for use in such applications do so at their  
    own risk and agree to fully indemnify Winbond for any damages resulting from such improper  
    use or sales.  
    Headquarters  
    Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.  
    27F, 2299 Yan An W. Rd. Shanghai,  
    200336 China  
    No. 4, Creation Rd. III,  
    Science-Based Industrial Park,  
    Hsinchu, Taiwan  
    2727 North First Street, San Jose,  
    CA 95134, U.S.A.  
    TEL: 1-408-9436666  
    TEL: 86-21-62365999  
    FAX: 86-21-62365998  
    TEL: 886-3-5770066  
    FAX: 1-408-5441798  
    FAX: 886-3-5665577  
    http://www.winbond.com.tw/  
    Taipei Office  
    Winbond Electronics Corporation Japan  
    7F Daini-ueno BLDG, 3-7-18  
    Shinyokohama Kohoku-ku,  
    Yokohama, 222-0033  
    Winbond Electronics (H.K.) Ltd.  
    Unit 9-15, 22F, Millennium City,  
    No. 378 Kwun Tong Rd.,  
    Kowloon, Hong Kong  
    9F, No.480, Rueiguang Rd.,  
    Neihu District, Taipei, 114,  
    Taiwan, R.O.C.  
    TEL: 886-2-8177-7168  
    FAX: 886-2-8751-3579  
    TEL: 81-45-4781881  
    TEL: 852-27513100  
    FAX: 81-45-4781800  
    FAX: 852-27552064  
    Please note that all data and specifications are subject to change without notice.  
    All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.  
    Publication Release Date: April 13, 2005  
    Revision 1.1  
    - 9 -  
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