W83194BG各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

W83194BR-323/W83194BG-323

STEPLESS CLOCK FOR INTEL

BROOKDALE CHIPSET

Date: 03/22/2006

Revision: 2.1

W83194BR-323W83194BG-323

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

W83194BR-323 Data Sheet Revision History

PAGES

DATES

VERSION

WEB

MAIN CONTENTS

VERSION

n.a.

All of the versions before 0.50 are for internal

use.

1

n.a.

P13

All

13/May

1.0

1.1

2.0

2.1

n.a

1.1

2.0

Change version and version on web site to 1.0

2

02/August

02/20/2003

03/22/2006

Delete Test mode register.

3

4

Update new form

5

Add lead free part number --- W83194BG-323

6

7

8

9

10

Please note that all data and specifications are subject to change without notice. All

the trademarks of products and companies mentioned in this data sheet belong to

their respective owners.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where

malfunction of these products can reasonably be expected to result in personal injury. Winbond

customers using or selling these products for use in such applications do so at their own risk and

agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

Publication Release Date: March 2006

- I -

Revision 2.1

W83194BR-323W83194BG-323

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

Table of Content-

1.

2.

3.

4.

5.

GENERAL DESCRIPTION ......................................................................................................... 1

PRODUCT FEATURES .............................................................................................................. 1

BLOCK DIAGRAM ...................................................................................................................... 2

PIN CONFIGURATION............................................................................................................... 2

PIN DESCRIPTION..................................................................................................................... 3

5.1

5.2

5.3

5.4

5.5

Crystal I/O.................................................................................................................................3

CPU, 3V66, and PCI Clock Outputs........................................................................................3

I²C Control Interface.................................................................................................................4

Fixed Frequency Outputs.........................................................................................................4

Power Pins................................................................................................................................5

6.

7.

FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 6

I2C CONTROL AND STATUS REGISTERS .............................................................................. 7

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

Register 0: Frequency Select Register (default = 0)...............................................................7

Register 1: CPU Clock Register (1 = enable, 0 = Stopped) ...................................................7

Register 2: PCI Clock Register (1 = enable, 0 = Stopped).....................................................7

Register 3: PCI, 48MHz Clock Register (1 = enable, 0 = Stopped) .......................................8

Register 4: 3V66 Control Register (1 = enable, 0 = Stopped)................................................8

Register 5: Watchdog Control Register...................................................................................8

Register 6: Watchdog Timer Register .....................................................................................9

Register 7: M/N Program Register ..........................................................................................9

Register 8: M/N Program Register ..........................................................................................9

Register 9: Spread Spectrum Programming Register ..........................................................10

Register 10: Divisor and Step-less Enable and Skew Control Register...............................10

Register 11: Winbond Chip ID Register (Read Only).........................................................11

Register 12: Winbond Chip ID Register (Read Only).........................................................11

Register 13: Reserved ...........................................................................................................11

Register 14: CPU to PCI Skew Control.................................................................................12

Register 15: SEL24_48 and SEL48_66 Control ...................................................................12

7.9

7.10

7.11

7.12

7.13

7.14

7.15

7.16

8.

ACCESS INTERFACE.............................................................................................................. 13

8.1

8.2

8.3

8.4

Block Write protocol ...............................................................................................................13

Block Read protocol...............................................................................................................13

Byte Write protocol.................................................................................................................13

Byte Read protocol.................................................................................................................13

9.

10.

11.

ORDERING INFORMATION..................................................................................................... 14

HOW TO READ THE TOP MARKING...................................................................................... 14

PACKAGE DRAWING AND DIMENSIONS.............................................................................. 15

- II -

W83194BR-323W83194BG-323

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

1. GENERAL DESCRIPTION

The W83194BR-323 is a Clock Synthesizer for Intel Brook dale 845 chipset. W83194BR-323

provides all clocks required for high-speed microprocessor and provides step-less frequency

programming and 32 different frequencies of CPU, PCI, and 3V66 clocks setting. All clocks are

externally selectable with smooth transitions.

The W83194BR-323 provides I²C serial bus interface to program the registers to enable or disable

each clock outputs and provides -0.5% and +/-0.25% center type spread spectrum or programmable

S.S.T. scale to reduce EMI.

The W83194BR-323 also has watchdog timer and reset output pin to support auto-reset when

systems hanging caused by improper frequency setting.

The W83194BR-323 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.

High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. The

fixed frequency outputs as REF and 48 MHz provide better than 0.5V /ns slew rate.

2. PRODUCT FEATURES

3 Differential pairs of CPU clock outputs

• 4 3V66 clock outputs

• 10 PCI synchronous clocks

• 24_48Mhz clock output for super I/O.

• 48 MHz clock output for USB.

• Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns

• Smooth frequency switch with selections from 66.8 to 200MHz

• Step-less frequency programming

• I²C 2-Wire serial interface and support byte read/write and block read/write.

• -0.5% and +/- 0.25% center type spread spectrum

• Programmable S.S.T. scale to reduce EMI

• Programmable registers to enable/stop each output and select modes

• Watch Dog Timer and RESET# output pins

• 48-pin SSOP package

Publication Release Date: March 2006

- 1 -

Revision 2.1

W83194BR-323W83194BG-323

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

3. BLOCK DIAGRAM

Driver

48MHz

PLL2

24_48MHz

Mux

1/2

XIN

2

XTAL

OSC

REF0:1

XOUT

VCOCLK

PLL1

Spread

3

Spectrum

CPUCLK_T 0:2

CPUCLK_C 0:2

Divider

Stop

/2,/4,/8,/16

/3,/6,/12

/5,/10,/20

/7,/14

M/N/Ratio

S.S.P

4

3V66_0:3

ROM

Latch

&

VTTPWRGD#

FS<4:0>

1

POR

PCICLK_F0:2

PCICLK_0:6

Stop

/9,/18

Control

Logic

PD#

PCI_STOP#

CPU_STOP#

&

RESET#

Rref

2

Config

Register

MULTISEL 0:1

*SDATA

*SDCLK

I2C

interface

4. PIN CONFIGURATION

*MULTSEL1/REF1

1

2

3

4

5

6

48

*MULTSEL0/REF0

GND

47

46

VDDREF

Xin

VDDCPU

45

Xout

CPUCLK_T2

CPUCLK_C2

GND

44

43

42

41

40

39

38

PCICLK_F0/*FS2

PCICLK_F1/*FS3

7

*PD#

PCICLK_F2/&SEL24_4

8

CPUCLK_T0

9

VDDPCI

PCICLK0/*FS4

PCICLK1

CPUCLK_C0

VDDCPU

CPUCLK_T1

CPUCLK_C1

GND

10

11

12

37

PCICLK2

GND

36

35

34

33

32

31

30

13

14

15

PCICLK3

IREF

PCICLK4

VDDCORE

GND

PCICLK5

PCICLK6

16

17

18

19

VDD3V66

3V66_0

VDDPCI

VTTPWRGD#

RESET#

3V66_1

29

28

27

26

25

GND

20

3V66_2

21

GND

3V66_3 / 48MHz /*SEL48_66

22

48MHz/*FS0

24_48MHz/*FS1

VDD48

*SDCLK

*SDATA

23

24

* :internal 120K pull-up

&:internal 120K pull-down

#: active low

- 2 -

W83194BR-323W83194BG-323

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

5. PIN DESCRIPTION

BUFFER TYPE SYMBOL

DESCRIPTION

IN

Input

IN_td120k

OUT

OD

I/O

I/OD

#

Input pin and internal 120K pull down

Output

Open Drain

Bi-directional Pin

Bi-directional Pin, Open Drain

Active Low

*

&

Internal 120kΩ pull-up

Internal 120kΩ pull-down

5.1 Crystal I/O

PIN NAME

TYPE

DESCRIPTION

3

XIN

IN

Crystal input with internal loading capacitors (18pF) and

feedback resistors.

4

XOUT

OUT Crystal output at 14.318MHz nominally with internal loading

capacitors (18pF).

5.2 CPU, 3V66, and PCI Clock Outputs

PIN NAME

TYPE

DESCRIPTION

41,38,

40,37

45,44

CPUCLK_T [0:2]

OUT Low skew (< 250ps) differential clock outputs for host

CPUCLK_C [0:2]

frequencies of CPU and chipset.

31,30,28 3V66_0:2

OUT ꢀ 3.3V 66MHz clock outputs.

27

3V66_3 / 48MHz

OUT ꢀ 3V66_3 or 48MHz clock output.

*SEL48_66

IN_tp120kLatched input for 48MHz or 66MHz select pin. This is internal

120K pull up default 66MHz. In power on reset period, it is a

hardware-latched pin, and it can be R/W by I2C control after

power on reset period. Select by register 16 bit 6.

35

IREF

IN

ꢀ Deciding the reference current for the CPUCLK pairs.

The pin was connected to the precision resistor tied to

ground to decide the appropriate current. There are

several modes to select different current via power on

trapping the Pin 1 & 48 (MULTISEL0, 1). The table is

show as follows.

20

19

RESET#

OD System reset signal when the watchdog is time out. This pin

will generate 250ms low phase when the watchdog timer is

timeout.

VTTPWRGD#

IN

Power good input signal comes from ACPI with low active.

This 3.3V input is level sensitive strobe used to determine FS

[4:0] and MULTISEL0, MULTISEL1, input are valid and is

ready to sampled. This pin is low active.

Publication Release Date: March 2006

- 3 -

Revision 2.1

W83194BR-323W83194BG-323

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

CPU, 3V66, and PCI Clock Outputs, continued

42

PIN NAME

PD#

TYPE

IN

DESCRIPTION

Power Down Function. This is power down pin, low active

(PD#).

Internal 120K pull up

6

7

PCICLK_F0

*FS2

OUT 3.3V free running PCI clock output.

IN_tp120kLatched input for FS2 at initial power up for H/W selecting

the output frequency, This is internal 120K pull up.

OUT 3.3V free running PCI clock output.

PCICLK_F1

*FS3

IN_tp120kLatched input for FS3 at initial power up for H/W selecting

the output frequency, This is internal 120K pull up.

8

PCICLK_F2

&SEL24_48

OUT 3.3V free running PCI clock outputs.

IN_td120kLatched input for 24MHz or 48MHz select pin. This is internal

120K pull down default 24MHz.

10

PCICLK0

*FS4

OUT Low skew (< 250ps) PCI clock outputs.

IN_tP120kLatched input for FS4 at initial power up for H/W selecting

the output frequency, This is internal 120K pull up.

11, 12, 14, PCICLK [1:6]

15, 16, 17

OUT Low skew (< 250ps) PCI clock outputs.

5.3 I²C Control Interface

Pin Name

SDATA*

Type

Description

25

I/OD Serial data of I²C 2-wire control interface with internal pull-

up resistor.

26

SCLK*

IN

Serial clock of I²C 2-wire control interface with internal pull-

up resistor.

5.4 Fixed Frequency Outputs

PIN NAME

TYPE

DESCRIPTION

48

REF0

OUT 14.318NHz output.

MULTSEL0*

IN_tp120kLatched input for MULTSEL0 at initial power up, internal

120K pull up

OUT 14.318NHz output.

1

REF1

MULTSEL1*

IN_tp120kLatched input for MULTSEL1 at initial power up, internal

120K pull up

22

23

48MHz

*FS0

OUT 48MHz clock output for USB.

IN_tp120kLatched input for FS0 at initial power up for H/W selecting

the output frequency. This is internal 120K pull up.

OUT 24(default) or 48MHz clock output, In power on reset period,

it is a hardware-latched pin, and it can be R/W by I2C control

after power on reset period. Select by register 16 bit 7.

IN_tp120kLatched input for FS1 at initial power up for H/W selecting

the output frequency. This is internal 120K pull up.

24_48MHz

*FS1

- 4 -

W83194BR-323W83194BG-323

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

5.5 Power Pins

PIN NAME

TYPE

DESCRIPTION

2

VDDREF

VDDPCI

VDD3V66

VDDCPU

VDDCORE

VDD48

PWR 3.3V power supply for REF.

PWR 3.3V power supply for PCI.

PWR 3.3V power supply for 3V66.

PWR 3.3V power supply for CPU.

PWR 3.3V power supply for analog core.

PWR Analog power 3.3V for 48MHz.

PWR Ground pin for 3.3 V

9,18

32

39,46

34

24

5, 13, 21, 29, 33,

36, 43, 47

GND

Hardware MULTSEL [1:0] selects Function

MULTSEL1 MULTSEL0 BOARD TARGET

TRACE/TERM Z

REFERENCE R,IREF

= VDD/(3*RR)

OUTPUT

CURRENT

Ioh=4*IREF

VOH @ Z

0

1

0

1

0

1

0

1

0

1

0

1

0

Rr =221 1%

IREF = 5.00mA

Rr =221 1%

1.0V @ 50

1.2V @ 60

50 Ω

60 Ω

50 Ω

60 Ω

50 Ω

60 Ω

50 Ω

60 Ω

50 Ω

60 Ω

50 Ω

60 Ω

50 Ω

60 Ω

50 Ω

60 Ω

Ioh=4*IREF

Ioh=5*IREF

Ioh=6*IREF

Ioh=7*IREF

Ioh=4*IREF

Ioh=5*IREF

Ioh=6*IREF

Ioh=7*IREF

Ioh=6*IREF

IREF = 5.00mA

Rr =221 1%

1.25V @

50

1.5V @ 60

IREF = 5.00mA

Rr =221 1%

IREF = 5.00mA

Rr =221 1%

1.5V @ 50

1.8V @ 60

IREF = 5.00mA

Rr =221 1%

IREF = 5.00mA

Rr =221 1%

1.75V @

50

2.1V @ 50

IREF = 5.00mA

Rr =221 1%

IREF = 5.00mA

Rr =475 1%

0.47V @

50

IREF = 2.32mA

Rr =475 1%

0.56V @

50

IREF = 2.32mA

Rr =475 1%

0.58V @

50

IREF = 2.32mA

Rr =475 1%

0.7V @ 60

IREF = 2.32mA

Rr =475 1%

0.7V @ 50

IREF = 2.32mA

Rr =475 1%

0.84V @

60

IREF = 2.32mA

Rr =475 1%

0.81V @

50

IREF = 2.32mA

Rr =475 1%

0.97V @

60

IREF = 2.32mA

Publication Release Date: March 2006

Revision 2.1

- 5 -

W83194BR-323W83194BG-323

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE

This frequency table is used at power on latched FS [4:0] value or software programming at SSEL

[4:0] (Register 0 bit 6 ~ 2).

FS4

FS3

FS2

FS1

FS0

CPU (MHZ)

3V66(MHZ)

PCI (MHZ)

SPREAD %

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

102.0

105.0

108.0

111.0

114.0

117.0

120.0

123.0

126.0

130.0

136.0

140.0

144.0

148.0

152.0

156.0

160.0

164.0

166.6

170.0

175.0

180.0

185.0

190.0

66.8

68.0

70.0

72.0

74.0

76.0

78.0

80.0

82.0

63.0

65.0

68.0

70.0

72.0

74.0

76.0

78.0

80.0

82.0

66.6

68.0

70.0

72.0

74.0

76.0

66.8

66.6

34.0

35.0

36.0

37.0

38.0

39.0

40.0

41.0

31.5

32.5

34.0

35.0

36.0

37.0

38.0

39.0

40.0

41.0

33.3

34.0

35.0

36.0

37.0

38.0

33.4

33.3

+/-0.25%

-0.5%

100.2

133.6

200.4

66.6

100.0

200.0

133.3

-0.5%

- 6 -

W83194BR-323W83194BG-323

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

7. I2C CONTROL AND STATUS REGISTERS

7.1 Register 0: Frequency Select Register (default = 0)

BIT

NAME

PWD

DESCRIPTION

Enable Spread Spectrum in the frequency table.

0 = Normal 1 = Spread Spectrum enabled

7

EN_SPSP

0

6

5

4

3

2

SSEL [4]

SSEL [3]

SSEL [2]

SSEL [1]

SSEL [0]

0

Frequency selection by software via I²C.

Enable software program FS [4:0].

1

EN_SSEL

0

0 = Select frequency by hardware.

1= Select frequency by software I²C - Bit 6 ~ 2.

Enable reload safe frequency when the watchdog is timeout.

0 = reload the FS [4:0] latched pins when watchdog time out.

1 = reload the safe frequency bit defined at Register 5 bit 4~0.

0

EN_SAFE_FREQ

0

7.2 Register 1: CPU Clock Register (1 = enable, 0 = Stopped)

BIT

7

6

5

4

3

2

1

0

PIN NO

44,45

37,38

PWD

1

X

DESCRIPTION

CPUCLK_T2 / C2

CPUCLK_T1 / C1

CPUCLK_T0 / C0

FS [4] Read back.

FS [3] Read back

FS [2] Read back

FS [1] Read back

FS [0] Read back

40,41

-

7.3 Register 2: PCI Clock Register (1 = enable, 0 = Stopped)

BIT

7

6

5

4

3

2

1

0

PIN NO

PWD

DESCRIPTION

MULTISEL0 trapping pin data read back

48

17

16

15

14

12

11

10

X

1

PCICLK6

PCICLK5

PCICLK4

PCICLK3

PCICLK2

PCICLK1

PCICLK0

Publication Release Date: March 2006

Revision 2.1

- 7 -

W83194BR-323W83194BG-323

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

7.4 Register 3: PCI, 48MHz Clock Register (1 = enable, 0 = Stopped)

BIT

7

6

5

4

3

2

1

0

PIN NO

PWD

DESCRIPTION

22

23

48

1

48MHZ

24_48MHz

REF0

REF1

Reserved

PCICLK_F2

PCICLK_F1

PCICLK_F0

8

7

6

7.5 Register 4: 3V66 Control Register (1 = enable, 0 = Stopped)

BIT

7

6

5

4

3

2

1

0

PIN NO

PWD

DESCRIPTION

-

27

28

30

31

1

Reserved

3V66_3 / 48MHz

3V66_2

3V66_1

3V66_0

7.6 Register 5: Watchdog Control Register

BIT

7

6

NAME

MULTISEL1

EN_WD

PWD

X

0

DESCRIPTION

MULTISEL1 trapping pin data read back

Enable Watchdog Timer if set to 1. Set to 0, disable watchdog timer.

Read this bit will return a counting state. If timer continues down count,

this bit will return 1. Otherwise, this bit will return 0.

5

WD_TIMEOUT

0

Watchdog Timeout Status. If the watchdog is started and timer down

counts to zero, this bit will be set to 1. Clear this bit to logic 0, If set to 1,

when the watchdog is restart in the next time. This bit is Read Only.

4

3

2

1

0

SAF_FREQ [4]

SAF_FREQ [3]

SAF_FREQ [2]

SAF_FREQ [1]

SAF_FREQ [0]

0

Watchdog safe frequency bits. These bits will be reloaded into FS [4:0],

if the watchdog is timeout and enable reload safe frequency bits.

- 8 -

W83194BR-323W83194BG-323

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

7.7 Register 6: Watchdog Timer Register

BIT

7

6

5

4

3

2

1

0

NAME

PWD

DESCRIPTION

WD_TIME [7]

WD_TIME [6]

WD_TIME [5]

WD_TIME [4]

WD_TIME [3]

WD_TIME [2]

WD_TIME [1]

WD_TIME [0]

0

1

0

Watchdog timeout time. The bit resolution is 250mS. The default time is

8*250mS = 2.0 seconds. If the watchdog timer is start, this register will

be down count. Read this register will return a down count value.

7.8 Register 7: M/N Program Register

BIT

7

6

5

4

3

2

1

0

NAME

N_DIV [8]

TEST1

PWD

DESCRIPTION

1

0

1

0

1

Programmable N divisor value. Bit 7 ~0 are defined in the Register 8.

Test bit 1. Winbond test bit, do not change them.

Test bit 0. Winbond test bit, do not change them.

TEST0

M_DIV [4]

M_DIV [3]

M_DIV [2]

M_DIV [1]

M_DIV [0]

Programmable M divisor value.

7.9 Register 8: M/N Program Register

BIT

7

6

5

4

3

2

1

0

NAME

N_DIV [7]

N_DIV [6]

N_DIV [5]

N_DIV [4]

N_DIV [3]

N_DIV [2]

N_DIV [1]

N_DIV [0]

PWD

DESCRIPTION

0

1

0

1

Programmable N divisor value bit 7 ~0. The bit 8 is defined in Register 7.

Publication Release Date: March 2006

- 9 -

Revision 2.1

W83194BR-323W83194BG-323

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

7.10 Register 9: Spread Spectrum Programming Register

BIT

7

6

5

4

3

2

1

0

NAME

SP_UP [3]

SP_UP [2]

SP_UP [1]

PWD

DESCRIPTION

Spread Spectrum Up Counter bit 3.

0

1

Spread Spectrum Up Counter bit 2.

Spread Spectrum Up Counter bit 1.

Spread Spectrum Up Counter bit 0

Spread Spectrum Down Counter bit 3

Spread Spectrum Down Counter bit 2

Spread Spectrum Down Counter bit 1

Spread Spectrum Down Counter bit 0

SP_UP [0]

SP_DOWN [3]

SP_DOWN [2]

SP_DOWN [1]

SP_DOWN [0]

7.11 Register 10: Divisor and Step-less Enable and Skew Control Register

BIT

7

NAME

EN_MN_PROG

PWD

0

DESCRIPTION

0: use frequency table

1: use M/N register to program frequency

The equation is VCO freq. = 14.318MHz * (N+4)/ M. When the

watchdog timer is timeout, this will be clear. In this time, the

frequency is set to hardware default latched or safe frequency

set by EN_SFAE_FREQ (Register 0 bit 0).

6

5

4

3

2

1

0

RATIO_SEL [3]

RATIO_SEL [2]

RATIO_SEL [1]

RATIO_SEL [0]

CPU_3V66_SKEW [2]

CPU_3V66_SKEW [1]

CPU_3V66_SKEW [0]

0

1

0

1

0

CPU, 3V66, and PCI ratio selection. The ratio is shown as

following table.

CPU to 3V66 skew.

Table of CPU, 3V66, and PCI clock selection.

I2C Reg10 Definition

REG10

BIT6

REG10

BIT5

REG10

BIT4

REG10

BIT3

CPU 3V66

PCI

SSEL3

SSEL2

SSEL1

SSEL0 RATIO RATIO RATIO

0

1

0

1

0

1

0

1

0

1

2

3

4

6

5

6

8

6

10

12

16

12

- 10 -

W83194BR-323W83194BG-323

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

7.12 Register 11: Winbond Chip ID Register (Read Only)

BIT

7

6

5

4

3

2

1

0

NAME

PWD

DESCRIPTION

Winbond Chip ID. W83194BR-323 is 0x57.

Winbond Chip ID.

CHPI_ID [7]

CHPI_ID [6]

CHPI_ID [5]

CHPI_ID [4]

CHPI_ID [3]

CHPI_ID [2]

CHPI_ID [1]

CHPI_ID [0]

0

1

0

1

0

1

7.13 Register 12: Winbond Chip ID Register (Read Only)

BIT

7

6

5

4

3

2

1

0

NAME

SUB_ID [3]

SUB_ID [2]

SUB_ID [1]

SUB_ID [0]

VER_ID [3]

VER_ID [2]

VER_ID [1]

VER_ID [0]

PWD

DESCRIPTION

The sub-chip ID of W83194BR-323 is defined as 0010b.

Winbond Sub-Chip ID.

Winbond Version ID. The Version ID of W83194BR-323 is 0010b.

Winbond Version ID.

0

1

0

1

0

Winbond Version ID.

7.14 Register 13: Reserved

BIT

7

6

5

4

3

2

1

0

NAME

Reserved

PWD

DESCRIPTION

0

1

0

1

Reserved

Publication Release Date: March 2006

Revision 2.1

- 11 -

W83194BR-323W83194BG-323

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

7.15 Register 14: CPU to PCI Skew Control

BIT

7

6

5

4

3

2

1

0

NAME

Reserved

PWD

DESCRIPTION

1

0

1

0

Reserved

CPU_PCI_SKEW [2]

CPU_PCI_SKEW [1]

CPU_PCI_SKEW [0]

Reserved

CPU to PCI Skew

Reserved

7.16 Register 15: SEL24_48 and SEL48_66 Control

BIT

7

NAME

SEL24_48

PWD

X

DESCRIPTION

In power on reset period, it is a hardware-latched pin, and it can

be R/W by I2C control after power on reset period. 0-> 24 MHz,

1->48MHz.

6

SEL_48_66

X

In power on reset period, it is a hardware-latched pin, and it can

be R/W by I2C control after power on reset period. 0-> 48 MHz,

1->66MHz.

5

4

3

2

1

0

Reserved

0

1

Reserved for Winbond internal use, do not change them

- 12 -

W83194BR-323W83194BG-323

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

8. ACCESS INTERFACE

The W83194BR-323 provides I²C Serial Bus for microprocessor to read/write internal registers. In the

W83194BR-323 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I²C

address is defined at 0xD2.

Block Read and Block Write Protocol

8.1 Block Write protocol

8.2 Block Read protocol

## In block mode, the command code must filled 8’h00

8.3 Byte Write protocol

8.4 Byte Read protocol

Publication Release Date: March 2006

- 13 -

Revision 2.1

W83194BR-323W83194BG-323

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

9. ORDERING INFORMATION

PART NUMBER

PACKAGE TYPE

48 PIN SSOP

PRODUCTION FLOW

W83194BR-323

Commercial, 0°C to +70°C

48 PIN SSOP

(Lead free package)

W83194BG-323

Commercial, 0°C to +70°C

10. HOW TO READ THE TOP MARKING

W83194BR-323

28051234

W83194BG-323

28051234

514GAB

1st line: Winbond logo and the type number:

Normal part:W83194BR-323, Lead free part:W83194BG-323

2nd line: Tracking code 2 8051234

2: wafers manufactured in Winbond FAB 2

8051234: wafer production series lot number

3rd line: Tracking code 514 G BB

514: packages made in '2005, week 14

G: assembly house ID; O means OSE, G means GR

A: Internal use code

B: IC revision

All the trademarks of products and companies mentioned in this data sheet belong to their respective

owners.

- 14 -

W83194BR-323W83194BG-323

STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET

11. PACKAGE DRAWING AND DIMENSIONS

Please note that all data and specifications are subject to change without notice. All the trade marks

of products and companies mentioned in this data sheet belong to their respective owners.

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal

instruments, combustion control instruments, or for other applications intended to support or

sustain life. Further more, Winbond products are not intended for applications wherein failure

of Winbond products could result or lead to a situation wherein personal injury, death or

severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.

Headquarters

Winbond Electronics Corporation America

Winbond Electronics (Shanghai) Ltd.

27F, 2299 Yan An W. Rd. Shanghai,

200336 China

No. 4, Creation Rd. III,

2727 North First Street, San Jose,

CA 95134, U.S.A.

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 86-21-62365999

TEL: 1-408-9436666

TEL: 886-3-5770066

FAX: 1-408-5441798

FAX: 86-21-62365998

FAX: 886-3-5665577

http://www.winbond.com.tw/

Taipei Office

Winbond Electronics Corporation Japan

7F Daini-ueno BLDG, 3-7-18

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.

Shinyokohama Kohoku-ku,

Yokohama, 222-0033

TEL: 81-45-4781881

No. 378 Kwun Tong Rd.,

Kowloon, Hong Kong

TEL: 852-27513100

TEL: 886-2-8177-7168

FAX: 886-2-8751-3579

FAX: 81-45-4781800

FAX: 852-27552064

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Publication Release Date: March 2006

Revision 2.1

- 15 -

型号:	W83194BG-323
是否Rohs认证：	符合
生命周期：	Obsolete
IHS 制造商：	NUVOTON TECHNOLOGY CORP
包装说明：	SSOP, SSOP48,.4
Reach Compliance Code：	unknown
风险等级：	5.82
JESD-30 代码：	R-PDSO-G48
端子数量：	48
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP
封装等效代码：	SSOP48,.4
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH
电源：	3.3 V
认证状态：	Not Qualified
子类别：	Clock Generators
标称供电电压：	3.3 V
表面贴装：	YES
温度等级：	COMMERCIAL
端子形式：	GULL WING
端子节距：	0.635 mm
端子位置：	DUAL

电子百科

产品导航

产品型号W83194BG-323的Datasheet PDF文件预览

W83194BG相关产品

W83194BG相关文章

IC37:专业IC行业平台