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    产品型号W83194AR-73的Datasheet PDF文件预览

    W83194AR-73  
    150MHZ CLOCK FOR WHITNEY CHIPSET  
    1.0 GENERAL DESCRIPTION  
    The W83194AR-73 is a Clock Synthesizer for Intel Whitney chipset. W83194AR-73 provides all  
    clocks required for high-speed RISC or CISC microprocessor and also provides 32 different  
    frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally  
    selectable with smooth transitions.  
    The W83194AR-73 provides I2C serial bus interface to program the registers to enable or disable  
    each clock outputs and provides 0.25% center and 0-0.5% down type spread spectrum to reduce EMI.  
    The W83194AR-73 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.  
    High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30  
    pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as  
    maintaining 50¡ Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide  
    better than 0.5V /ns slew rate.  
    1.0 PRODUCT FEATURES  
    ·
    ·
    ·
    ·
    2 CPU clocks  
    9 SDRAM clocks for 2 DIMMs  
    8 PCI synchronous clocks.  
    Optional single or mixed supply:  
    (VDDR = VDDP=VDDS = VDD48 = VDD3 = 3.3V, VDDA=VDDC=2.5V)  
    Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns  
    Smooth frequency switch with selections from 66.8 to 150MHz  
    I2C 2-Wire serial interface and I2C read back  
    0.25% center and 0-0.5% down type spread spectrum  
    Programmable registers to enable/stop each output and select modes  
    (mode as Tri-state or Normal )  
    ·
    ·
    ·
    ·
    ·
    ·
    ·
    48 MHz for USB  
    24 MHz for super I/O  
    ·
    Packaged in 48-pin SSOP  
    Publication Release Date: May 1999  
    Revision 0.40  
    - 1 -  
    W83194AR-73  
    PRELIMINARY  
    3.0 PIN CONFIGURATION  
    REF1/*SEL_3V66  
    VDDR  
    1
    2
    3
    4
    5
    6
    7
    8
    9
    VddA  
    IOAPIC  
    VDDC  
    CPUCLK0  
    CPUCLK1  
    VSS  
    48  
    47  
    46  
    45  
    44  
    43  
    42  
    41  
    40  
    39  
    38  
    Xin  
    Xout  
    VSS  
    VSS  
    3V66-0  
    3V66-1  
    VDD3  
    VDDP  
    VSS  
    SDRAM 0  
    SDRAM 1  
    SDRAM 2  
    VDDS  
    10  
    11  
    12  
    PCICLK0/ *FS0  
    PCICLK1/ *FS1  
    PCICLK2/*SEL24_48#  
    37  
    36  
    35  
    34  
    33  
    32  
    31  
    30  
    SDRAM 3  
    13  
    14  
    15  
    16  
    17  
    18  
    19  
    20  
    21  
    22  
    23  
    24  
    SDRAM 4  
    SDRAM 5  
    VSS  
    SDRAM 6  
    SDRAM 7  
    SDRAM_F  
    VDDS  
    VSS  
    24_48MHz/ *FS2  
    48MHz-0  
    48MHz-1/ *FS3  
    VSS  
    PCICLK3  
    PCICLK4  
    PCICLK5  
    VDDP  
    PCICLK6  
    PCICLK7  
    29  
    28  
    27  
    26  
    25  
    VSS  
    PD#  
    *SDCLK  
    *SDATA  
    VDD48  
    Publication Release Date: May 1999  
    Revision 0.30  
    - 2 -  
    W83194AR-73  
    PRELIMINARY  
    4.0 FREQUENCY SELECTION BY HARDWARE  
    FS3 FS2 FS1 FS0 CPU(MHz) SDRAM  
    (MHz)  
    3V66 (MHz)  
    PCI(MHz) IOAPIC  
    (MHz)  
    SEL_3V66=0 SEL_3V66=1  
    0
    0
    0
    0
    0
    0
    0
    0
    1
    1
    1
    1
    1
    1
    1
    1
    0
    0
    0
    0
    1
    1
    1
    1
    0
    0
    0
    0
    1
    1
    1
    1
    0
    0
    1
    1
    0
    0
    1
    1
    0
    0
    1
    1
    0
    0
    1
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    100.23  
    100.9  
    105  
    100.23  
    100.9  
    105  
    66.82  
    67.26  
    70  
    33.41  
    33.63  
    35  
    16.71  
    16.815  
    17.5  
    66.82  
    67.26  
    70  
    66.89  
    120  
    100.33  
    120  
    66.89  
    64  
    66.89  
    80  
    33.44  
    40  
    16.72  
    20.00  
    20.67  
    22.22  
    16.66  
    17.5  
    124  
    124  
    64  
    82.66  
    88.86  
    66.65  
    70  
    41.33  
    44.43  
    33.32  
    35  
    133.3  
    133.6  
    140  
    133.3  
    100.2  
    140  
    66.65  
    66.65  
    70  
    150  
    150  
    64  
    75  
    37.50  
    38.33  
    35  
    18.75  
    19.17  
    17.5  
    114.99  
    70  
    114.99  
    105  
    64  
    76.66  
    70  
    70  
    75  
    112.5  
    124.96  
    90  
    64  
    75  
    37.5  
    41.65  
    30  
    18.75  
    20.825  
    15  
    83.31  
    90  
    64  
    83.31  
    60  
    60  
    95  
    95  
    63.33  
    63.33  
    31.67  
    15.84  
    5.0 SERIAL CONTROL REGISTERS  
    The Pin column lists the affected pin number and the @PowerUp column gives the state at true  
    power up. Registers are set to the values shown only on true power up. "Command Code" byte and  
    "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data  
    (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge.  
    After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and  
    acknowledged.  
    Publication Release Date: May 1999  
    - 3 -  
    Revision 0.30  
    W83194AR-73  
    PRELIMINARY  
    5.1 Register 0: CPU Frequency Select Register  
    Bit  
    @PowerUp  
    Pin  
    Description  
    7
    0
    -
    0 = ¡ Ó0.25% Center type Spread Spectrum Modulation  
    1 = 0~ 0.5% Down type Spread Spectrum Modulation  
    SSEL2 ( Frequency table selection by software via I2C)  
    SSEL1 ( Frequency table selection by software via I2C)  
    SSEL0 ( Frequency table selection by software via I2C)  
    0 = Selection by hardware  
    6
    5
    4
    3
    0
    0
    0
    0
    -
    -
    -
    -
    1 = Selection by software I2C - Bit (2, 6:4), Register1 Bit1  
    SSEL3 (Frequency table selection by software via I2C )  
    0 = Normal  
    2
    1
    0
    0
    -
    -
    1 = Spread Spectrum enabled  
    0
    0
    -
    0 = Running  
    1 = Tristate all outputs  
    5.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive)  
    Bit  
    7
    @PowerUp  
    Pin  
    -
    Description  
    X
    X
    X
    1
    1
    1
    1
    1
    FS3#  
    6
    -
    FS0#  
    5
    -
    FS2#  
    4
    28  
    27  
    26  
    -
    24_48MHz(Active / Inactive)  
    48MHz-0(Active / Inactive)  
    48MHz-1(Active / Inactive)  
    3
    2
    SEL_3V66(Frequency table selection by software via I2C )  
    1
    0
    31  
    SDRAM_F(Active / Inactive)  
    5.3 Register 2: SDRAM Clock Register (1 = Active, 0 = Inactive)  
    Bit  
    7
    @PowerUp  
    Pin  
    32  
    33  
    35  
    36  
    37  
    39  
    40  
    41  
    Description  
    1
    1
    1
    1
    1
    1
    1
    1
    SDRAM7 (Active / Inactive)  
    SDRAM6 (Active / Inactive)  
    SDRAM5 (Active / Inactive)  
    SDRAM4 (Active / Inactive)  
    SDRAM3 (Active / Inactive)  
    SDRAM2 (Active / Inactive)  
    SDRAM1 (Active / Inactive)  
    SDRAM0 (Active / Inactive)  
    6
    5
    4
    3
    2
    1
    0
    Publication Release Date: May 1999  
    Revision 0.30  
    - 4 -  
    W83194AR-73  
    PRELIMINARY  
    5.4 Register 3: PCI Clock Register (1 = Active, 0 = Inactive)  
    Bit  
    7
    @PowerUp  
    Pin  
    20  
    19  
    17  
    16  
    15  
    13  
    12  
    11  
    Description  
    1
    1
    1
    1
    1
    1
    1
    1
    PCICLK7 (Active / Inactive)  
    PCICLK6 (Active / Inactive)  
    PCICLK5 (Active / Inactive)  
    PCICLK4 (Active / Inactive)  
    PCICLK3 (Active / Inactive)  
    PCICLK2 (Active / Inactive)  
    PCICLK1 (Active / Inactive)  
    PCICLK0 (Active / Inactive)  
    6
    5
    4
    3
    2
    1
    0
    5.5 Register 4: Additional Register (1 = Active, 0 = Inactive)  
    Bit  
    7
    @PowerUp  
    Pin  
    -
    Description  
    X
    1
    1
    0
    1
    X
    SEL_3V66#  
    6
    8
    3V66_1(Active / Inactive)  
    3V66_0(Active / Inactive)  
    Reserve  
    5
    7
    4
    -
    3
    47  
    IOAPIC (Active / Inactive)  
    FS1#  
    2
    -
    1
    1
    1
    44  
    45  
    CPUCLK1(Active / Inactive)  
    CPUCLK0(Active / Inactive)  
    0
    5.6 Register 5: Reserve Register  
    Bit  
    7
    @PowerUp  
    Pin  
    Description  
    0
    0
    0
    0
    0
    0
    0
    0
    -
    -
    -
    -
    -
    -
    -
    -
    Reserve  
    Reserve  
    Reserve  
    Reserve  
    Reserve  
    Reserve  
    Reserve  
    Reserve  
    6
    5
    4
    3
    2
    1
    0
    Publication Release Date: May 1999  
    Revision 0.30  
    - 5 -  
    W83194AR-73  
    PRELIMINARY  
    5.7 Register 6: Winbond Chip ID Register (Read Only)  
    Bit  
    7
    @PowerUp  
    Pin  
    Description  
    1
    0
    0
    1
    0
    0
    1
    0
    -
    -
    -
    -
    -
    -
    -
    -
    Winbond Chip ID  
    Winbond Chip ID  
    Winbond Chip ID  
    Winbond Chip ID  
    Winbond Chip ID  
    Winbond Chip ID  
    Winbond Chip ID  
    Winbond Chip ID  
    6
    5
    4
    3
    2
    1
    0
    5.8 Register 7: Winbond Chip ID Register (Read Only)  
    Bit  
    7
    @PowerUp  
    Pin  
    Description  
    0
    0
    0
    0
    0
    0
    1
    0
    -
    -
    -
    -
    -
    -
    -
    -
    Winbond Chip ID  
    Winbond Chip ID  
    Winbond Chip ID  
    Winbond Chip ID  
    Winbond Chip ID  
    Winbond Chip ID  
    Winbond Chip ID  
    Winbond Chip ID  
    6
    5
    4
    3
    2
    1
    0
    Publication Release Date: May 1999  
    Revision 0.30  
    - 6 -  
    W83194AR-73  
    PRELIMINARY  
    6.0 SPECIFICATIONS  
    6.1 ABSOLUTE MAXIMUM RATINGS  
    Stresses greater than those listed in this table may cause permanent damage to the device.  
    Precautions should be taken to avoid application of any voltage higher than the maximum rated  
    voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability.  
    Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd).  
    Symbol  
    Vdd , VIN  
    TSTG  
    Parameter  
    Rating  
    Voltage on any pin with respect to GND  
    - 0.5 V to + 7.0 V  
    Storage Temperature  
    Ambient Temperature  
    Operating Temperature  
    - 65°C to + 150°C  
    - 55°C to + 125°C  
    0°C to + 70°C  
    TB  
    TA  
    6.2 AC CHARACTERISTICS  
    VddR=Vdd3=VddP=VddS=3.3V  
    ±
    5 %, VddC = VddA= 2.375V~2.9V , TA = 0  
    °
    C to +70  
    Test Conditions  
    Measured at 1.5V  
    °C  
    Parameter  
    Symbol Min  
    Typ  
    Max  
    55  
    4
    Units  
    %
    Output Duty Cycle  
    45  
    50  
    CPU/SDRAM to PCI Offset  
    1
    ns  
    15 pF Load Measured at 1.5V  
    15 pF Load Measured at 1.5V  
    tOFF  
    Skew (CPU-CPU), (PCI-  
    PCI), (SDRAM-SDRAM)  
    250  
    ps  
    tSKEW  
    ¡ Ó  
    250  
    CPU/SDRAM  
    ps  
    tCCJ  
    Cycle to Cycle Jitter  
    CPU/SDRAM  
    500  
    ps  
    KHz  
    ns  
    tJA  
    Absolute Jitter  
    Jitter Spectrum 20 dB  
    Bandwidth from Center  
    Output Rise (0.4V ~ 2.0V)  
    & Fall (2.0V ~0.4V) Time  
    BWJ  
    500  
    1.6  
    0.4  
    15 pF Load on CPU and PCI  
    outputs  
    tTLH  
    tTHL  
    Overshoot/Undershoot  
    Beyond Power Rails  
    Ring Back Exclusion  
    Vover  
    0.7  
    0.7  
    1.5  
    2.1  
    V
    V
    22 W at source of 8 inch PCB  
    run to 15 pF load  
    VRBE  
    Ring Back must not enter this  
    range.  
    Publication Release Date: May 1999  
    Revision 0.30  
    - 7 -  
    W83194AR-73  
    PRELIMINARY  
    6.3 DC CHARACTERISTICS  
    VddR=Vdd3=VddP=VddS=3.3V  
    ±
    5 %, VddC = VddA= 2.375V~2.9V , TA = 0  
    °
    C to +70  
    °C  
    Parameter  
    Symbol Min  
    Typ  
    Max  
    Units  
    Test Conditions  
    Input Low Voltage  
    Vss-  
    0.3  
    0.8  
    VIL  
    VIH  
    IIL  
    Vdc  
    Input High Voltage  
    2.0  
    Vdd  
    +0.3  
    Vdc  
    mA  
    mA  
    mA  
    Input Low Current  
    (no pull-up Resistors)  
    -5  
    2.0  
    Input Low Current  
    (pull-up Resistors)  
    -200  
    -5  
    -100  
    IIL  
    Input High Current  
    5
    IIH  
    IDD  
    Operating Current  
    Power Down Current  
    Input Frequency  
    Pin Inductance  
    60  
    400  
    100  
    600  
    mA  
    mA  
    @66M  
    IDDPD  
    Fi  
    CL= 0pF  
    14.318  
    7
    MHz  
    nH  
    Vdd=3.3V  
    Lpin  
    CIN  
    Input Capacitance  
    5
    pF  
    Logic Inputs  
    COUT  
    CINX  
    TTra  
    T
    6
    pF  
    Output pins capacitance  
    X1 & X2 pins  
    13.5  
    1
    22.5  
    3
    pF  
    Transition Time  
    mS  
    nS  
    Disable/Enable Delay  
    Clock stabilization  
    10  
    3
    TSTA  
    mS  
    Publication Release Date: May 1999  
    Revision 0.30  
    - 8 -  
    W83194AR-73  
    PRELIMINARY  
    7.0 ORDERING INFORMATION  
    Part Number  
    Package Type  
    Production Flow  
    W83194AR-73  
    48 PIN SSOP  
    Commercial, 0°C to +70°C  
    8.0 HOW TO READ THE TOP MARKING  
    W83194AR-73  
    28051234  
    814GBB  
    1st line: Winbond logo and the type number: W83194AR-73  
    2nd line: Tracking code 2 8051234  
    2: wafers manufactured in Winbond FAB 2  
    8051234: wafer production series lot number  
    3rd line: Tracking code 814 G B B  
    814: packages made in '98, week 14  
    G: assembly house ID; A means ASE, S means SPIL, G means GR  
    BB: IC revision  
    All the trade marks of products and companies mentioned in this data sheet belong to their  
    respective owners.  
    Publication Release Date: May 1999  
    - 9 -  
    Revision 0.30  
    W83194AR-73  
    PRELIMINARY  
    9.0 PACKAGE DRAWING AND DIMENSIONS  
    Headquarters  
    No. 4, Creation Rd. III  
    Science-Based Industrial Park  
    Hsinchu, Taiwan  
    TEL: 886-35-770066  
    Winbond Electronics  
    (North America) Corp.  
    2730 Orchard Parkway  
    San Jose, CA 95134 U.S.A.  
    TEL: 1-408-9436666  
    Winbond Electronics (H.K.) Ltd.  
    Rm. 803, World Trade Square, Tower II  
    123 Hoi Bun Rd., Kwun Tong  
    Kowloon, Hong Kong  
    TEL: 852-27516023-7  
    FAX: 852-27552064  
    FAX: 886-35-789467  
    www: http://www.winbond.com.tw/  
    FAX: 1-408-9436668  
    Taipei Office  
    11F, No. 115, Sec. 3, Min-Sheng East Rd.  
    Taipei, Taiwan  
    TEL: 886-2-7190505  
    FAX: 886-2-7197502  
    TLX: 16485 WINTPE  
    Please note that all data and specifications are subject to change without notice. All the trade  
    marks of products and companies mentioned in this data sheet belong to their respective  
    owners.  
    These products are not designed for use in life support appliances, devices, or systems  
    where malfunction of these products can reasonably be expected to result in personal injury.  
    Winbond customers using or selling these products for use in such applications do so at their  
    own risk and agree to fully indemnify Winbond for any damages resulting from such improper  
    use or sale.  
    Publication Release Date: May 1999  
    - 10 -  
    Revision 0.30  
    配单直通车
    W83194AR-73产品参数
    型号:W83194AR-73
    是否Rohs认证： 不符合
    生命周期：Obsolete
    IHS 制造商：WINBOND ELECTRONICS CORP
    零件包装代码：SSOP
    包装说明：SSOP-48
    针数：48
    Reach Compliance Code：not_compliant
    ECCN代码：EAR99
    HTS代码：8542.39.00.01
    风险等级：5.81
    其他特性：ALSO OPERATES AT 3.3V SUPPLY
    JESD-30 代码：R-PDSO-G48
    JESD-609代码：e0
    长度：15.875 mm
    端子数量：48
    最高工作温度：70 °C
    最低工作温度：
    最大输出时钟频率：150 MHz
    封装主体材料：PLASTIC/EPOXY
    封装代码：SSOP
    封装等效代码：SSOP48,.4
    封装形状：RECTANGULAR
    封装形式：SMALL OUTLINE, SHRINK PITCH
    峰值回流温度（摄氏度）：NOT SPECIFIED
    电源：2.5,3.3 V
    主时钟/晶体标称频率：14.318 MHz
    认证状态：Not Qualified
    座面最大高度：2.794 mm
    子类别：Clock Generators
    最大压摆率：100 mA
    最大供电电压：2.9 V
    最小供电电压：2.375 V
    标称供电电压：2.5 V
    表面贴装：YES
    技术：CMOS
    温度等级：COMMERCIAL
    端子面层：Tin/Lead (Sn/Pb)
    端子形式：GULL WING
    端子节距：0.635 mm
    端子位置：DUAL
    处于峰值回流温度下的最长时间：NOT SPECIFIED
    宽度：7.5 mm
    uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFIC
    Base Number Matches：1
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