W83194BR-372
Table of Contents-
1.
2.
3.
4.
5.
GENERAL DESCRIPTION ......................................................................................................... 1
PRODUCT FEATURES .............................................................................................................. 1
PIN CONFIGURATION............................................................................................................... 2
BLOCK DIAGRAM ...................................................................................................................... 2
PIN DESCRIPTION..................................................................................................................... 3
5.1
5.2
5.3
5.4
5.5
5.6
Crystal I/O.............................................................................................................................3
CPU, AGP, ZCLK and PCI, IOAPIC Clock Outputs............................................................3
Fixed Frequency Outputs.....................................................................................................4
I2C Control Interface.............................................................................................................4
Power Management Pins.....................................................................................................4
Power Pins............................................................................................................................4
6.
7.
FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 5
I2C CONTROL AND STATUS REGISTERS............................................................................... 6
7.1
7.2
7.3
Register 0: Frequency Select (Default = 40h).....................................................................6
Register 1: CPU Clock (1 = Enable, 0 = Stopped) (Default: 68h).......................................6
Register 2: PCI Clock (1 = Enable, 0 = Stopped) (Default: FFh)........................................6
7.4
Register 3: AGP, 24_48MHz, 48MHz, REF Control (1 =Enable, 0 =Stopped) (Default:
7
FFh)
7.5
7.6
7.7
7.8
Register 4: IOAPIC, ZCLK Control (1 = Enable, 0 = Stopped) (Default: F0h) ...................7
Register 5: 24_48MHz Control (Default: 88h).....................................................................7
Register 6: M/N (Default: 90h) .............................................................................................8
Register 7: N (Default: BBh).................................................................................................8
Register 8: Winbond Chip ID (Default: 72h) (Read only)....................................................8
Register 9: Reserved (Default: 50h) (Read only)................................................................9
Register 10: M/N Program (Default: 04h)............................................................................9
Register 11: Spread Spectrum Programming (Default: 0Eh) ...........................................10
Register 12: Divisor and Step-less Enable Control (Default: 88h)....................................10
Register 13: FIX Mode Control (Default: 0Fh)...................................................................12
Register 14: Fix Mode Control (Default: 2Ch) ...................................................................12
Register 15: Skew Control (Default: E4h)..........................................................................13
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
8.
ACCESS INTERFACE.............................................................................................................. 14
8.1
8.2
Block Write Protocol...........................................................................................................14
Block Read Protocol...........................................................................................................14
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