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    • W83194BR-341
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    产品型号W83194BR-372的Datasheet PDF文件预览

    W83194BR-372  
    WINBOND  
    CLOCK GENERATOR  
    FOR SIS 746/748 CHIPSETS  
    Publication Release Date: April 13, 2005  
    Revision 1.1  
    - I -  
    W83194BR-372  
    Table of Contents-  
    1.  
    2.  
    3.  
    4.  
    5.  
    GENERAL DESCRIPTION ......................................................................................................... 1  
    PRODUCT FEATURES .............................................................................................................. 1  
    PIN CONFIGURATION............................................................................................................... 2  
    BLOCK DIAGRAM ...................................................................................................................... 2  
    PIN DESCRIPTION..................................................................................................................... 3  
    5.1  
    5.2  
    5.3  
    5.4  
    5.5  
    5.6  
    Crystal I/O.............................................................................................................................3  
    CPU, AGP, ZCLK and PCI, IOAPIC Clock Outputs............................................................3  
    Fixed Frequency Outputs.....................................................................................................4  
    I2C Control Interface.............................................................................................................4  
    Power Management Pins.....................................................................................................4  
    Power Pins............................................................................................................................4  
    6.  
    7.  
    FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 5  
    I2C CONTROL AND STATUS REGISTERS............................................................................... 6  
    7.1  
    7.2  
    7.3  
    Register 0: Frequency Select (Default = 40h).....................................................................6  
    Register 1: CPU Clock (1 = Enable, 0 = Stopped) (Default: 68h).......................................6  
    Register 2: PCI Clock (1 = Enable, 0 = Stopped) (Default: FFh)........................................6  
    7.4  
    Register 3: AGP, 24_48MHz, 48MHz, REF Control (1 =Enable, 0 =Stopped) (Default:  
    7
    FFh)  
    7.5  
    7.6  
    7.7  
    7.8  
    Register 4: IOAPIC, ZCLK Control (1 = Enable, 0 = Stopped) (Default: F0h) ...................7  
    Register 5: 24_48MHz Control (Default: 88h).....................................................................7  
    Register 6: M/N (Default: 90h) .............................................................................................8  
    Register 7: N (Default: BBh).................................................................................................8  
    Register 8: Winbond Chip ID (Default: 72h) (Read only)....................................................8  
    Register 9: Reserved (Default: 50h) (Read only)................................................................9  
    Register 10: M/N Program (Default: 04h)............................................................................9  
    Register 11: Spread Spectrum Programming (Default: 0Eh) ...........................................10  
    Register 12: Divisor and Step-less Enable Control (Default: 88h)....................................10  
    Register 13: FIX Mode Control (Default: 0Fh)...................................................................12  
    Register 14: Fix Mode Control (Default: 2Ch) ...................................................................12  
    Register 15: Skew Control (Default: E4h)..........................................................................13  
    7.9  
    7.10  
    7.11  
    7.12  
    7.13  
    7.14  
    7.15  
    7.16  
    8.  
    ACCESS INTERFACE.............................................................................................................. 14  
    8.1  
    8.2  
    Block Write Protocol...........................................................................................................14  
    Block Read Protocol...........................................................................................................14  
    - II -  
    W83194BR-372  
    8.3  
    8.4  
    Byte Write Protocol.............................................................................................................14  
    Byte Read Protocol.............................................................................................................14  
    9.  
    SPECIFICATIONS .................................................................................................................... 15  
    9.1  
    9.2  
    9.3  
    9.4  
    9.5  
    9.6  
    9.7  
    9.8  
    9.9  
    Absolute Maximum Ratings ...............................................................................................15  
    General Operating Characteristics ....................................................................................15  
    Skew Group Timing Clock .................................................................................................15  
    CPU (Open Drain) Electrical Characteristics.....................................................................16  
    AGP, ZCLK Electrical Characteristics................................................................................16  
    PCI Electrical Characteristics.............................................................................................16  
    24M, 48M Electrical Characteristics ..................................................................................17  
    REF Electrical Characteristics............................................................................................17  
    IOAPIC Electrical Characteristics ......................................................................................17  
    10.  
    11.  
    12.  
    13.  
    ORDERING INFORMATION..................................................................................................... 18  
    HOW TO READ THE TOP MARKING...................................................................................... 18  
    PACKAGE DRAWING AND DIMENSIONS.............................................................................. 19  
    REVISION HISTORY................................................................................................................ 20  
    Publication Release Date: April 13, 2005  
    - III -  
    Revision 1.1  
    W83194BR-372  
    1. GENERAL DESCRIPTION  
    The W83194BR-372 is a Clock Synthesizer for SIS 746/748 chipset. W83194BR-372 provides all  
    clocks required for high-speed microprocessor and provides step-less frequency programming and 32  
    different frequencies of CPU, PCI, and AGP clocks setting, support two ZCLK clock outputs; all clocks  
    are externally selectable with smooth transitions.  
    The W83194BR-372 provides I2C serial bus interface to program the registers to enable or disable  
    each clock outputs and provides -0.5% and +/-0.25% center type spread spectrum or programmable  
    S.S.T. scale to reduce EMI.  
    The W83194BR-372 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.  
    2. PRODUCT FEATURES  
    •
    •
    •
    •
    •
    •
    •
    •
    •
    •
    •
    •
    •
    •
    •
    •
    •
    •
    1 2.5V open drain Differential pairs clock outputs for CPU  
    1 2.5V open drain singled-ended clock output for chipset host bus.  
    2 3.3V ZCLK clock outputs  
    2 AGP clock outputs  
    8 PCI synchronous clocks  
    2 2.5V IOAPIC clock outputs  
    1 24_48Mhz clock output for super I/O.  
    1 48 MHz clock output for USB.  
    3 14.318MHz REF clock outputs.  
    ZCLK/AGP/PCI clock out supports synchronous and asynchronous mode  
    Smooth frequency switch with selections from 100 to 200MHz  
    Step-less frequency programming  
    I2C 2-Wire serial interface and support byte read/write and block read/write.  
    -0.5% and +/- 0.25% center type spread spectrum  
    Programmable S.S.T. scale to reduce EMI  
    Programmable registers to enable/stop each output and select modes  
    Programmable clock outputs Skew control  
    48-pin SSOP package  
    Publication Release Date: April 13, 2005  
    Revision 1.1  
    - 1 -  
    W83194BR-372  
    3. PIN CONFIGURATION  
    48  
    47  
    46  
    45  
    44  
    43  
    42  
    41  
    40  
    39  
    38  
    37  
    36  
    35  
    34  
    33  
    32  
    31  
    30  
    29  
    28  
    27  
    26  
    25  
    VDDI  
    VDDREF  
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10  
    11  
    12  
    13  
    14  
    15  
    16  
    17  
    18  
    19  
    20  
    21  
    22  
    23  
    24  
    FS0&/REF0  
    FS1&/REF1  
    REF2  
    IOAPIC1  
    IOAPIC0  
    GND  
    CPU_STOP#*  
    CPUT1  
    VDDCPU  
    GND  
    CPUT0  
    CPUC0  
    VDDCPU  
    GND  
    GND  
    XIN  
    XOUT  
    GND  
    ZCLK0  
    ZCLK1  
    VDDZ  
    PCI_STOP#*  
    VDDPCI  
    FS2&/PCI_F0  
    FS3*/PCI_F1  
    PCI0  
    VDDA  
    SCLK*  
    SDATA*  
    PD#*  
    GND  
    PCI1  
    GND  
    VDDPCI  
    PCI2  
    PCI3  
    PCI4  
    PCI5  
    GND  
    AGP_0  
    AGP_1  
    VDDAGP  
    VDD48  
    48MHz  
    24_48MHz  
    GND  
    #: Active low  
    *: Internal pull up resistor 120K to VDD  
    &: Internal Pull-down resistor 120K to GND  
    4. BLOCK DIAGRAM  
    48MHz  
    PLL2  
    Divider  
    24_48MHz  
    3
    XTAL  
    OSC  
    XIN  
    XOUT  
    REF 0:2  
    PLL1  
    Spread  
    Spectrum  
    2
    VCOCLK  
    CPUT0:1  
    CPUC0  
    2
    ZCLK0:1  
    M/N/Ratio  
    ROM  
    2
    Divider  
    IOAPIC0:1  
    AGP 0:1  
    2
    8
    FS(0:3)  
    PD#*  
    Latch  
    &POR  
    PCI_F0:1,P  
    CI_0:5  
    Control  
    Logic  
    &Config  
    Register  
    PCI_STOP#*  
    CPU_STOP#*  
    SDATA*  
    SCLK*  
    I2C  
    Interface  
    - 2 -  
    W83194BR-372  
    5. PIN DESCRIPTION  
    BUFFER TYPE SYMBOL  
    DESCRIPTION  
    IN  
    INtp120k  
    INtd120k  
    OUT  
    OD  
    #
    Input  
    Latched input at power up, internal 120kΩ pull up.  
    Latched input at power up, internal 120kΩ pull down.  
    Output  
    Open Drain  
    Active Low  
    *
    &
    Internal 120kΩ pull-up  
    Internal 120 kΩ pull-down  
    5.1 Crystal I/O  
    PIN  
    PIN NAME  
    TYPE  
    DESCRIPTION  
    Crystal input with internal loading capacitors (18pF) and  
    feedback resistors.  
    6
    XIN  
    IN  
    Crystal output at 14.318MHz nominally with internal loading  
    capacitors (18pF).  
    7
    XOUT  
    OUT  
    5.2 CPU, AGP, ZCLK and PCI, IOAPIC Clock Outputs  
    PIN  
    PIN NAME  
    CPUT0  
    CPUC0  
    TYPE  
    DESCRIPTION  
    40,39  
    OD 2.5V open drain differential clock outputs for AMD K7 CPU  
    2.5V open drain singled –ended synchronize with CPUT0, For  
    43  
    CPUT1  
    OD  
    chipset host bus  
    31,30  
    9,10  
    AGP_0: 1  
    ZCLK0: 1  
    PCI_F0  
    OUT 3.3V AGP clock outputs.  
    OUT 3.3V ZCLK clock outputs, For MuTIOL bus.  
    OUT 3.3V PCI free running clock output.  
    14  
    15  
    Latched input for FS2 at initial power up for H/W selecting the  
    FS2&  
    PCI_F1  
    FS3*  
    INtd120k  
    output frequency. This is internal 120K pull down.  
    OUT 3.3V PCI free running clock output.  
    Latched input for FS3 at initial power up for H/W selecting the  
    INtp120k  
    output frequency, This is internal 120K pull up.  
    16, 17, 20,  
    21, 22, 23  
    47, 46  
    PCI [0:5]  
    OUT Low skew (< 250ps) PCI clock outputs.  
    OUT 2.5V IOAPIC outputs.  
    IOAPIC [0:1]  
    Publication Release Date: April 13, 2005  
    - 3 -  
    Revision 1.1  
    W83194BR-372  
    5.3 Fixed Frequency Outputs  
    PIN  
    PIN NAME  
    TYPE  
    DESCRIPTION  
    REF0  
    OUT  
    14.318MHz output.  
    2
    Latched input for FS0 at initial power up for H/W selecting the  
    FS0&  
    REF1  
    FS1&  
    INtd120k  
    OUT  
    output frequency. This is internal 120K pull down.  
    14.318MHz output.  
    3
    Latched input for FS1 at initial power up for H/W selecting the  
    INtd120k  
    output frequency. This is internal 120K pull down.  
    4
    27  
    REF2  
    48MHz  
    OUT  
    OUT  
    14.318MHz output.  
    48MHz clock output for USB.  
    24MHz (default) or 48MHz clock output, it could be R/W by I2C  
    26  
    24_48MHz  
    OUT  
    control after power on reset period. Select by register 5 bit 7.  
    5.4 I2C Control Interface  
    PIN  
    PIN NAME  
    TYPE  
    DESCRIPTION  
    Serial data of I2C 2-wire control interface with internal pull-up  
    resistor.  
    34  
    SDATA*  
    I/OD  
    Serial clock of I2C 2-wire control interface with internal pull-up  
    resistor.  
    35  
    SCLK*  
    IN  
    5.5 Power Management Pins  
    PIN  
    PIN NAME  
    TYPE  
    DESCRIPTION  
    Power Down Function. This is power down pin, low active (PD#).  
    Internal 120K pull up  
    33  
    PD#*  
    INtp120k  
    Active low, Stop all PCI clock output besides the free running  
    12  
    44  
    PCI_STOP#* INtp120k  
    clocks.  
    CPU_STOP#* INtp120k Active low, Stop all CPU clock outputs.  
    5.6 Power Pins  
    PIN  
    1
    13,19  
    29  
    38,42  
    28  
    11  
    PIN NAME TYPE  
    DESCRIPTION  
    PWR 3.3V power supply for REF.  
    PWR 3.3V power supply for PCI.  
    VDDREF  
    VDDPCI  
    VDDAGP  
    VDDCPU  
    VDD48  
    VDDZ  
    PWR 3.3V power supply for AGP.  
    PWR 2.5V power supply for CPU.  
    PWR 3.3V power supply for 48MHz.  
    PWR 3.3V power supply for ZCLK.  
    PWR 2.5V power supply for IOAPIC  
    PWR 3.3V power supply for Analog core logic.  
    48  
    36  
    VDDI  
    VDDA  
    5, 8, 18, 24, 25,  
    GND  
    PWR Ground pin  
    32, 37, 41, 45  
    - 4 -  
    W83194BR-372  
    6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE  
    This frequency table is used at power on latched FS [4:0] value or software programming at SSEL  
    [4:0] (Register 0 bit 7 ~ 3).  
    FS4 FS3 FS2 FS1 FS0 CPU (MHZ)  
    ZCLK (MHZ)  
    66.67  
    AGP (MHZ)  
    66.67  
    50.00  
    66.67  
    50.00  
    66.67  
    50.00  
    66.67  
    55.56  
    66.67  
    50.00  
    66.67  
    50.00  
    66.67  
    66.67  
    66.58  
    55.48  
    63.64  
    66.62  
    66.67  
    74.08  
    83.34  
    64.73  
    66.62  
    66.67  
    66.67  
    68.68  
    64.43  
    66.62  
    68.91  
    66.67  
    67.56  
    66.67  
    PCI (MHZ)  
    33.33  
    33.33  
    33.33  
    33.33  
    33.33  
    33.33  
    33.33  
    33.33  
    33.33  
    33.33  
    33.33  
    33.33  
    33.33  
    33.33  
    33.29  
    33.29  
    31.82  
    33.31  
    33.33  
    33.33  
    33.33  
    32.37  
    66.31  
    33.33  
    33.33  
    34.34  
    32.22  
    33.31  
    34.45  
    33.33  
    33.78  
    33.33  
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    0
    0
    0
    0
    0
    0
    0
    0
    1
    1
    1
    1
    1
    1
    1
    1
    0
    0
    0
    0
    0
    0
    0
    0
    1
    1
    1
    1
    1
    1
    1
    1
    0
    0
    0
    0
    1
    1
    1
    1
    0
    0
    0
    0
    1
    1
    1
    1
    0
    0
    0
    0
    1
    1
    1
    1
    0
    0
    0
    0
    1
    1
    1
    1
    0
    0
    1
    1
    0
    0
    1
    1
    0
    0
    1
    1
    0
    0
    1
    1
    0
    0
    1
    1
    0
    0
    1
    1
    0
    0
    1
    1
    0
    0
    1
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    133.34  
    133.34  
    133.34  
    133.34  
    133.34  
    133.34  
    133.34  
    133.34  
    100.00  
    100.00  
    100.00  
    100.00  
    100.00  
    166.67  
    110.97  
    110.97  
    114.55  
    119.91  
    133.34  
    133.34  
    133.34  
    145.64  
    149.89  
    166.67  
    111.12  
    137.37  
    144.97  
    149.89  
    155.04  
    166.67  
    180.17  
    200.01  
    66.67  
    100.00  
    100.00  
    133.34  
    133.34  
    166.67  
    166.67  
    66.67  
    66.67  
    100.00  
    100.00  
    133.34  
    133.34  
    166.45  
    166.45  
    95.45  
    99.93  
    83.34  
    111.12  
    133.34  
    116.51  
    99.93  
    111.12  
    133.34  
    137.37  
    144.97  
    149.89  
    124.03  
    133.34  
    135.13  
    133.34  
    Publication Release Date: April 13, 2005  
    Revision 1.1  
    - 5 -  
    W83194BR-372  
    7. I2C CONTROL AND STATUS REGISTERS  
    7.1 Register 0: Frequency Select (Default = 40h)  
    BIT  
    7
    6
    5
    4
    NAME  
    PWD  
    DESCRIPTION  
    SSEL [4]  
    SSEL [3]  
    SSEL [2]  
    SSEL [1]  
    SSEL [0]  
    0
    1
    0
    0
    0
    Frequency selection by software via I2C  
    3
    Enable software table selection FS [4:0].  
    0 = Hardware table setting (Jump mode).  
    2
    EN_SSEL  
    0
    1 = Software table setting through Bit7~3. (Jump less mode)  
    Enable spread spectrum mode under clock output.  
    0 = Spread Spectrum mode disable  
    1 = Spread Spectrum mode enable  
    Reserved  
    1
    0
    EN_SPSP  
    Reserved  
    0
    0
    7.2 Register 1: CPU Clock (1 = Enable, 0 = Stopped) (Default: 68h)  
    BIT  
    PIN NO  
    PWD  
    DESCRIPTION  
    7
    6
    5
    4
    Tri-state  
    0
    1
    1
    X
    Tri-state all output if set 1  
    CPUT1 output control  
    CPUT0 / C0 output control  
    Default: 0 (Read only)  
    43  
    40,39  
    -
    3
    2
    1
    0
    15  
    14  
    3
    X
    X
    X
    X
    Power on latched value of FS3 pin. Default: 1 (Read only)  
    Power on latched value of FS2 pin. Default: 0 (Read only)  
    Power on latched value of FS1 pin. Default: 0 (Read only)  
    Power on latched value of FS0 pin. Default: 0 (Read only)  
    2
    7.3 Register 2: PCI Clock (1 = Enable, 0 = Stopped) (Default: FFh)  
    BIT  
    PIN NO  
    PWD  
    DESCRIPTION  
    7
    6
    5
    4
    3
    2
    1
    0
    15  
    14  
    23  
    22  
    21  
    20  
    17  
    16  
    1
    1
    1
    1
    1
    1
    1
    1
    PCI_F1 output control  
    PCI_F0 output control  
    PCI5 output control  
    PCI4 output control  
    PCI3 output control  
    PCI2 output control  
    PCI1 output control  
    PCI0 output control  
    - 6 -  
    W83194BR-372  
    7.4 Register 3: AGP, 24_48MHz, 48MHz, REF Control (1 =Enable, 0 =Stopped)  
    (Default: FFh)  
    BIT  
    7
    6
    5
    4
    3
    2
    1
    0
    PIN NO  
    PWD  
    DESCRIPTION  
    30  
    31  
    26  
    27  
    4
    3
    2
    -
    1
    1
    1
    1
    1
    1
    1
    1
    AGP_1 output control  
    AGP_0 output control  
    24_48MHz output control  
    48MHz output control  
    REF2 output control  
    REF1 output control  
    REF0 output control  
    Reserved  
    7.5 Register 4: IOAPIC, ZCLK Control (1 = Enable, 0 = Stopped) (Default: F0h)  
    BIT  
    7
    6
    5
    4
    3
    2
    1
    PIN NO  
    PWD  
    DESCRIPTION  
    47  
    46  
    10  
    9
    1
    1
    1
    1
    0
    0
    0
    IOAPIC1 output control  
    IOAPIC0 output control  
    ZCLK1 output control  
    ZCLK0 output control  
    Reserved  
    -
    SEL<2>  
    SEL<1>  
    Asynchronous ZCLK/AGP/PCI frequency table selection, SEL<2:0>  
    001: 132 / 66 / 33M  
    011: 132 / 88 / 44M  
    101: 132 / 66 / 33M  
    111: 132 / 88 / 33M  
    010:132 / 75.43 / 37.7M  
    100:176 / 88 / 44M  
    110:132 / 75.43 / 33M  
    000: Clock from PLL1  
    0
    SEL<0>  
    0
    7.6 Register 5: 24_48MHz Control (Default: 88h)  
    BIT  
    7
    6
    5
    4
    3
    2
    1
    0
    NAME  
    PWD  
    DESCRIPTION  
    SEL24_48  
    Reserved  
    Reserved  
    Reserved  
    Reserved  
    Reserved  
    Reserved  
    Reserved  
    1
    0
    0
    0
    1
    0
    0
    0
    24 / 48 MHz output selection, 1: 24 MHz (Default), 0: 48 MHz.  
    Reserved  
    Reserved  
    Reserved  
    Publication Release Date: April 13, 2005  
    Revision 1.1  
    - 7 -  
    W83194BR-372  
    7.7 Register 6: M/N (Default: 90h)  
    Bit  
    7
    6
    Name  
    N<8>  
    M<6>  
    M>5>  
    M<4>  
    M<3>  
    M<2>  
    M<1>  
    M<0>  
    PWD  
    DESCRIPTION  
    1
    0
    0
    1
    0
    0
    0
    0
    Programmable N divisor value. Bit 7 ~0 are defined in the Register 7.  
    5
    4
    3
    Programmable M divisor  
    2
    1
    0
    7.8 Register 7: N (Default: BBh)  
    BIT  
    7
    6
    NAME  
    N<7>  
    N<6>  
    N<5>  
    N<4>  
    N<3>  
    N<2>  
    N<1>  
    N<0>  
    PWD  
    DESCRIPTION  
    1
    0
    1
    1
    1
    0
    1
    1
    5
    4
    Programmable N divisor bit 7 ~0. The bit 8 is defined in Register 6.  
    3
    2
    1
    0
    7.9 Register 8: Winbond Chip ID (Default: 72h) (Read only)  
    BIT  
    7
    6
    5
    4
    NAME  
    PWD  
    DESCRIPTION  
    Winbond Chip ID. W83194BR-372 (SA5872).  
    Winbond Chip ID.  
    Winbond Chip ID.  
    Winbond Chip ID.  
    CHPI_ID [7]  
    CHPI_ID [6]  
    CHPI_ID [5]  
    CHPI_ID [4]  
    CHPI_ID [3]  
    CHPI_ID [2]  
    CHPI_ID [1]  
    CHPI_ID [0]  
    0
    1
    1
    1
    0
    0
    1
    0
    3
    Winbond Chip ID.  
    2
    1
    0
    Winbond Chip ID.  
    Winbond Chip ID.  
    Winbond Chip ID.  
    - 8 -  
    W83194BR-372  
    7.10 Register 9: Reserved (Default: 50h) (Read only)  
    BIT  
    7
    6
    5
    4
    NAME  
    PWD  
    DESCRIPTION  
    Reserved  
    Reserved  
    Reserved  
    Reserved  
    Reserved  
    Reserved  
    Reserved  
    Reserved  
    0
    1
    0
    1
    0
    0
    0
    0
    Reserved  
    Reserved  
    Reserved  
    Reserved  
    3
    2
    1
    0
    7.11 Register 10: M/N Program (Default: 04h)  
    BIT  
    NAME  
    PWD  
    DESCRIPTION  
    0: Output frequency depend on frequency table  
    1: Program all clock frequency by changing M/N value  
    The equation is  
    VCO =14.318MHz*(N+4)/ M.  
    7
    EN_MN_PROG  
    0
    Once the watchdog timer timeout, the bit will be clear. Then the  
    frequency will be decided by hardware default FS<4:0> or desired  
    frequency select SAF_FREQ [4:0] depend on EN_SAFE_FREQ  
    (Reg0 - bit 0).  
    6
    5
    4
    3
    2
    1
    0
    N<9>  
    0
    0
    0
    0
    1
    0
    0
    Programmable N divisor bit 9.  
    Reserved  
    IVAL<3>  
    IVAL<2>  
    IVAL<1>  
    IVAL<0>  
    Reserved  
    Reserved  
    Charge pump current selection  
    Reserved  
    Publication Release Date: April 13, 2005  
    - 9 -  
    Revision 1.1  
    W83194BR-372  
    7.12 Register 11: Spread Spectrum Programming (Default: 0Eh)  
    BIT  
    7
    6
    5
    4
    NAME  
    PWD  
    DESCRIPTION  
    SP_UP [3]  
    SP_UP [2]  
    SP_UP [1]  
    SP_UP [0]  
    SP_DOWN [3]  
    SP_DOWN [2]  
    SP_DOWN [1]  
    SP_DOWN [0]  
    0
    0
    0
    0
    1
    1
    1
    0
    Spread Spectrum Up Counter bit 3 ~ bit 0.  
    3
    2
    Spread Spectrum Down Counter bit 3 ~ bit 0  
    2’s complement representation.  
    Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000  
    1
    0
    7.13 Register 12: Divisor and Step-less Enable Control (Default: 88h)  
    BIT  
    7
    NAME  
    Reserved  
    Reserved  
    Reserved  
    DS4  
    PWD  
    DESCRIPTION  
    1
    0
    0
    0
    1
    0
    0
    0
    Reserved  
    Reserved  
    6
    5
    4
    3
    2
    1
    DS3  
    DS2  
    DS1  
    Defined the CPU, ZCLK, AGP, PCI divider ratio  
    0
    DS0  
    - 10 -  
    W83194BR-372  
    Table-2 CPU, ZCLK, AGP, PCI divider ratio selection Table  
    DS4 DS3 DS2 DS1 DS0 CPU Ratio  
    ZCLK Ratio  
    AGP Ratio  
    PCI Ratio  
    12  
    12  
    12  
    12  
    12  
    12  
    20  
    20  
    12  
    12  
    12  
    12  
    12  
    20  
    20  
    20  
    18  
    18  
    20  
    20  
    20  
    18  
    18  
    20  
    20  
    16  
    18  
    18  
    18  
    20  
    16  
    12  
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    0
    0
    0
    0
    0
    0
    0
    0
    1
    1
    1
    1
    1
    1
    1
    1
    0
    0
    0
    0
    0
    0
    0
    0
    1
    1
    1
    1
    1
    1
    1
    1
    0
    0
    0
    0
    1
    1
    1
    1
    0
    0
    0
    0
    1
    1
    1
    1
    0
    0
    0
    0
    1
    1
    1
    1
    0
    0
    0
    0
    1
    1
    1
    1
    0
    0
    1
    1
    0
    0
    1
    1
    0
    0
    1
    1
    0
    0
    1
    1
    0
    0
    1
    1
    0
    0
    1
    1
    0
    0
    1
    1
    0
    0
    1
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    3
    3
    3
    3
    3
    3
    5
    5
    4
    4
    4
    4
    4
    4
    6
    6
    5
    5
    5
    5
    5
    4
    4
    4
    6
    4
    4
    4
    4
    4
    3
    2
    6
    6
    4
    4
    3
    3
    4
    4
    6
    6
    4
    4
    3
    5
    4
    4
    6
    6
    8
    6
    5
    5
    6
    6
    5
    4
    4
    4
    5
    5
    4
    3
    6
    8
    6
    8
    6
    8
    10  
    12  
    6
    8
    6
    8
    6
    10  
    10  
    12  
    9
    9
    10  
    9
    8
    9
    9
    10  
    10  
    8
    9
    9
    9
    10  
    8
    6
    Publication Release Date: April 13, 2005  
    Revision 1.1  
    - 11 -  
    W83194BR-372  
    7.14 Register 13: FIX Mode Control (Default: 0Fh)  
    BIT  
    NAME  
    PWD  
    DESCRIPTION  
    PCI output frequency select mode  
    (Valid only when SEL<2:0> is nonzero)  
    0: Output frequency according to frequency selection table  
    1: Output frequency according to FIX frequency table  
    ZCLK output frequency select mode  
    7
    FIX_PCI  
    0
    (Valid only when SEL<2:0> is nonzero)  
    0: Output frequency according to frequency selection table  
    1: Output frequency according to FIX frequency table  
    6
    FIX_ZCLK  
    0
    5
    4
    3
    2
    1
    0
    SPCNT [5]  
    SPCNT [4]  
    SPCNT [3]  
    SPCNT [2]  
    SPCNT [1]  
    SPCNT [0]  
    0
    0
    1
    1
    1
    1
    Spread Spectrum Programmable time, the resolution is 280ns. Default  
    period is 11.8us  
    7.15 Register 14: Fix Mode Control (Default: 2Ch)  
    BIT  
    NAME  
    PWD  
    DESCRIPTION  
    AGP output frequency select mode  
    7
    Fix_AGP  
    0
    0: Output frequency according to frequency selection table  
    1: Output frequency according to FIX frequency table  
    Invert the USB48 phase,  
    6
    INV_USB48  
    0
    0: In phase with USB24_48  
    1: 180 degrees out of phase  
    5
    4
    Reserved  
    SPSP1  
    1
    0
    Reserved  
    Spread Spectrum type select.  
    00 : Down  
    1%  
    01 : Down 0.5%  
    10 : Center +/- 0.5%  
    3
    SPSP0  
    1
    11 : Center +/- 0.25%  
    2
    1
    0
    ASKEW [2]  
    ASKEW [1]  
    ASKEW [0]  
    1
    0
    0
    CPU to AGP skew control, Skew resolution is 340ps  
    Expand the skew direction is same as  
    CPU_AGP_SKEW [2:0] setting  
    - 12 -  
    W83194BR-372  
    7.16 Register 15: Skew Control (Default: E4h)  
    BIT  
    7
    6
    5
    4
    NAME  
    CPU1STOP_EN  
    CPU0STOP_EN  
    ZSKEW [2]  
    PWD  
    DESCRIPTION  
    1
    1
    1
    0
    0
    1
    0
    0
    Stop CPU1 clocks, 1: Enable stop feature, 0: Disable  
    Stop CPU0 clocks, 1: Enable stop feature, 0: Disable  
    Reserved CPU to ZCLK skew control, Skew resolution is 340ps  
    Expand the skew direction is same as  
    ZSKEW [1]  
    CPU_ZCLK_SKEW [2:0] setting  
    3
    2
    ZSKEW [0]  
    PSKEW [2]  
    CPU to PCI skew control, Skew resolution is 340ps  
    Expand the skew direction is same as  
    CPU_PCI_SKEW [2:0] setting  
    1
    0
    PSKEW [1]  
    PSKEW [0]  
    Publication Release Date: April 13, 2005  
    - 13 -  
    Revision 1.1  
    W83194BR-372  
    8. ACCESS INTERFACE  
    The W83194BR-372 provides I2C Serial Bus for microprocessor to read/write internal registers. In the  
    W83194BR-372 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C  
    address is defined at 0xD2.  
    Block Read and Block Write Protocol  
    8.1 Block Write Protocol  
    8.2 Block Read Protocol  
    ## In block mode, the command code must filled 8’h00  
    8.3 Byte Write Protocol  
    8.4 Byte Read Protocol  
    - 14 -  
    W83194BR-372  
    9. SPECIFICATIONS  
    9.1 Absolute Maximum Ratings  
    Stresses greater than those listed in this table may cause permanent damage to the device.  
    Precautions should be taken to avoid application of any voltage higher than the maximum rated  
    voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability.  
    Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD).  
    PARAMETER  
    Absolute 3.3V Core Supply Voltage  
    Absolute 3.3V I/O Supple Voltage  
    Operating 3.3V Core Supply Voltage  
    Operating 3.3V I/O Supple Voltage  
    Storage Temperature  
    Ambient Temperature  
    Operating Temperature  
    Input ESD protection (Human body model)  
    RATING  
    -0.5V to +4.6V  
    - 0.5 V to + 4.6 V  
    3.135V to 3.465V  
    3.135V to 3.465V  
    - 65°C to + 150°C  
    - 55°C to + 125°C  
    0°C to + 70°C  
    2000V  
    9.2 General Operating Characteristics  
    VDD48=VDDAGP=VDDREF=VDDPCI= 3.3V ± 5 %, TA = 0°C to +70°C, Cl=10pF  
    PARAMETER  
    Input Low Voltage  
    Input High Voltage  
    Output Low Voltage  
    Output High Voltage  
    SYM.  
    VIL  
    VIH  
    VOL  
    VOH  
    MIN. MAX. UNITS  
    TEST CONDITIONS  
    0.8  
    Vdc  
    Vdc  
    Vdc  
    Vdc  
    2.0  
    2.4  
    0.4  
    All outputs using 3.3V power  
    All outputs using 3.3V power  
    CPU = 100 to 200 MHz  
    Operating Supply Current  
    Idd  
    350  
    mA  
    PCI = 33.3 Mhz with load  
    Input pin capacitance  
    Output pin capacitance  
    Input pin inductance  
    Cin  
    Cout  
    Lin  
    5
    6
    7
    pF  
    pF  
    nH  
    9.3 Skew Group Timing Clock  
    VDD48=VDDAGP=VDDREF=VDDPCI = 3.3V ± 5 %, TA = 0°C to +70°C, Cl=10pF  
    PARAMETER  
    AGP to PCI Skew  
    CPU to CPU Skew  
    AGP to AGP Skew  
    PCI to PCI Skew  
    MIN. TYP.  
    1.5 2.6  
    MAX.  
    3.5  
    UNITS  
    ns  
    ps  
    ps  
    ps  
    TEST CONDITIONS  
    Measured at 1.5V  
    Crossing point  
    Measured at 1.5V  
    Measured at 1.5V  
    Measured at 1.5V  
    Measured at 1.5V  
    200  
    250  
    500  
    1000  
    500  
    48MHz to 48MHz Skew  
    REF to REF Skew  
    ps  
    ps  
    Publication Release Date: April 13, 2005  
    Revision 1.1  
    - 15 -  
    W83194BR-372  
    9.4 CPU (Open Drain) Electrical Characteristics  
    VDDCPU= 2.5V ± 5 %, TA = 0°C to +70°C, external 1.5V pull-up  
    PARAMETER  
    Rise Time  
    Fall Time  
    MIN.  
    -
    -
    MAX.  
    900  
    900  
    UNITS  
    ps  
    ps  
    TEST CONDITIONS  
    100 to 200 Mhz, Vol=20%, Voh=80%  
    100 to 200Mhz, Vol=20%, Voh=80%  
    Absolute crossing point  
    Voltages  
    550  
    1250  
    mV  
    100 to 200Mhz  
    Cycle to Cycle jitter  
    Duty Cycle  
    250  
    55  
    ps  
    %
    100 to 200Mhz  
    100 to 200Mhz  
    45  
    9.5 AGP, ZCLK Electrical Characteristics  
    VDDAGP=VDDZ= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,  
    PARAMETER  
    Rise Time  
    Fall Time  
    Cycle to Cycle jitter  
    Duty Cycle  
    MIN.  
    500  
    500  
    MAX.  
    2000  
    2000  
    250  
    UNITS  
    ps  
    ps  
    ps  
    %
    TEST CONDITIONS  
    Measure from 0.4V to 2.4V  
    Measure from 2.4V to 0.4V  
    Measure 1.5V point  
    45  
    55  
    Pull-Up Current Min  
    Pull-Up Current Max  
    Pull-Down Current Min  
    Pull-Down Current Max  
    -33  
    mA  
    mA  
    mA  
    mA  
    Vout=1.0V  
    Vout=3.135V  
    Vout=1.95V  
    Vout=0.4V  
    -33  
    38  
    30  
    9.6 PCI Electrical Characteristics  
    VDDPCI= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,  
    PARAMETER  
    Rise Time  
    Fall Time  
    Cycle to Cycle jitter  
    Duty Cycle  
    MIN.  
    500  
    500  
    MAX.  
    2000  
    2000  
    250  
    UNITS  
    ps  
    ps  
    ps  
    %
    TEST CONDITIONS  
    Measure from 0.4V to 2.4V  
    Measure from 2.4V to 0.4V  
    Measure 1.5V point  
    45  
    55  
    Pull-Up Current Min  
    Pull-Up Current Max  
    Pull-Down Current Min  
    Pull-Down Current Max  
    -33  
    mA  
    mA  
    mA  
    mA  
    Vout=1.0V  
    Vout=3.135V  
    Vout=1.95V  
    Vout=0.4V  
    -33  
    38  
    30  
    - 16 -  
    W83194BR-372  
    9.7 24M, 48M Electrical Characteristics  
    VDD48= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,  
    PARAMETER  
    Rise Time  
    Fall Time  
    MIN.  
    500  
    500  
    MAX.  
    2000  
    2000  
    500  
    UNITS  
    ps  
    ps  
    TEST CONDITIONS  
    Measure from 0.4V to 2.4V  
    Measure from 2.4V to 0.4V  
    Measure 1.5V point  
    Long term jitter  
    ps  
    Duty Cycle  
    45  
    55  
    %
    Pull-Up Current Min  
    Pull-Up Current Max  
    Pull-Down Current Min  
    Pull-Down Current Max  
    -33  
    mA  
    mA  
    mA  
    mA  
    Vout=1.0V  
    Vout=3.135V  
    Vout=1.95V  
    Vout=0.4V  
    -33  
    38  
    30  
    9.8 REF Electrical Characteristics  
    VDDREF= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,  
    PARAMETER  
    Rise Time  
    Fall Time  
    Cycle to Cycle jitter  
    Duty Cycle  
    MIN.  
    1000  
    1000  
    MAX.  
    4000  
    4000  
    1000  
    55  
    UNITS  
    ps  
    ps  
    ps  
    %
    TEST CONDITIONS  
    Measure from 0.4V to 2.4V  
    Measure from 2.4V to 0.4V  
    Measure 1.5V point  
    45  
    Pull-Up Current Min  
    Pull-Up Current Max  
    Pull-Down Current Min  
    Pull-Down Current Max  
    -33  
    mA  
    mA  
    mA  
    mA  
    Vout=1.0V  
    Vout=3.135V  
    Vout=1.95V  
    Vout=0.4V  
    -33  
    38  
    30  
    9.9 IOAPIC Electrical Characteristics  
    VDDI= 2.5V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,  
    PARAMETER  
    Rise Time  
    Fall Time  
    Cycle to Cycle jitter  
    Duty Cycle  
    MIN.  
    400  
    400  
    MAX.  
    1600  
    1600  
    500  
    UNITS  
    ps  
    ps  
    ps  
    %
    TEST CONDITIONS  
    Measure from 0.4V to 2.0V  
    Measure from 2.0V to 0.4V  
    Measure 1.25V point  
    45  
    55  
    Pull-Up Current Min  
    Pull-Up Current Max  
    Pull-Down Current Min  
    Pull-Down Current Max  
    -27  
    mA  
    mA  
    mA  
    mA  
    Vout=1.0V  
    Vout=2.375V  
    Vout=1.2V  
    Vout=0.3V  
    -27  
    30  
    27  
    Publication Release Date: April 13, 2005  
    Revision 1.1  
    - 17 -  
    W83194BR-372  
    10. ORDERING INFORMATION  
    PART NUMBER  
    PACKAGE TYPE  
    PRODUCTION FLOW  
    W83194BR-372  
    48 PIN SSOP  
    Commercial, 0°C to +70°C  
    11. HOW TO READ THE TOP MARKING  
    W83194BR-372  
    28051234  
    342GBASA  
    1st line: Winbond logo and the type number: W83194BR-372  
    2nd line: Tracking code 2 8051234  
    2: wafers manufactured in Winbond FAB 2  
    8051234: wafer production series lot number  
    3rd line: Tracking code 342 G A A SA  
    342: packages made in '2003, week 42  
    G: assembly house ID; O means OSE, G means GR  
    A: Internal use code  
    A: IC revision  
    SA: mask version  
    All the trademarks of products and companies mentioned in this data sheet belong to their  
    respective owners.  
    - 18 -  
    W83194BR-372  
    12. PACKAGE DRAWING AND DIMENSIONS  
    Publication Release Date: April 13, 2005  
    Revision 1.1  
    - 19 -  
    W83194BR-372  
    13. REVISION HISTORY  
    VERSION  
    DATE  
    PAGE  
    DESCRIPTION  
    All of the versions before 0.50 are for internal  
    use.  
    0.5  
    0.6  
    09/03/03  
    10/01/03  
    n.a.  
    1, 6, 7, 10, 11,  
    12, 16, 17  
    First published preliminary version.  
    Modify some description, red text.  
    Correction IC version, correction some  
    description and default value  
    0.7  
    12/18/03  
    18  
    0.8  
    1.0  
    1.1  
    04/27/04  
    12/28/04  
    4/13/2005  
    5, 11  
    Change frequency table ‘01101’  
    Update on Web  
    Add disclaimer  
    20  
    Important Notice  
    Winbond products are not designed, intended, authorized or warranted for use as components  
    in systems or equipment intended for surgical implantation, atomic energy control  
    instruments, airplane or spaceship instruments, transportation instruments, traffic signal  
    instruments, combustion control instruments, or for other applications intended to support or  
    sustain life. Further more, Winbond products are not intended for applications wherein failure  
    of Winbond products could result or lead to a situation wherein personal injury, death or  
    severe property or environmental damage could occur.  
    Winbond customers using or selling these products for use in such applications do so at their  
    own risk and agree to fully indemnify Winbond for any damages resulting from such improper  
    use or sales.  
    Headquarters  
    Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.  
    27F, 2299 Yan An W. Rd. Shanghai,  
    200336 China  
    No. 4, Creation Rd. III,  
    Science-Based Industrial Park,  
    Hsinchu, Taiwan  
    2727 North First Street, San Jose,  
    CA 95134, U.S.A.  
    TEL: 1-408-9436666  
    TEL: 86-21-62365999  
    FAX: 86-21-62365998  
    TEL: 886-3-5770066  
    FAX: 1-408-5441798  
    FAX: 886-3-5665577  
    http://www.winbond.com.tw/  
    Taipei Office  
    Winbond Electronics Corporation Japan  
    7F Daini-ueno BLDG, 3-7-18  
    Shinyokohama Kohoku-ku,  
    Yokohama, 222-0033  
    Winbond Electronics (H.K.) Ltd.  
    Unit 9-15, 22F, Millennium City,  
    No. 378 Kwun Tong Rd.,  
    Kowloon, Hong Kong  
    9F, No.480, Rueiguang Rd.,  
    Neihu District, Taipei, 114,  
    Taiwan, R.O.C.  
    TEL: 886-2-8177-7168  
    FAX: 886-2-8751-3579  
    TEL: 81-45-4781881  
    TEL: 852-27513100  
    FAX: 81-45-4781800  
    FAX: 852-27552064  
    Please note that all data and specifications are subject to change without notice.  
    All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.  
    - 20 -  
    配单直通车
    W83194BR-372产品参数
    型号:W83194BR-372
    是否Rohs认证： 不符合
    生命周期：Obsolete
    零件包装代码：SSOP
    包装说明：SSOP, SSOP48,.4
    针数：48
    Reach Compliance Code：unknown
    ECCN代码：EAR99
    HTS代码：8542.39.00.01
    风险等级：5.25
    其他特性：ALSO REQUIRES 2.5V SUPPLY
    JESD-30 代码：R-PDSO-G48
    JESD-609代码：e0
    长度：15.88 mm
    端子数量：48
    最高工作温度：70 °C
    最低工作温度：
    最大输出时钟频率：200.01 MHz
    封装主体材料：PLASTIC/EPOXY
    封装代码：SSOP
    封装等效代码：SSOP48,.4
    封装形状：RECTANGULAR
    封装形式：SMALL OUTLINE, SHRINK PITCH
    峰值回流温度（摄氏度）：240
    电源：2.5,3.3 V
    主时钟/晶体标称频率：14.318 MHz
    认证状态：Not Qualified
    座面最大高度：2.79 mm
    子类别：Clock Generators
    最大供电电压：3.465 V
    最小供电电压：3.135 V
    标称供电电压：3.3 V
    表面贴装：YES
    技术：CMOS
    温度等级：COMMERCIAL
    端子面层：TIN LEAD
    端子形式：GULL WING
    端子节距：0.635 mm
    端子位置：DUAL
    处于峰值回流温度下的最长时间：30
    宽度：7.49 mm
    uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFIC
    Base Number Matches：1
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