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产品型号W9812G6GH-6的概述

芯片W9812G6GH-6的概述 W9812G6GH-6是一款由威刚半导体制造的动态随机存取存储器(DRAM),广泛应用于各类电子设备中,如个人电脑、服务器、游戏机以及其他消费类电子产品。该芯片具备高性能和低功耗的特点,适用于嵌入式系统和高带宽需求的应用场景。W9812G6GH-6的命名代表其特定的存储容量、封装类型和技术规格,使其在市场中具有独特的识别性。 芯片W9812G6GH-6的详细参数 W9812G6GH-6内存芯片的基本参数如下: - 存储容量:该芯片的存储容量为1GB(8Gb)。 - 内存类型:DDR2 SDRAM。 - 时钟频率:工作频率可达到400MHz。 - 数据总线宽度:16位。 - 工作电压:2.5V±0.2V。 - 功耗:在工作状态下的功耗相对较低,适合移动设备的需求。 - 封装类型:FBGA(Fine Ball Grid Array)。 - 行/列地址:40...

产品型号W9812G6GH-6的Datasheet PDF文件预览

W9812G6GH  
2M X 4 BANKS X 16 BITS SDRAM  
Table of Contents-  
1. GENERAL DESCRIPTION.............................................................................................................. 3  
2. FEATURES...................................................................................................................................... 3  
3. AVAILABLE PART NUMBER .......................................................................................................... 3  
4. PIN CONFIGURATION.................................................................................................................... 4  
5. PIN DESCRIPTION ......................................................................................................................... 5  
6. BLOCK DIAGRAM........................................................................................................................... 6  
7. FUNCTIONAL DESCRIPTION........................................................................................................ 7  
7.1  
7.2  
7.3  
7.4  
7.5  
7.6  
7.7  
7.8  
Power Up and Initialization ................................................................................................. 7  
Programming Mode Register.............................................................................................. 7  
Bank Activate Command .................................................................................................... 7  
Read and Write Access Modes .......................................................................................... 7  
Burst Read Command ........................................................................................................ 8  
Burst Write Command......................................................................................................... 8  
Read Interrupted by a Read ............................................................................................... 8  
Read Interrupted by a Write................................................................................................ 8  
Write Interrupted by a Write................................................................................................ 8  
Write Interrupted by a Read................................................................................................ 8  
Burst Stop Command.......................................................................................................... 9  
Addressing Sequence of Sequential Mode......................................................................... 9  
Addressing Sequence of Interleave Mode.......................................................................... 9  
Auto-precharge Command................................................................................................ 10  
Precharge Command........................................................................................................ 10  
Self Refresh Command..................................................................................................... 10  
Power Down Mode............................................................................................................ 11  
No Operation Command................................................................................................... 11  
Deselect Command .......................................................................................................... 11  
Clock Suspend Mode........................................................................................................ 11  
7.9  
7.10  
7.11  
7.12  
7.13  
7.14  
7.15  
7.16  
7.17  
7.18  
7.19  
7.20  
8. OPERATION MODE...................................................................................................................... 12  
9. ELECTRICAL CHARACTERISTICS ............................................................................................. 13  
9.1  
9.2  
9.3  
Absolute Maximum Ratings.............................................................................................. 13  
Recommended DC Operating Conditions ........................................................................ 13  
Capacitance...................................................................................................................... 13  
Publication Release Date:Aug. 13, 2007  
- 1 -  
Revision A06  
W9812G6GH  
9.4  
9.5  
DC Characteristics............................................................................................................ 14  
AC Characteristics and Operating Condition.................................................................... 15  
10. TIMING WAVEFORMS.................................................................................................................. 17  
10.1  
10.2  
10.3  
10.4  
Command Input Timing..................................................................................................... 17  
Read Timing...................................................................................................................... 18  
Control Timing of Input/Output Data................................................................................. 19  
Mode Register Set Cycle .................................................................................................. 20  
11. OPERATING TIMING EXAMPLE.................................................................................................. 21  
11.1  
11.2  
11.3  
11.4  
11.5  
11.6  
11.7  
11.8  
11.9  
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3).......................................... 21  
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)............... 22  
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3).......................................... 23  
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)............... 24  
Interleaved Bank Write (Burst Length = 8) ....................................................................... 25  
Interleaved Bank Write (Burst Length = 8, Auto-precharge) ............................................ 26  
Page Mode Read (Burst Length = 4, CAS Latency = 3)................................................... 27  
Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) ....................................... 28  
Auto Precharge Read (Burst Length = 4, CAS Latency = 3)............................................ 29  
11.10 Auto Precharge Write (Burst Length = 4) ......................................................................... 30  
11.11 Auto Refresh Cycle........................................................................................................... 31  
11.12 Self Refresh Cycle ............................................................................................................ 32  
11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)................................. 33  
11.14 Power Down Mode............................................................................................................ 34  
11.15 Auto-precharge Timing (Read Cycle) ............................................................................... 35  
11.16 Auto-precharge Timing (Write Cycle) ............................................................................... 36  
11.17 Timing Chart of Read to Write Cycle ................................................................................ 37  
11.18 Timing Chart of Write to Read Cycle ................................................................................ 37  
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) ............................................... 38  
11.20 Timing Chart of Burst Stop Cycle (Precharge Command)................................................ 38  
11.21 CKE/DQM Input Timing (Write Cycle) .............................................................................. 39  
11.22 CKE/DQM Input Timing (Read Cycle) .............................................................................. 40  
12. PACKAGE SPECIFICATION......................................................................................................... 41  
12.1  
54L TSOP (II)-400 mil....................................................................................................... 41  
13. REVISION HISTORY..................................................................................................................... 42  
Publication Release Date:Aug. 13, 2007  
- 2 -  
Revision A06  
W9812G6GH  
1. GENERAL DESCRIPTION  
W9812G6GH is a high-speed synchronous dynamic random access memory (SDRAM), organized as  
2M words × 4 banks × 16 bits. Using pipelined architecture and 0.11 µm process technology,  
W9812G6GH delivers a data bandwidth of up to 166M words per second (-6). For different application,  
W9812G6GH is sorted into two speed grades: -6/6C/6I, -75. The –6/6C/6I is compliant to the  
166Mhz/CL3 specification, the -75 is compliant to the 133MHz/CL3 specification.  
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be  
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE  
command. Column addresses are automatically generated by the SDRAM internal counter in burst  
operation. Random column read is also possible by providing its address at each clock cycle. The  
multiple bank nature enables interleaving among internal banks to hide the precharging time.  
By having a programmable Mode Register, the system can change burst length, latency cycle,  
interleave or sequential burst to maximize its performance. W9812G6GH is ideal for main memory in  
high performance applications.  
2. FEATURES  
3.3V ± 0.3V Power Supply  
Up to 166 MHz Clock Frequency  
2,097,152 Words × 4 banks × 16 bits organization  
Self Refresh Mode  
CAS Latency: 2and 3  
Burst Length: 1, 2, 4, 8 and full page  
Burst Read, Single Writes Mode  
Byte Data Controlled by DQM  
Auto-precharge and Controlled Precharge  
4K Refresh cycles / 64 mS  
Interface: LVTTL  
Packaged in TSOP II 54 pin, 400 mil - 0.80  
W9812G6GH is using Lead free materials  
RoHS compliant  
3. AVAILABLE PART NUMBER  
MAXIMUM SELF  
OPERATING  
PART NUMBER  
SPEED  
REFRESH CURRENT  
TEMPERATURE  
W9812G6GH-6  
W9812G6GH-6C  
W9812G6GH-6I  
W9812G6GH-75  
166MHz/CL3  
166MHz/CL3  
166MHz/CL3  
133MHz/CL3  
2 mA  
2 mA  
2 mA  
2 mA  
0°C ~ 70°C  
0°C ~ 70°C  
-40°C ~ 85°C  
0°C ~ 70°C  
Publication Release Date:Aug. 13, 2007  
-Revision A06  
- 3  
 
W9812G6GH  
4. PIN CONFIGURATION  
VCC  
VSS  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
1
DQ15  
DQ0  
2
VSSQ  
3
VCCQ  
DQ1  
DQ14  
DQ13  
4
DQ2  
5
VSSQ  
VCCQ  
6
DQ12  
DQ11  
DQ3  
DQ4  
7
8
V
CCQ  
V
SSQ  
9
DQ10  
DQ9  
DQ5  
DQ6  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
V
SSQ  
VCCQ  
DQ8  
VSS  
NC  
DQ7  
VCC  
LDQM  
WE  
UDQM  
CLK  
CKE  
NC  
CAS  
RAS  
CS  
A11  
A9  
BS0  
BS1  
A10/AP  
A0  
A8  
A7  
A6  
A1  
A5  
A2  
A4  
VSS  
A3  
VCC  
Publication Release Date:Aug. 13, 2007  
Revision A06  
- 4 -  
 
W9812G6GH  
5. PIN DESCRIPTION  
PIN NUMBER PIN NAME  
FUNCTION  
DESCRIPTION  
Multiplexed pins for row and column address.  
23 26, 22,  
A0 A11  
29 35  
Address  
Row address: A0 A11. Column address: A0 A8.  
Select bank to activate during row address latch time,  
or bank to read/write during address latch time.  
20, 21  
BS0, BS1  
Bank Select  
2, 4, 5, 7, 8,  
10, 11, 13, 42,  
44, 45, 47, 48,  
50, 51, 53  
Data Input/  
Output  
DQ0 −  
Multiplexed pins for data output and input.  
DQ15  
Disable or enable the command decoder. When  
command decoder is disabled, new command is  
ignored and previous operation continues.  
Command input. When sampled at the rising edge of  
the clock, RAS , CAS and WE define the  
operation to be executed.  
19  
18  
Chip Select  
CS  
Row Address  
Strobe  
RAS  
Column Address  
Strobe  
17  
16  
CAS  
WE  
Referred to RAS  
Referred to RAS  
Write Enable  
The output buffer is placed at Hi-Z (with latency of 2)  
when DQM is sampled high in read cycle. In write  
cycle, sampling DQM high will block the write  
operation with zero latency.  
UDQM/  
LDQM  
Input/Output  
Mask  
39, 15  
System clock used to sample inputs on the rising edge  
of clock.  
38  
37  
CLK  
CKE  
Clock Inputs  
CKE controls the clock activation and deactivation.  
Clock Enable When CKE is low, Power Down mode, Suspend mode  
or Self Refresh mode is entered.  
1, 14, 27  
28, 41, 54  
VCC  
VSS  
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.  
Ground  
Ground for input buffers and logic circuit inside DRAM.  
Power (+3.3V) Separated power from VCC, used for output buffers to  
for I/O Buffer improve noise.  
3, 9, 43, 49  
VCCQ  
Ground for I/O Separated ground from VSS, used for output buffers to  
6, 12, 46, 52  
36, 40  
VSSQ  
NC  
Buffer  
improve noise.  
No Connection No connection  
Publication Release Date:Aug. 13, 2007  
-Revision A06  
- 5  
 
W9812G6GH  
6. BLOCK DIAGRAM  
CLK  
CLOCK  
BUFFER  
CKE  
CS  
CONTROL  
SIGNAL  
GENERATOR  
RAS  
COMMAND  
DECODER  
CAS  
COLUMN DECODER  
COLUMN DECODER  
W E  
R
R
O
W
O
W
D
E
C
O
D
E
R
D
E
C
O
D
E
R
CELL ARRAY  
BANK #0  
CELL ARRAY  
BANK #1  
A10  
MODE  
REGISTER  
A0  
SENSE AMPLIFIER  
SENSE AMPLIFIER  
ADDRESS  
BUFFER  
A9  
DMn  
A11  
BS0  
BS1  
DQ0  
DATA CONTROL  
CIRCUIT  
DQ  
BUFFER  
DQ15  
REFRESH  
COUNTER  
COLUMN  
COUNTER  
UDQM  
LDQM  
COLUMN DECODER  
COLUMN DECODER  
R
R
O
W
O
W
CELL ARRAY  
BANK #3  
CELL ARRAY  
BANK #2  
D
E
C
O
D
E
R
D
E
C
O
D
E
R
SENSE AMPLIFIER  
SENSE AMPLIFIER  
Note: The cell array configuration is 4096 * 512 * 16.  
Publication Release Date:Aug. 13, 2007  
Revision A06  
- 6 -  
 
W9812G6GH  
7. FUNCTIONAL DESCRIPTION  
7.1 Power Up and Initialization  
The default power up state of the mode register is unspecified. The following power up and  
initialization sequence need to be followed to guarantee the device being preconditioned to each user  
specific needs.  
During power up, all VCC and VCCQ pins must be ramp up simultaneously to the specified voltage  
when the input signals are held in the “NOP” state. The power up voltage must not exceed VCC +0.3V  
on any of the input pins or Vcc supplies. After power up, an initial pause of 200 µS is required followed  
by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus  
during power up, it is required that the DQM and CKE pins be held high during the initial pause period.  
Once all banks have been precharged, the Mode Register Set Command must be issued to initialize  
the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after  
programming the Mode Register to ensure proper subsequent operation.  
7.2 Programming Mode Register  
After initial power up, the Mode Register Set Command must be issued for proper device operation.  
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode  
Register Set Command can be issued. The Mode Register Set Command is activated by the low  
signals of RAS, CAS , CS and WE at the positive edge of the clock. The address input data  
during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A  
new command may be issued following the mode register set command once a delay equal to tRSC  
has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.  
7.3 Bank Activate Command  
The Bank Activate command must be applied before any Read or Write operation can be executed.  
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate  
command is applied to when the first read or write operation can begin must not be less than the RAS  
to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank  
Activate command can be issued to the same bank. The minimum time interval between successive  
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).  
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice  
versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is  
specified as tRAS (max).  
7.4 Read and Write Access Modes  
After a bank has been activated , a read or write cycle can be followed. This is accomplished by  
setting RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin  
voltage level defines whether the access cycle is a read operation ( WE high), or a write operation  
( WE low). The address inputs determine the starting column address.  
Reading or writing to a different row within an activated bank requires the bank be precharged and a  
new Bank Activate command be issued. When more than one bank is activated, interleaved bank  
Read or Write operations are possible. By using the programmed burst length and alternating the  
access and precharge operations between multiple banks, seamless data access operation among  
many different pages can be realized. Read or Write Commands can also be issued to the same bank  
or between active banks on every clock cycle.  
Publication Release Date:Aug. 13, 2007  
- 7  
-Revision A06  
 
W9812G6GH  
7.5 Burst Read Command  
The Burst Read command is initiated by applying logic low level to CS and CAS while holding  
RAS and WE high at the rising edge of the clock. The address inputs determine the starting column  
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst  
length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page  
explain the address sequence of interleave mode and sequential mode.  
7.6 Burst Write Command  
The Burst Write command is initiated by applying logic low level to CS , CAS and WE while  
holding RAS high at the rising edge of the clock. The address inputs determine the starting column  
address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle  
that the Write Command is issued. The remaining data inputs must be supplied on each subsequent  
rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes  
will be ignored.  
7.7 Read Interrupted by a Read  
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,  
the remaining addresses are overridden by the new read address with the full burst length. The data  
from the first Read Command continues to appear on the outputs until the CAS Latency from the  
interrupting Read Command the is satisfied.  
7.8 Read Interrupted by a Write  
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output  
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will  
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the  
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM  
masking is no longer needed.  
7.9 Write Interrupted by a Write  
A burst write may be interrupted before completion of the burst by another Write Command. When the  
previous burst is interrupted, the remaining addresses are overridden by the new address and data  
will be written into the device until the programmed burst length is satisfied.  
7.10 Write Interrupted by a Read  
A Read Command will interrupt a burst write operation on the same clock cycle that the Read  
Command is activated. The DQs must be in the high impedance state at least one cycle before the  
new read data appears on the outputs to avoid data contention. When the Read Command is  
activated, any residual data from the burst write cycle will be ignored.  
Publication Release Date:Aug. 13, 2007  
- 8 -  
Revision A06  
 
W9812G6GH  
7.11 Burst Stop Command  
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open  
for future Read or Write Commands to the same page of the active bank, if the burst length is full page.  
Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop  
Command is defined by having RAS and CAS high with CS and WE low at the rising edge of  
the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency  
in a burst read cycle interrupted by Burst Stop.  
7.12 Addressing Sequence of Sequential Mode  
A column access is performed by increasing the address from the column address which is input to  
the device. The disturb address is varied by the Burst Length as shown in Table 2.  
Table 2 Address Sequence of Sequential Mode  
DATA  
Data 0  
Data 1  
Data 2  
Data 3  
Data 4  
Data 5  
Data 6  
Data 7  
ACCESS ADDRESS  
BURST LENGTH  
n
BL = 2 (disturb address is A0)  
No address carry from A0 to A1  
BL = 4 (disturb addresses are A0 and A1)  
No address carry from A1 to A2  
n + 1  
n + 2  
n + 3  
n + 4  
n + 5  
n + 6  
n + 7  
BL = 8 (disturb addresses are A0, A1 and A2)  
No address carry from A2 to A3  
7.13 Addressing Sequence of Interleave Mode  
A column access is started in the input column address and is performed by inverting the address bit  
in the sequence shown in Table 3.  
Table 3 Address Sequence of Interleave Mode  
DATA  
Data 0  
Data 1  
ACCESS ADDRESS  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
BURST LENGTH  
BL = 2  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
Data 2  
Data 3  
Data 4  
Data 5  
Data 6  
Data 7  
BL = 4  
BL = 8  
Publication Release Date:Aug. 13, 2007  
-Revision A06  
- 9  
 
W9812G6GH  
7.14 Auto-precharge Command  
If A10 is set to high when the Read or Write Command is issued, then the Auto-precharge function is  
entered. During Auto-precharge, a Read Command will execute as normal with the exception that the  
active bank will begin to precharge automatically before all burst read cycles have been completed.  
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled  
burst cycle. The number of clocks is determined by CAS Latency.  
A Read or Write Command with Auto-precharge can not be interrupted before the entire burst  
operation is completed. Therefore, use of a Read, Write or Precharge Command is prohibited during a  
read or write cycle with Auto-precharge. Once the precharge operation has started, the bank cannot  
be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-precharge command is  
illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write  
with Auto-precharge function is initiated. The SDRAM automatically enters the precharge operation  
two clocks delay from the last burst write cycle. This delay is referred to as Write tWR. The bank  
undergoing Auto-precharge can not be reactivated until tWR and tRP are satisfied. This is referred to as  
t
DAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto-precharge Command, the interval  
between the Bank Activate Command and the beginning of the internal precharge operation must  
satisfy tRAS (min).  
7.15 Precharge Command  
The Precharge Command is used to precharge or close a bank that has been activated. The  
Precharge Command is entered when CS, RAS and WE are low and CAS is high at the rising  
edge of the clock. The Precharge Command can be used to precharge each bank separately or all  
banks simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to  
be precharged when the command is issued. After the Precharge Command is issued, the precharged  
bank must be reactivated before a new read or write access can be executed. The delay between the  
Precharge Command and the Activate Command must be greater than or equal to the Precharge time  
(tRP).  
7.16 Self Refresh Command  
The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE  
high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.  
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.  
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are  
disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will  
exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the  
device exits Self Refresh Operation and before the next command can be issued. This delay is equal  
to the tAC cycle time plus the Self Refresh exit time.  
If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly  
distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and  
just after exiting the self refresh mode. The period between the Auto Refresh command and the next  
command is specified by tRC.  
Publication Release Date:Aug. 13, 2007  
- 10 -  
Revision A06  
 
W9812G6GH  
7.17 Power Down Mode  
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are  
gated off to reduce the power. The Power Down mode does not perform any refresh operations,  
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the  
device.  
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation  
Command is required on the next rising clock edge, depending on tCK. The input buffers need to be  
enabled with CKE held high for a period equal to tCKS (min) + tCK (min).  
7.18 No Operation Command  
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to  
prevent the SDRAM from registering any unwanted commands between operations. A No Operation  
Command is registered when CS is low with RAS, CAS , and WE held high at the rising edge of  
the clock. A No Operation Command will not terminate a previous operation that is still executing, such  
as a burst read or write cycle.  
7.19 Deselect Command  
The Deselect Command performs the same function as a No Operation Command. Deselect  
Command occurs when CS is brought high, the RAS, CAS , and WE signals become don’t cares.  
7.20 Clock Suspend Mode  
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low  
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode  
deactivates the internal clock and suspends any clocked operation that was currently being executed.  
There is a one clock delay between the registration of CKE low and the time at which the SDRAM  
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are  
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay  
from when CKE returns high to when Clock Suspend mode is exited.  
Publication Release Date:Aug. 13, 2007  
- 11  
-Revision A06  
 
W9812G6GH  
8. OPERATION MODE  
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.  
Table 1 shows the truth table for the operation commands.  
Table 1 Truth Table (Note (1), (2))  
DEVICE  
A0A9  
COMMAND  
CKEn-1 CKEn DQM BS0, 1 A10  
CS RAS CAS  
WE  
STATE  
A11  
Bank Active  
Idle  
Any  
H
H
H
H
x
x
x
x
x
x
x
x
v
v
x
v
v
L
v
x
x
v
L
L
L
L
L
L
H
H
H
L
H
L
L
L
Bank Precharge  
Precharge All  
Write  
Any  
H
L
L
Active (3)  
H
Write with Auto-precharge  
Active (3)  
H
x
x
v
H
v
L
H
L
L
Read  
Active (3)  
Active (3)  
Idle  
H
H
H
H
H
H
H
H
L
x
x
x
x
x
x
x
x
x
x
x
v
v
v
x
x
x
x
x
x
L
H
v
x
x
x
x
x
x
v
v
v
x
x
x
x
x
x
L
L
L
L
L
H
L
L
H
H
H
L
L
L
L
H
H
x
H
H
L
Read with Auto-precharge  
Mode Register Set  
No – Operation  
Burst Stop  
x
Any  
x
H
H
x
H
L
Active (4)  
Any  
x
Device Deselect  
Auto - Refresh  
Self - Refresh Entry  
x
x
Idle  
H
L
H
L
L
L
x
H
H
x
Idle  
L
idle  
x
Self Refresh Exit  
(S.R.)  
Active  
L
H
H
L
x
x
x
x
x
x
x
x
L
x
H
x
H
x
x
x
Clock suspend Mode Entry  
Power Down Mode Entry  
Idle  
H
H
L
L
x
x
x
x
x
x
x
x
H
L
x
x
x
x
Active (5)  
H
H
Clock Suspend Mode Exit  
Power Down Mode Exit  
Active  
L
H
x
x
x
x
x
x
x
x
Any  
L
L
H
H
x
x
x
x
x
x
x
x
H
L
x
x
x
x
(power down)  
H
H
Data write/Output Enable  
Data Write/Output Disable  
Active  
Active  
H
H
x
x
L
x
x
x
x
x
x
x
x
x
x
x
x
x
x
H
Notes:  
(1) v = valid  
x = Don’t care  
L = Low Level H = High Level  
(2) CKEn signal is input level when commands are provided.  
CKEn-1 signal is the input level one clock cycle before the command is issued.  
(3) These are state of bank designated by BS0, BS1 signals.  
(4) Device state is full page burst operation.  
(5) Power Down Mode can not be entered in the burst cycle.  
When this command asserts in the burst cycle, device state is clock suspend mode.  
Publication Release Date:Aug. 13, 2007  
Revision A06  
- 12 -  
 
W9812G6GH  
9. ELECTRICAL CHARACTERISTICS  
9.1 Absolute Maximum Ratings  
PARAMETER  
Input/Output Voltage  
Power Supply Voltage  
SYMBOL  
VIN, VOUT  
VCC, VCCQ  
TOPR  
RATING  
UNIT  
V
V
-0.3 ~ VCC + 0.3  
-0.3 ~ 4.6  
0 ~ 70  
Operating Temperature(-6/6C/-75)  
Operating Temperature(-6I)  
Storage Temperature  
°C  
°C  
°C  
°C  
W
TOPR  
-40 ~ 85  
-55 ~ 150  
260  
TSTG  
Soldering Temperature (10s)  
Power Dissipation  
TSOLDER  
PD  
1
Short Circuit Output Current  
IOUT  
50  
mA  
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability  
of the device.  
9.2 Recommended DC Operating Conditions  
(Ta = 0 to 70°C for -6/-6C/-75 , Ta= -40 to 85°C for -6I )  
PARAMETER  
Power Supply Voltage  
SYMBOL  
MIN.  
TYP.  
MAX.  
UNIT  
VCC  
VCCQ  
VIH  
3.0  
3.0  
2.0  
-0.3  
3.3  
3.3  
-
3.6  
3.6  
VCC + 0.3  
0.8  
V
V
V
V
Power Supply Voltage (for I/O Buffer)  
Input High Voltage  
Input Low Voltage  
VIL  
-
Note: VIH(max) = VCC/ VCCQ+1.2V for pulse width < 5 nS  
VIL(min) = VSS/ VSSQ-1.2V for pulse width < 5 nS  
9.3 Capacitance  
(VCC = 3.3V, f = 1 MHz, Ta 25°C)  
PARAMETER  
SYMBOL  
MIN.  
MAX.  
UNIT  
Input Capacitance  
(A0 to A11, BS0, BS1, CS, RAS , CAS , WE , DQM,  
CKE)  
CI  
-
3.8  
pf  
Input Capacitance (CLK)  
Input/Output capacitance  
CCLK  
CIO  
-
-
3.5  
6.5  
pf  
pf  
Note: These parameters are periodically sampled and not 100% tested.  
Publication Release Date:Aug. 13, 2007  
-Revision A06  
- 13  
 
W9812G6GH  
9.4 DC Characteristics  
(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C for -6/-6C/-75, Ta= -40 to 85°C for -6I)  
-6/-6C/-6I  
MAX.  
-75  
MAX.  
PARAMETER  
SYM.  
UNIT  
NOTES  
Operating Current  
tCK = min., tRC = min.  
1 bank operation  
CKE = VIH  
ICC1  
100  
85  
3
Active precharge command  
cycling without burst operation  
Standby Current  
ICC2  
30  
2
30  
2
3
3
tCK = min, CS = VIH  
VIH/L = VIH(min)/VIL(max.)  
Bank: Inactive state  
CKE = VIL (Power  
Down mode)  
ICC2P  
Standby Current  
CKE = VIH  
ICC2S  
15  
15  
CLK = VIL, CS = VIH  
VIH/L = VIH(min)/VIL(max)  
BANK: Inactive state  
CKE = VIL (Power  
down mode)  
ICC2PS  
2
2
mA  
No Operating Current  
tCK = min., CS = VIH(min)  
CKE = VIH  
ICC3  
65  
15  
60  
15  
BANK: Active state  
CKE = VIL (Power  
down mode)  
ICC3P  
(4 banks)  
Burst Operating Current  
ICC4  
120  
200  
2
100  
190  
2
3, 4  
3
tCK = min.  
Read/ Write command cycling  
Auto Refresh Current  
ICC5  
ICC6  
tCK = min.  
Auto refresh command cycling  
Self Refresh Current  
Self Refresh Mode  
CKE = 0.2V  
PARAMETER  
SYMBOL  
MIN.  
MAX.  
UNIT  
NOTES  
Input Leakage Current  
(0V VIN VCC, all other pins not under test = 0V)  
Output Leakage Current  
II(L)  
-5  
5
µA  
IO(L)  
VOH  
VOL  
-5  
2.4  
-
5
-
µA  
V
(Output disable , 0V VOUT VCCQ)  
LVTTL Output H Level Voltage  
(IOUT = -2 Ma )  
LVTTL Output L Level Voltage  
(IOUT = 2 Ma )  
0.4  
V
Publication Release Date:Aug. 13, 2007  
Revision A06  
- 14 -  
 
W9812G6GH  
9.5 AC Characteristics and Operating Condition  
(Vcc = 3.3V ± 0.3V, Ta = 0 to 70°C for -6/-6C/-75, Ta= -40 to 85°C for -6I, Notes: 5,6,7,8,9,10)  
-6/-6I  
6C  
-75  
PARAMETER  
SYM.  
UNIT  
NOTES  
MIN. MAX. MIN.  
MAX. MIN. MAX.  
Ref/Active to Ref/Active Command Period  
Active to precharge Command Period  
60  
60  
65  
tRC  
tRAS  
42 100000 42 100000 45 100000 nS  
Active to Read/Write Command Delay  
18  
1
18  
1
20  
1
tRCD  
tCCD  
Time  
Read/Write(a) to Read/Write(b) Command  
Period  
tCK  
Precharge to Active Command Period  
Active(a) to Active(b) Command Period  
18  
12  
2
2
10  
6
18  
12  
--  
2
--  
6
20  
15  
2
2
tRP  
tRRD  
nS  
CL* = 2  
CL* = 3  
Write Recovery Time  
tCK  
tWR  
tCK  
CL* = 2  
1000  
10 1000  
7.5  
CLK Cycle Time  
CL* = 3  
9
9
CLK High Level width  
CLK Low Level width  
Access Time from  
CLK  
tCH  
tCL  
2
2
2
2
2.5  
2.5  
CL* = 2  
CL* = 3  
6
5
--  
5
6
nS  
10  
tAC  
5.4  
3
3
0
0
Output Data Hold Time  
3
3
0
0
3
3
0
0
10  
8
10  
tOH  
tHZ  
tLZ  
Output Data High Impedance Time  
Output Data Low Impedance Time  
Power Down Mode Entry Time  
6
6
7.5  
6
1
6
1
7.5  
1
tSB  
Transition Time of CLK  
0.5  
0.5  
0.5  
7
tT  
(Rise and Fall)  
Data-in Set-up Time  
Data-in Hold Time  
Address Set-up Time  
Address Hold Time  
CKE Set-up Time  
1.5  
1.0  
1.5  
1.0  
1.5  
1.0  
1.5  
1.0  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
1.0  
1.5  
1.0  
1.5  
1.0  
1.5  
1.0  
9
9
9
9
9
9
9
9
tDS  
tDH  
tAS  
tAH  
tCKS  
tCKH  
tCMS  
tCMH  
tREF  
tRSC  
tXSR  
CKE Hold Time  
Command Set-up Time  
Command Hold Time  
Refresh Time  
Mode register Set Cycle Time  
Exit self refresh to ACTIVE command  
64  
64  
64  
mS  
nS  
nS  
12  
72  
12  
72  
15  
75  
*CL = CAS Latency  
* -- = not support  
Publication Release Date:Aug. 13, 2007  
-Revision A06  
- 15  
 
W9812G6GH  
Notes:  
1. Operation exceeds “Absolute Maximum Ratings” may cause permanent damage to the devices.  
2. All voltages are referenced to VSS  
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the  
minimum values of tCK and tRC.  
4. These parameters depend on the output loading conditions. Specified values are obtained with  
output open.  
5. Power up sequence is further described in the “Functional Description” section.  
6. AC Testing Conditions  
PARAMETER  
CONDITIONS  
1.4V  
Output Reference Level  
Output Load  
Input Signal Levels (VIH/VIL)  
Transition Time (tT: tr/tf) of Input Signal  
Input Reference Level  
See diagram below  
2.4V/0.4V  
1/1 nS  
1.4V  
1.4 V  
50 ohms  
30pF  
output  
Z = 50 ohms  
ACTEST LOAD  
7. Transition times are measured between VIH and VIL.  
8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to  
output level.  
9. Assumed input rise and fall time (tT ) = 1nS.  
If tr & tf is longer than 1nS, transient time compensation should be considered,  
i.e., [(tr + tf)/2-1]nS should be added to the parameter  
( The tT maximum can’t be more than 10nS for low frequency application. )  
10. If clock rising time (tT) is longer than 1nS, (tT/2-0.5)nS should be added to the parameter.  
Publication Release Date:Aug. 13, 2007  
- 16 -  
Revision A06  
W9812G6GH  
10. TIMING WAVEFORMS  
10.1 Command Input Timing  
t
CL  
tCH  
t
CK  
V
V
IH  
IL  
CLK  
CS  
t
T
tT  
t
CMS  
tCMH  
t
CMH  
tCMS  
t
CMS  
t
CMH  
RAS  
t
t
CMS  
CMS  
t
t
CMH  
CMH  
CAS  
WE  
tAS  
tAH  
A0-A11  
BS0, 1  
t
CKS  
t
CKH  
t
CKH  
t
CKS  
t
CKS  
t
CKH  
CKE  
Publication Release Date:Aug. 13, 2007  
-Revision A06  
- 17  
 
W9812G6GH  
10.2 Read Timing  
Read CAS Latency  
CLK  
CS  
RAS  
CAS  
WE  
A0-A11  
BS0, 1  
t
AC  
t
AC  
t
HZ  
t
OH  
t
OH  
t
LZ  
Valid  
Valid  
Data-Out  
Data-Out  
DQ  
Read Command  
Burst Length  
Publication Release Date:Aug. 13, 2007  
Revision A06  
- 18 -  
 
W9812G6GH  
10.3 Control Timing of Input/Output Data  
Control Timing of Input Data  
(Word Mask)  
CLK  
t
CMS  
tCMH  
t
CMH  
tCMS  
DQM  
t
DS  
t
DH  
t
DS  
t
DH  
t
DS  
t
DH  
t
DS  
tDH  
Valid  
Data-in  
Valid  
Valid  
Valid  
Data-in  
Data-in  
Data-in  
DQ0 -15  
(Clock Mask)  
CLK  
t
CKH  
t
CKS  
t
CKH  
tCKS  
CKE  
t
DS  
t
DH  
t
DS  
t
DH  
t
DS  
t
DH  
t
DS  
tDH  
Valid  
Valid  
Data-in  
Valid  
Valid  
DQ0 -15  
Data-in  
Data-in  
Data-in  
Control Timing of Output Data  
(Output Enable)  
CLK  
t
CMH  
t
CMS  
tCMS  
t
CMH  
DQM  
t
AC  
t
HZ  
tAC  
t
AC  
t
AC  
t
LZ  
t
OH  
t
OH  
t
OH  
t
OH  
Valid  
Data-Out  
Valid  
Valid  
Data-Out  
Data-Out  
OPEN  
DQ0 -15  
(Clock Mask)  
CLK  
t
CKH  
t
CKS  
t
CKH  
tCKS  
CKE  
t
AC  
t
AC  
tAC  
tAC  
t
OH  
t
OH  
t
OH  
tOH  
Valid  
Valid  
Data-Out  
Valid  
Data-Out  
DQ0 -15  
Data-Out  
Publication Release Date:Aug. 13, 2007  
-Revision A06  
- 19  
 
W9812G6GH  
10.4 Mode Register Set Cycle  
t
RSC  
CLK  
t
CMS  
tCMH  
CS  
t
CMS  
tCMH  
RAS  
CAS  
WE  
t
t
CMS  
CMS  
t
t
CMH  
CMH  
t
AS  
tAH  
Register  
set data  
A0-A11  
BS0,1  
next  
command  
Burst  
Length  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A2  
0
A
1
A0  
0
Sequ  
e
ntial  
Interleave  
Burst Length  
Addressing Mode  
CAS Latency  
0
0
1
1
0
0
1
1
0
1
2
2
0
0
4
4
0
1
A80  
A80  
1
0
1
0
1
Reserved  
Full age  
Address  
Reserved  
1
1
0
0
1
A
1
0
1
AP0  
A3  
0
A10  
in  
g Mode  
Sequential  
Interleave  
A
"0" (Test Mode)  
A
0
A8  
"0"  
Reserved  
Write ode  
A6  
0
A
5
A4  
0
CAS Latency  
0
Reserved  
A
9
M
0
0
1
Res rved  
e
0
1
0
2
A10  
"0"  
"0"  
"0"  
"0"  
0
1
1
3
A11  
1
A
0
0
0
Reserved  
BS0  
BS1  
Reserved  
A
9
Single Write Mode  
0
A10  
Burst read andBurst write  
Burst read anAd0single write  
Publication Release Date:Aug. 13, 2007  
Revision A06  
- 20 -  
 
W9812G6GH  
11. OPERATING TIMING EXAMPLE  
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)  
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
1
2
3
4
5
0
CLK  
CS  
t
RC  
tRC  
t
RC  
tRC  
RAS  
CAS  
t
RAS  
t
RP  
t
RAS  
RP  
tRP  
t
RAS  
t
tRAS  
WE  
BS0  
BS1  
t
RCD  
t
RCD  
t
RCD  
t
RCD  
RAa  
RAa  
RBb  
RAc  
RAc  
RBd  
RBd  
A10  
RAe  
RAe  
A0-A9,  
A11  
CBx  
RBb  
CAy  
CAw  
CBz  
DQM  
CKE  
DQ  
t
AC  
t
AC  
t
AC  
t
AC  
bx3  
bx1  
aw0  
aw2  
aw3  
bx0  
bx2  
cy0 cy1  
cy2 cy3  
aw1  
t
RRD  
t
RRD  
tRRD  
t
RRD  
Precharge  
Read  
Active  
Read  
Precharge  
Active  
Bank #0  
Bank #1  
Bank #2  
Read  
Active  
Precharge  
Read  
Active  
Active  
Idle  
Bank #3  
Publication Release Date:Aug. 13, 2007  
-Revision A06  
- 21  
 
W9812G6GH  
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)  
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
1
2
3
4
5
0
CLK  
CS  
t
RC  
tRC  
t
RC  
t
RC  
RAS  
CAS  
t
RAS  
t
RP  
t
RAS  
t
t
RP  
RAS  
t
RAS  
RP  
t
WE  
BS0  
BS1  
t
RCD  
t
RCD  
t
RCD  
t
RCD  
RAe  
RBd  
RAa  
RBb  
RAc  
A10  
A0-A9,  
A11  
CBz  
RAa  
CAw  
CAy  
RAe  
CBx  
RBb  
RAc  
RBd  
DQM  
CKE  
t
AC  
t
AC  
t
AC  
t
AC  
aw0 aw1 aw2  
aw3  
bx0 bx1  
bx2 bx3  
cy0  
cy1 cy2  
cy3  
dz0  
DQ  
t
RRD  
t
RRD  
t
RRD  
tRRD  
Read  
AP*  
Active  
AP*  
Read  
Active  
Active  
Active  
AP*  
Bank #0  
Bank #1  
Bank #2  
Bank #3  
Read  
Read  
Active  
Idle  
* AP is the internal precharge start timing  
Publication Release Date:Aug. 13, 2007  
Revision A06  
- 22 -  
 
W9812G6GH  
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)  
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23  
1
2
3
4
5
0
CLK  
CS  
t
RC  
tRC  
t
RC  
RAS  
t
RAS  
t
RP  
tRAS  
t
RP  
t
RAS  
tRP  
CAS  
WE  
BS0  
BS1  
t
RCD  
t
RCD  
tRCD  
RAa  
RAa  
RAc  
RAc  
A10  
RBb  
RBb  
A0-A9,  
A11  
CAx  
CBy  
CAz  
DQM  
CKE  
t
AC  
t
AC  
t
AC  
ax0 ax1  
ax2  
ax3  
ax4  
ax5 ax6  
by0  
by1  
by4 by5  
by6  
by7  
DQ  
CZ0  
t
RRD  
t
RRD  
Read  
Active  
Idle  
Precharge  
Active  
Read  
Precharge  
Bank #0  
Bank #1  
Bank #2  
Bank #3  
Active  
Precharge  
Read  
Publication Release Date:Aug. 13, 2007  
-Revision A06  
- 23  
 
W9812G6GH  
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)  
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20  
1
2
3
4
5
21 22 23  
0
CLK  
CS  
t
RC  
RAS  
t
RAS  
t
RAS  
t
RP  
t
RAS  
t
RP  
CAS  
WE  
BS0  
BS1  
t
RCD  
tRCD  
t
RCD  
A10  
RBb  
RBb  
RAc  
RAa  
RAa  
CAz  
CAx  
RAc  
CBy  
A0-A9,  
A11  
DQM  
CKE  
DQ  
t
CAC  
t
CAC  
t
CAC  
ax3  
ax4  
ax0  
ax2  
ax5 ax6  
ax7  
by0  
by1  
by4  
by5  
by6  
ax1  
CZ0  
t
RRD  
t
RRD  
AP*  
Read  
Active  
Bank #0 Active  
Bank #1  
Read  
Active  
Read  
AP*  
Bank #2  
Idle  
* AP is the internal precharge start timing  
Bank #3  
Publication Release Date:Aug. 13, 2007  
Revision A06  
- 24 -  
 
W9812G6GH  
11.5 Interleaved Bank Write (Burst Length = 8)  
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23  
1
2
3
4
5
0
CLK  
CS  
t
RC  
RAS  
CAS  
t
RAS  
t
RAS  
t
RP  
tRP  
t
RAS  
tRCD  
t
RCD  
t
RCD  
WE  
BS0  
BS1  
RBb  
RAc  
RAc  
RAa  
RAa  
A10  
A0-A9,  
A11  
CAx  
RBb  
CBy  
CAz  
DQM  
CKE  
DQ  
ax0 ax1  
RRD  
ax4  
ax5  
ax6 ax7 by0  
by1 by2  
RRD  
by3  
by4  
by5  
by6  
by7  
CZ0  
CZ1  
CZ2  
t
t
Active  
Write  
Precharge  
Active  
Write  
Bank #0  
Active  
Write  
Precharge  
Bank #1  
Bank #2  
Bank #3  
Idle  
Publication Release Date:Aug. 13, 2007  
-Revision A06  
- 25  
 
W9812G6GH  
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge)  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23  
CLK  
CS  
t
RC  
RAS  
CAS  
t
RP  
t
RAS  
t
RAS  
WE  
BS0  
BS1  
t
RCD  
tRCD  
t
RCD  
RAa  
RAa  
RBb  
RBb  
RAb  
RAc  
A10  
A0-A9  
A11  
CAx  
CBy  
CAz  
DQM  
CKE  
DQ  
ax4  
by2  
by5  
ax0 ax1  
ax5  
ax6 ax7  
by0 by1  
by3  
by4  
by6  
by7 CZ0  
CZ1  
CZ2  
tRRD  
t
RRD  
Write  
Active  
AP*  
Active  
Write  
Bank #0  
Bank #1  
Bank #2  
Bank #3  
AP*  
Write  
Active  
Idle  
* AP is the internal precharge start timing  
Publication Release Date:Aug. 13, 2007  
Revision A06  
- 26 -  
 
W9812G6GH  
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23  
CLK  
CS  
t
CCD  
t
CCD  
tCCD  
t
RAS  
tRP  
t
RAS  
tRP  
RAS  
CAS  
WE  
BS0  
BS1  
t
RCD  
tRCD  
RAa  
RAa  
RBb  
RBb  
A10  
A0-A9,  
A11  
CBx  
CAy  
CAm  
CBz  
CAI  
DQM  
CKE  
t
AC  
t
AC  
t
AC  
t
AC  
tAC  
am1  
am2 bz0  
bz1  
bz2  
bz3  
a0  
a1  
a3  
bx0  
Ay0  
Ay1 Ay2 am0  
a2  
bx1  
DQ  
t
RRD  
Read  
Bank #0 Active  
Bank #1  
Read  
Read  
Precharge  
AP*  
Active  
Read  
Read  
Bank #2  
Idle  
Bank #3  
* AP is the internal precharge start timing  
Publication Release Date:Aug. 13, 2007  
-Revision A06  
- 27  
 
W9812G6GH  
11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)  
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
1
2
3
4
5
0
CLK  
CS  
t
RAS  
tRP  
RAS  
CAS  
WE  
BS0  
BS1  
t
RCD  
RAa  
RAa  
A10  
A0-A9,  
A11  
CAx  
CAy  
DQM  
CKE  
t
AC  
t
WR  
ax5  
ay1  
ax0  
ax1  
ax3  
ay0  
ay2  
ay4  
ax2  
ax4  
ay3  
DQ  
Q
Q
Q
Q
Q
Q
D
D
D
D
D
Bank #0  
Bank #1  
Bank #2  
Bank #3  
Active  
Idle  
Read  
Write  
Precharge  
Publication Release Date:Aug. 13, 2007  
Revision A06  
- 28 -  
 
W9812G6GH  
11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3)  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
CLK  
CS  
t
RC  
tRC  
RAS  
t
RAS  
t
RP  
t
RAS  
tRP  
CAS  
WE  
BS0  
BS1  
A10  
t
RCD  
tRCD  
RAa  
RAb  
A0-A9,  
A11  
CAx  
RAa  
CAw  
RAb  
DQM  
CKE  
DQ  
t
AC  
t
AC  
aw0 aw1 aw2 aw3  
bx0  
bx1  
bx2 bx3  
Bank #0  
AP*  
Active  
Idle  
Read  
Active  
Read  
AP*  
Bank #1  
Bank #2  
Bank #3  
* AP is the internal precharge start timing  
Publication Release Date:Aug. 13, 2007  
-Revision A06  
- 29  
 
W9812G6GH  
11.10 Auto Precharge Write (Burst Length = 4)  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
CLK  
CS  
t
RC  
t
RC  
RAS  
CAS  
t
RAS  
t
RP  
t
RAS  
tRP  
WE  
BS0  
BS1  
t
RCD  
t
RCD  
RAc  
RAa  
RAa  
RAb  
A10  
A0-A9,  
A11  
CAw  
RAb  
CAx  
RAc  
DQM  
CKE  
DQ  
bx0  
aw1 aw2  
bx1  
bx3  
bx2  
aw0  
aw3  
Active  
Idle  
AP*  
Bank #0  
Write  
Active  
Write  
Active  
AP*  
Bank #1  
Bank #2  
Bank #3  
* AP is the internal precharge start timing  
Publication Release Date:Aug. 13, 2007  
Revision A06  
- 30 -  
 
W9812G6GH  
11.11 Auto Refresh Cycle  
(CLK = 100 MHz)  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14  
15 16 17 18 19  
20 21 22 23  
CLK  
CS  
t
RP  
t
RC  
tRC  
RAS  
CAS  
WE  
BS0,1  
A10  
A0-A9,  
A11  
DQM  
CKE  
DQ  
All Banks  
Prechage  
Auto  
Auto Refresh (Arbitrary Cycle)  
Refresh  
Publication Release Date:Aug. 13, 2007  
-Revision A06  
- 31  
 
W9812G6GH  
11.12 Self Refresh Cycle  
(CLK = 100 MHz)  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
CLK  
CS  
tRP  
RAS  
CAS  
WE  
BS0,1  
A10  
A0-A9,  
A11  
DQM  
tCKS  
tCKS  
tSB  
CKE  
DQ  
tCKS  
tXSR  
Self Refresh Cycle  
No Operation / Command Inhibit  
Self Refresh  
Exit  
All Banks  
Self Refresh  
Entry  
Arbitrary Cycle  
Precharge  
Publication Release Date:Aug. 13, 2007  
Revision A06  
- 32 -  
 
W9812G6GH  
11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23  
CLK  
CS  
RAS  
CAS  
t
RCD  
WE  
BS0  
BS1  
A10  
RBa  
A0-A9,  
A11  
CBz  
RBa  
CBv  
CBw  
CBx CBy  
DQM  
CKE  
t
AC  
tAC  
DQ  
av0  
av1  
av3  
aw0  
ax0  
ay0  
az1  
az2  
az3  
az0  
av2  
Q
Q
Q
Q
D
D
D
Q
Q
Q
Q
Read  
Active  
Single Write  
Read  
Bank #0  
Bank #1  
Bank #2  
Bank #3  
Idle  
Publication Release Date:Aug. 13, 2007  
-Revision A06  
- 33  
 
W9812G6GH  
11.14 Power Down Mode  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
CLK  
CS  
RAS  
CAS  
WE  
BS  
RAa  
RAa  
RAa  
RAa  
A10  
A0-A9  
A11  
CAa  
CAx  
DQM  
tSB  
tSB  
CKE  
DQ  
tCKS  
tCKS  
tCKS  
tCKS  
ax0  
ax2  
ax3  
ax1  
Active  
NOP Read  
Precharge  
NOP Active  
Precharge Standby  
Power Down mode  
Active Standby  
Power Down mode  
Note: The PowerDown Mode is entered by asserting CKE "low".  
All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode.  
When CKE goes high, command input must be No operation at next CLK rising edge.  
Violating refresh requirements during power-down may result in a loss of data.  
Publication Release Date:Aug. 13, 2007  
Revision A06  
- 34 -  
 
W9812G6GH  
11.15 Auto-precharge Timing (Read Cycle)  
0
1
2
3
4
5
6
7
8
9
10  
11  
(1) CAS Latency=2  
( a ) burst length = 1  
Command  
Read AP  
Read  
Act  
t
RP  
DQ  
Q0  
( b ) burst length = 2  
Command  
AP  
Q0  
Act  
t
RP  
DQ  
Q1  
( c ) burst length = 4  
Command  
Read  
AP  
Q2  
Act  
Q4  
t
RP  
DQ  
Q0  
Q0  
Q1  
Q1  
Q3  
( d ) burst length = 8  
Command  
Read  
AP  
Q6  
Act  
t
RP  
DQ  
Q2  
Act  
Q3  
Act  
Q5  
Q7  
(2) CAS Latency=3  
( a ) burst length = 1  
Command  
Read AP  
Read  
t
RP  
DQ  
Q0  
Q0  
Q0  
Q0  
( b ) burst length = 2  
AP  
Command  
t
RP  
DQ  
Q1  
AP  
Q1  
( c ) burst length = 4  
Command  
Read  
Act  
Q4  
t
RP  
DQ  
Q2  
Q2  
Q3  
Q3  
( d ) burst length = 8  
Command  
Read  
AP  
Q5  
Act  
t
RP  
DQ  
Q1  
Q6  
Q7  
Note )  
Read  
represents the Read with Auto precharge command.  
represents the start of internal precharging.  
represents the Bank Activate command.  
AP  
Act  
When the Auto precharge command is asserted, the period from Bank Activate command to  
the start of internal precgarging must be at least tRAS(min).  
Publication Release Date:Aug. 13, 2007  
-Revision A06  
- 35  
 
W9812G6GH  
11.16 Auto-precharge Timing (Write Cycle)  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
CLK  
(1) CAS Latency = 2  
(a) burst length = 1  
Command  
Write  
D0  
AP  
Act  
tRP  
tWR  
DQ  
(b) burst length = 2  
Command  
Write  
D0  
AP  
Act  
AP  
tRP  
tWR  
DQ  
D1  
D1  
(c) burst length = 4  
Command  
Act  
D7  
Write  
D0  
tRP  
tWR  
DQ  
D2  
D3  
D3  
(d) burst length = 8  
Command  
Write  
D0  
AP  
Act  
tRP  
tWR  
DQ  
D1  
D2  
AP  
D4  
D5  
D6  
(2) CAS Latency = 3  
(a) burst length = 1  
Write  
D0  
Act  
Command  
tRP  
tWR  
DQ  
(b) burst length = 2  
Command  
Write  
D0  
AP  
Act  
tRP  
tWR  
DQ  
D1  
D1  
D1  
(c) burst length = 4  
Command  
Write  
D0  
AP  
D5  
Act  
tRP  
tWR  
DQ  
D2  
D2  
D3  
D3  
(d) burst length = 8  
Command  
Act  
Write  
D0  
AP  
tWR  
tRP  
DQ  
D4  
D6  
D7  
Note )  
represents the Write with Auto precharge command.  
represents the start of internal precharing.  
represents the Bank Active command.  
Write  
AP  
Act  
When the /auto precharge command is asserted,the period from Bank Activate  
command to the start of intermal precgarging must be at least tRAS (min).  
Publication Release Date:Aug. 13, 2007  
Revision A06  
- 36 -  
 
W9812G6GH  
11.17 Timing Chart of Read to Write Cycle  
In the case of Burst Length = 4  
1
2
3
4
5
6
7
8
9
10  
11  
0
(1) CAS Latency=2  
( a ) Command  
Read Write  
DQM  
DQ  
D0  
D1  
D2  
D1  
D3  
D2  
( b ) Command  
Read  
Write  
DQM  
DQ  
D0  
D3  
D3  
(2) CAS Latency=3  
( a ) Command  
DQM  
Read Write  
DQ  
D0  
D1  
Write  
D2  
D1  
D3  
D2  
( b ) Command  
Read  
DQM  
DQ  
D0  
Note: The Output data must be masked by DQM to avoid I/O conflict  
11.18 Timing Chart of Write to Read Cycle  
In the case of Burst Length=4  
1
2
3
4
5
6
7
8
9
10  
11  
0
(1) CAS Latency=2  
Write Read  
( a ) Command  
DQM  
DQ  
D0  
Q0  
Q1  
Q0  
Q2  
Q1  
Q3  
Q2  
( b ) Command  
DQM  
Read  
Write  
DQ  
D0  
D1  
Q3  
(2) CAS Latency=3  
( a ) Command  
DQM  
Write Read  
DQ  
D0  
Write  
Q0  
Q1  
Q0  
Q2  
Q1  
Q3  
Q2  
( b ) Command  
DQM  
Read  
DQ  
D0  
D1  
Q3  
Publication Release Date:Aug. 13, 2007  
-Revision A06  
- 37  
 
W9812G6GH  
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)  
0
1
2
3
4
5
6
7
8
9
10  
11  
(1) Read cycle  
( a ) CAS latency =2  
Command Read  
BST  
Q3  
DQ  
Q0  
Q1  
Q0  
Q2  
Q1  
Q4  
Q3  
( b )CAS latency = 3  
Command  
Read  
BST  
Q2  
DQ  
Q4  
(2) Write cycle  
Command  
DQ  
Write  
Q0  
BST  
Q1  
Q2  
Q3  
Q4  
Note: BST  
represents the Burst stop command  
11.20 Timing Chart of Burst Stop Cycle (Precharge Command)  
0
1
2
3
4
5
6
7
8
9
10  
11  
(1) Read cycle  
(a) CAS latency =2  
Read  
Read  
PRCG  
Q3  
Command  
DQ  
Q0  
Q1  
Q0  
Q2  
Q1  
Q4  
Q3  
(b) CAS latency =3  
PRCG  
Q2  
Command  
DQ  
Q4  
(2) Write cycle  
(a) CAS latency =2  
PRCG  
PRCG  
Write  
Command  
tWR  
tWR  
DQM  
DQ  
Q0  
Q1  
Q1  
Q2  
Q2  
Q3  
Q4  
(b) CAS latency =3  
Write  
Command  
DQM  
DQ  
Q0  
Q3  
Q4  
Publication Release Date:Aug. 13, 2007  
Revision A06  
- 38 -  
 
W9812G6GH  
11.21 CKE/DQM Input Timing (Write Cycle)  
1
CLK cycle No.  
2
3
4
5
7
6
External  
CLK  
Internal  
CKE  
DQM  
DQ  
D1  
1
D2  
2
D3  
3
D5  
5
D6  
DQM MASK  
CKE MASK  
( 1 )  
CLK cycle No.  
External  
4
7
6
CLK  
Internal  
CKE  
DQM  
DQ  
D1  
1
D2  
D3  
D5  
D6  
DQM MASK  
( 2 )  
CKE MASK  
2
3
4
5
6
7
CLK cycle No.  
External  
CLK  
Internal  
CKE  
DQM  
DQ  
D1  
D2  
D3  
D4  
D5  
D6  
CKE MASK  
( 3 )  
Publication Release Date:Aug. 13, 2007  
-Revision A06  
- 39  
 
W9812G6GH  
11.22 CKE/DQM Input Timing (Read Cycle)  
1
CLK cycle No.  
2
3
4
5
6
7
External  
CLK  
Internal  
CKE  
DQM  
DQ  
Q6  
7
Q1  
1
Q2  
2
Q3  
3
Q4  
Open  
Open  
( 1 )  
4
5
CLK cycle No.  
External  
6
CLK  
Internal  
CKE  
DQM  
DQ  
Q3  
Q4  
Q6  
7
Q1  
1
Q2  
Open  
( 2 )  
CLK cycle No.  
2
3
4
5
6
External  
CLK  
Internal  
CKE  
DQM  
DQ  
Q6  
Q3  
Q1  
Q5  
Q4  
Q2  
( 3 )  
Publication Release Date:Aug. 13, 2007  
Revision A06  
- 40 -  
 
W9812G6GH  
12. PACKAGE SPECIFICATION  
12.1 54L TSOP (II)-400 mil  
54  
28  
HE  
E
1
27  
e
b
C
D
L
A2  
A1  
A
L1  
ZD  
Y
SEATING PLANE  
Controlling Dimension: Millimeters  
DIMENSION  
DIMENSION  
(INCH)  
(MM)  
SYM.  
MIN.  
MAX.  
MIN.  
NOM.  
MAX.  
NOM.  
1.20  
0.15  
0.047  
0.006  
A
A1  
0.10  
0.05  
0.24  
0.002  
0.009  
0.004  
0.039  
1.00  
0.32  
0.15  
A2  
b
c
0.40  
0.016  
0.012  
0.006  
D
E
22.12  
10.06  
11.56  
22.62  
10.26  
11.96  
0.871  
0.396  
0.455  
0.875  
0.400  
0.905  
0.404  
0.471  
22.22  
10.16  
11.76  
0.80  
0.50  
0.80  
HE  
e
L
0.463  
0.0315  
0.020  
0.60  
0.10  
0.40  
0.016  
0.024  
0.004  
0.032  
L1  
Y
0.71  
0.028  
ZD  
Publication Release Date:Aug. 13, 2007  
-Revision A06  
- 41  
 
W9812G6GH  
13. REVISION HISTORY  
VERSION  
DATE  
PAGE  
DESCRIPTION  
Create new datasheet  
A01  
Mar. 24, 2006  
All  
A02  
A03  
Sep. 08, 2006  
Mar. 27, 2006  
10  
Exit Auto refresh to next command is specified by tRC  
Modify Characteristics Notes 9 and add Notes 10 (tT)  
15,16  
3,13,14,15 Add -6C grade for tIHmin=0.8nS  
15,32,34 Add tXSR timing specification  
A04  
Feb. 07, 2007  
A05  
A06  
Apr. 09, 2007 3,13,14,15 Add -6I grade for Ta= -40 to 85°C  
Revise transient time tT AC test condition and calculate  
Aug. 13, 2007  
16  
formula for compensation consideration in Notes 6, 9 of  
AC Characteristics and Operating Condition  
Important Notice  
Winbond products are not designed, intended, authorized or warranted for use as components  
in systems or equipment intended for surgical implantation, atomic energy control  
instruments, airplane or spaceship instruments, transportation instruments, traffic signal  
instruments, combustion control instruments, or for other applications intended to support or  
sustain life. Further more, Winbond products are not intended for applications wherein failure  
of Winbond products could result or lead to a situation wherein personal injury, death or  
severe property or environmental damage could occur.  
Winbond customers using or selling these products for use in such applications do so at their  
own risk and agree to fully indemnify Winbond for any damages resulting from such improper  
use or sales.  
Publication Release Date:Aug. 13, 2007  
- 42 -  
Revision A06  
 
配单直通车
W9812G6GH-6产品参数
型号:W9812G6GH-6
是否Rohs认证: 符合
生命周期:Obsolete
IHS 制造商:WINBOND ELECTRONICS CORP
零件包装代码:TSOP2
包装说明:0.400 INCH, 0.80 INCH PITCH, ROHS COMPLIANT, TSOP2-54
针数:54
Reach Compliance Code:unknown
ECCN代码:EAR99
HTS代码:8542.32.00.02
风险等级:5.64
访问模式:FOUR BANK PAGE BURST
最长访问时间:5 ns
其他特性:AUTO/SELF REFRESH
JESD-30 代码:R-PDSO-G54
长度:22.22 mm
内存密度:134217728 bit
内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16
功能数量:1
端口数量:1
端子数量:54
字数:8388608 words
字数代码:8000000
工作模式:SYNCHRONOUS
最高工作温度:70 °C
最低工作温度:
组织:8MX16
封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE
认证状态:Not Qualified
座面最大高度:1.2 mm
自我刷新:YES
最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V
表面贴装:YES
技术:CMOS
温度等级:COMMERCIAL
端子形式:GULL WING
端子节距:0.8 mm
端子位置:DUAL
宽度:10.16 mm
Base Number Matches:1
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