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产品型号X4C105V的概述

芯片X4C105V的概述 X4C105V是一款集成电路芯片，该芯片设计用于多种电子应用，因其灵活性和高效能而受到广泛关注。该芯片主要以低功耗、高速度的特性著称，非常适合在嵌入式系统、通信设备以及消费电子产品中使用。X4C105V的应用领域十分广泛，从智能家居设备到工业自动化都能找到它的身影。该芯片的设计考虑了用户对于性能、成本及能耗的平衡，提供了多种接口和丰富的功能配置，用户可以根据需求灵活选择。这使得X4C105V成为市场上非常有竞争力的选择。通过针对不同应用场景的性能优化，几乎所有对性能有要求的电子设备都能从中受益。芯片X4C105V的详细参数 X4C105V芯片的技术参数包括但不限于以下几个方面： 1. 工作电压：2.7V 到 5.5V，适合于多种电源环境。 2. 工作温度范围：-40°C 到 +85°C，适用于苛刻环境。 3. 处理速度：最高可达 100 MHz，支持高频率...

产品型号X4C105V20的Datasheet PDF文件预览

DATASHEET

X4C105

FN8124

Rev 2.00

July 3, 2008

4k, NOVRAM/EEPROM CPU Supervisor with NOVRAM and Output Ports

The low voltage X4C105 combines several functions into

one device. The first is a 2-wire, 4k-bit serial EEPROM

memory with write protection. A Write Protect (WP) pin

provides hardware protection for the upper half of this

memory against inadvertent writes.

Features

• 4k-bit serial EEPROM

- 400kHz serial interface speed

- 16-byte page write mode

• One nibble NOVRAM

A one nibble NOVRAM is provided and occupies a single

location. This allows access of 4-bits in a single 150ns cycle.

This is useful for tracking system operation or process

status. The NOVRAM memory is completely isolated from

the serial memory section.

- 120ns NOVRAM access speed

- AUTOSTORE

- Direct/bus access of NOVRAM bits

• Four output ports

A low voltage detect circuit activates a RESET pin when V_CC

drops below 3V. This signal also blocks new read or write

operations and initiates a NOVRAM AUTOSTORE. The

AUTOSTORE operation is powered by an external capacitor

to ensure that the value in the NOVRAM is always

maintained in the event of a power failure.

• Operates at 3.3V ± 10%

• Low voltage reset when V_CC< 3V

- 3% accurate thresholds available

- Output signal shows low voltage condition

- Activates NOVRAM AUTOSTORE

- Internal block on EEPROM operation

The four NOVRAM bits also appear on four separate output

pins to allow continuous control of external circuitry, such as

ASICs.

• Max EEPROM/NOVRAM nonvolatile write cycle: 5ms

• High reliability

Intersil EEPROMs are designed and tested for applications

requiring extended endurance. Inherent data retention is

greater than 100 years.

- 1,000,000 endurance cycles

- Guaranteed data retention: 100 years

- 20 Ld TSSOP package

Ordering Information

PART

NUMBER

PART

MARKING

V_CCLIMITS

(V)

V_TRIP

(V)

TEMP RANGE

(°C)

PACKAGE

20 Ld TSSOP

X4C105V20

X4C105V

X4C105V I

3.3V ±10%

2.8 to 2.95

0 to +70

X4C105V20I

-40 to +85

FN8124 Rev 2.00

July 3, 2008

Page 1 of 15

X4C105

Block Diagram

WRITE CONTROL LOGIC

HV GENERATION

TIMING AND CONTROL

EEPROM

MEMORY

OUTPUT

BUFFERS

AND

LATCHES

STATIC RAM

MEMORY

SCL

COMMAND

4k-BITS

SDA

DECODE

EEPROM

ARRAY

I/O

BUFFERS

AND

CONTROL

LOGIC

CONTROL

LOGIC AND

TIMING

Y DECODER

DATA REGISTER

CAP

LOW VOLTAGE DETECT

POWER-ON RESET

VOLTAGE

MONITOR

SUPPLY

RESET

Pinout

Device Description

X4C105

(20 LD TSSOP)

TOP VIEW

Serial Memory Section

The device contains a 4k-bit EEPROM memory array with an

internal address counter that allows it to be read sequentially,

through its entire address space after receiving only 1 full

address. The serial interface includes a current address read

that requires no input address, but allows reading of the entire

array starting from the address plus one of the last read or

write. The address counter is also used for the write operation

where the user may enter up to a page of data (16 bytes) after

supplying only 1 full address.

CAP

SCL

17 SDA

15 D1

RESET

A WP pin provides hardware write protection. The WP pin

active (HIGH) prevents writes to the top half of the memory.

11 O1

This section is a 4k-bit version of an industry standard 24C04

device.

Pin Descriptions

NOVRAM Section

DESCRIPTION

The X4C105 also contains a single nibble of NOVRAM, with

parallel access. This memory is completely isolated from the

serial memory section. The NOVRAM is intended to connect to

the system memory bus and uses standard CE, OE, and WE

pins to control access.

V_SS

SDA

Ground

Serial Data

Power

V_CC

SCL

Serial Clock

Write Protect

A NOVRAM (or nonvolatile RAM) consists of an SRAM part

and an EEPROM part. The SRAM is saved to EEPROM only

when power fails and the EEPROM is recalled to SRAM only

on power-up.

S1, S2

CAP

Device Select Inputs

External AUTOSTORE Capacitor

NOVRAM I/Os

Output Ports

D0, D1, D2, D3

RESET

The X4C105 has four output only ports. These are active

whenever power is applied to the device. The state of the output

pin reflects the value in the respective SRAM bit. As such, these

port pins provide a nonvolatile state. The conditions on the pins

are restored when power is re-applied to the device. This can be

valuable as a DIP switch replacement for controlling the

conditions of an ASIC or other system logic.

Low Voltage Detect Output

NOVRAM Chip Enable

NOVRAM Read Signal

NOVRAM Write signal

NOVRAM Outputs

O0, O1, O2, O3

FN8124 Rev 2.00

July 3, 2008

Page 2 of 15

X4C105

Low Voltage Detection

Serial Interface

When the internal low voltage detect circuitry senses that

Serial Interface Conventions

V_CCis low, several things happen:

The device supports a bidirectional bus oriented protocol.

The protocol defines any device that sends data onto the

bus as a transmitter, and the receiving device as the

receiver. The device controlling the transfer is called the

master and the device being controlled is called the slave.

The master always initiates data transfers, and provides the

clock for both transmit and receive operations. Therefore,

the devices in this family operate as slaves in all

applications.

• The RESET pin goes active.

• The contents of the SRAM are automatically saved to the

“shadow” EEPROM.

• Internal circuitry switches to provide power for the

AUTOSTORE operation from the CAP pin so the store

operation can complete even in the event of a catastrophic

power failure. To insure this, it is recommended that a

47µF capacitor be used on the CAP pin. The capacitor is

continuously charged during normal operation to provide

the necessary charge to complete the store operation.

Other internal circuits are turned off to minimize current

consumption during the store operations.

Serial Clock and Data

Data states on the SDA line can change only during SCL

LOW. SDA state changes during SCL HIGH are reserved for

indicating start and stop conditions. See Figure 2.

• Communication to the device is interrupted and any

command is aborted. If a serial nonvolatile store is in

progress when power fails, the operation is completed and

is followed by a NOVRAM AUTOSTORE cycle.

Serial Start Condition

All commands are preceded by the start condition, which is a

HIGH to LOW transition of SDA when SCL is HIGH. The

device continuously monitors the SDA and SCL lines for the

start condition and will not respond to any command until

this condition has been met. See Figure 3.

Capacitor Backup Circuit

The diagram in Figure 1 shows a representation of the

capacitor backup circuit.

TO INTERNAL

VOLTAGE SUPPLY

TRIP

HIGH WHEN

> V

TRIP

LOW WHEN

< V - 0.2V

TRIP

START

NOVRAM

AUTOSTORE

CAP

FIGURE 1. CAPACITOR BACK-UP CIRCUIT

SCL

SDA

DATA STABLE

DATA CHANGE

DATA STABLE

FIGURE 2. VALID DATA CHANGES ON THE SDA BUS

FN8124 Rev 2.00

July 3, 2008

Page 3 of 15

X4C105

In the read mode, the device will transmit eight bits of data,

release the SDA line, then monitor the line for an acknowledge.

If an acknowledge is detected and no stop condition is

generated by the master, the device will continue to transmit

data. The device will terminate further data transmissions if an

acknowledge is not detected. The master must then issue a

stop condition to return the device to standby mode and place

the device into a known state.

Serial Stop Condition

All communications must be terminated by a stop condition,

which is a LOW to HIGH transition of SDA when SCL is HIGH.

The stop condition is also used to place the device into the

standby power mode after a read sequence. A stop condition

can only be issued after the transmitting device has released

the bus. See Figure 2.

Serial Acknowledge

Serial Write Operations

Acknowledge is a software convention used to indicate

successful data transfer. The transmitting device, either master

or slave, will release the bus after transmitting eight bits. During

the ninth clock cycle, the receiver will pull the SDA line LOW to

acknowledge that it received the eight bits of data. Refer to

Figure 4.

Byte Write

For a write operation, the device requires the slave address byte

and a word address byte. This gives the master access to any

one of the words in the array. After receipt of the word address

byte, the device responds with an acknowledge, and awaits the

next eight bits of data. After receiving the 8 bits of the data byte,

the device again responds with an acknowledge. The master then

terminates the transfer by generating a stop condition, at which

time the device begins the internal write cycle to the nonvolatile

memory. During this internal write cycle, the device inputs are

disabled, so the device will not respond to any requests from the

master. The SDA output is at high impedance. See Figure 5.

The device will respond with an acknowledge after recognition

of a start condition and if the correct device identifier and select

bits are contained in the slave address byte. If a write operation

is selected, the device will respond with an acknowledge after

the receipt of each subsequent eight bit word. The device will

acknowledge all incoming data and address bytes, except for

the slave address byte when the device identifier and/or select

bits are incorrect or when the device is busy, such as during a

nonvolatile write.

An attempted write to a protected block of memory will

suppress the acknowledge bit and the operation will terminate.

SCL

SDA

START

STOP

FIGURE 3. VALID START AND STOP CONDITIONS

SCL

FROM

MASTER

DATA OUTPUT

FROM

TRANSMITTER

DATA OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVE

FN8124 Rev 2.00

July 3, 2008

Page 4 of 15

X4C105

The master terminates the data byte loading by issuing a stop

condition, which causes the device to begin the nonvolatile

write cycle. As with the byte write operation, all inputs are

disabled until completion of the internal write cycle. Refer to

Figure 7 for the address, acknowledge, and data transfer

sequence.

Page Write

The device is capable of a page write operation. It is initiated in

the same manner as the byte write operation; but instead of

terminating the write cycle after the first data byte is

transferred, the master can transmit an unlimited number of 8-

bit bytes. After the receipt of each byte, the device will respond

with an acknowledge, and the address is internally

Stops and Write Modes

incremented by one. The page address remains constant.

When the counter reaches the end of the page, it “rolls over”

and goes back to ‘0’ on the same page. This means that the

master can write 16 bytes to the page starting at any location

on that page. If the master begins writing at location 10, and

loads 12 bytes, then the first 5 bytes are written to locations 10

through 15, and the last 7 bytes are written to locations 0

through 6. Afterwards, the address counter would point to

location 7 of the page that was just written. See Figure 6. If the

master supplies more than 16 bytes of data, then new data

over-writes the previous data, one byte at a time.

Stop conditions that terminate write operations must be sent by

the master after sending at least 1 full data byte plus the

subsequent ACK signal. If a stop is issued in the middle of a

data byte, or before 1 full data byte plus its associated ACK is

sent, then the device will reset itself without performing the

write. The contents of the array will not be affected.

SIGNALS

FROM THE

BYTE

SLAVE

ADDRESS

DATA

MASTER

SDA BUS

SIGNALS

FROM THE

SLAVE

FIGURE 5. BYTE WRITE SEQUENCE

7 BYTES

5 BYTES

ADDRESS POINTER

ADDRESS

n - 1

ADDRESS = 6

ENDS HERE

ADDR = 7

FIGURE 6. WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 10

(1 < n < 16)

SIGNALS

FROM THE

MASTER

BYTE

ADDRESS

SLAVE

ADDRESS

DATA

(1)

DATA

(n)

SDA BUS

SIGNALS

FROM THE

SLAVE

FIGURE 7. PAGE WRITE OPERATION

FN8124 Rev 2.00

July 3, 2008

Page 5 of 15

X4C105

Serial Read Operations

BYTE LOAD

COMPLETED BY

ISSUING STOP

Read operations are initiated in the same manner as write

operations with the exception that the R/W bit of the slave

address byte is set to one. There are three basic read

operations: current address read, random read, and sequential

read.

ISSUE START

Current Address Read

ISSUE SLAVE

ADDRESS BYTE

ISSUE STOP

Internally the device contains an address counter that

maintains the address of the last word read incremented by

one. Therefore, if the last read was to address n, the next read

operation would access data from address n+1. On power-up,

the address of the address counter is undefined, requiring a

read or write operation for initialization.

ACK

RETURNED?

YES

Upon receipt of the slave address byte with the R/W bit set to

one, the device issues an acknowledge and then transmits the

eight bits of the data byte. The master terminates the read

operation when it does not respond with an acknowledge during

the ninth clock and then issues a stop condition. Refer to Figure

9 for the address, acknowledge, and data transfer sequence.

HIGH VOLTAGE

CYCLE COMPLETE.

CONTINUE

ISSUE STOP

COMMAND

YES

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read operation,

the master must either issue a stop condition during the ninth

cycle or hold SDA HIGH during the ninth clock cycle and then

issue a stop condition.

CONTINUE NORMAL

READ OR WRITE

COMMAND

PROCEED

Random Read

FIGURE 8. ACKNOWLEDGE POLLING SEQUENCE

A random read operation allows the master to access any

memory location in the array. Prior to issuing the slave address

byte with the R/W bit set to one, the master must first perform a

“dummy” write operation. The master issues the start condition

and the slave address byte, receives an acknowledge, then

issues the word address byte. After acknowledging receipts of

the word address byte, the master immediately issues another

start condition and the slave address byte with the R/W bit set

to one. This is followed by an acknowledge from the device

and then by the eight bit word. The master terminates the read

operation by not responding with an acknowledge and then

issuing a stop condition. Refer to Figure 10 for the address,

acknowledge and data transfer sequence.

Acknowledge Polling

The disabling of the inputs during high voltage cycles can be

used to take advantage of the typical 5ms write cycle time.

Once the stop condition is issued to indicate the end of the

master’s byte load operation, the device initiates the internal

non volatile write cycle. Acknowledge polling can be initiated

immediately. To do this, the master issues a start condition

followed by the slave address byte for a write or read

operation. If the device is still busy with the high voltage cycle

then no ACK will be returned. If the device has completed the

write operation, an ACK will be returned and the host can then

proceed with the read or write operation. Refer to the flow chart

in Figure 8.

The device offers a similar operation, called “Set Current

Address,” where the device ends the transmission and issues a

stop instead of the second start, shown in Figure 10. The device

SLAVE

ADDRESS

SIGNALS

FROM THE

MASTER

SDA BUS

SIGNALS

FROM THE

SLAVE

DATA

FIGURE 9. CURRENT ADDRESS READ SEQUENCE

FN8124 Rev 2.00

July 3, 2008

Page 6 of 15

X4C105

goes into standby mode after the stop and all bus activity will be

ignored until a start is detected. This operation loads the new

address into the address counter. The next current address read

operation will then read from the newly loaded address. This

operation could be useful if the master knows the next address it

needs to read, but is not ready for the data.

• a device type identifier that is always ‘1010’.

• two bits that provide the device select bits.

• one bit that becomes the MSB of the address.

• one bit of the slave command byte is a R/W bit. The R/W bit

of the slave address byte defines the operation to be

performed. When the R/W bit is a one, then a read operation

is selected. A zero selects a write operation. Refer to Figure

11.

Sequential Read

Sequential reads can be initiated as either a current address

read or random address read. The first data byte is transmitted

as with the other modes; however, the master now responds

with an acknowledge, indicating it requires additional data. The

device continues to output data for each acknowledge received.

The master terminates the read operation by not responding

with an acknowledge and then issuing a stop condition.

After loading the entire slave address byte from the SDA bus,

the device compares the device select bits with the status of

the device select pins. Upon a correct compare, the device

outputs an acknowledge on the SDA line.

Slave Byte

The data output is sequential, with the data from address n

followed by the data from address n + 1. The address counter

for read operations increments through all page and column

addresses, allowing the entire memory contents to be serially

read during one operation. At the end of the address space the

R/W

Word Address

The word address is either supplied by the master or obtained

from an internal counter. The internal counter is undefined on a

power-up condition.

counter “rolls over” to address 0000 and the device continues

to output data for each acknowledge received. Refer to Figure

11 for the acknowledge and data transfer sequence.

Write Protect Operations

The WP pin provides write protection. The WP pin protects the

upper half of the array.

Serial Device Addressing

Slave Address Byte

TABLE 1. WRITE PROTECTED AREAS

Following a start condition, the master must output a slave

address byte. This byte consists of several parts:

WP PIN

SERIAL MEMORY WRITE PROTECTION

LOW Writes possible to all locations

HIGH No writes to 100H-1FFH, writes possible to 000H to 0FFH

SIGNALS

FROM THE

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS

SLAVE

ADDRESS

SDA BUS

SIGNALS

FROM THE

SLAVE

DATA

FIGURE 10. RANDOM ADDRESS READ SEQUENCE

SIGNALS

FROM THE

MASTER

SLAVE

ADDRESS

SDA BUS

SIGNALS

FROM THE

SLAVE

DATA

(2)

DATA

(n - 1)

DATA

(1)

DATA

(n)

(“n” IS ANY INTEGER GREATER THAN 1)

FIGURE 11. SEQUENTIAL READ SEQUENCE

FN8124 Rev 2.00

July 3, 2008

Page 7 of 15

X4C105

Absolute Maximum Ratings

Thermal Information

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on any Pin with Respect to GND . . . . . . . . . . -1.0V to 7.0V

DC Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA

Thermal Resistance (Typical, Note 1)



_JA(°C/W)

110

20 Lead TSSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . .

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTE:

1. _JAis measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Specifications V_CC= 3.0V to 3.6V at -40°C to +85°C, unless otherwise specified. Parameters with MIN and/or MAX limits are

100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are

not production tested.

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

_CC1(Note 2) Active Supply Current Serial

V_IL= V_CCx 0.1, V_IH= V_CCx 0.9, f_SCL= 400kHz, SDA = Read/Write

2.0

Read or Serial Write (Does Not Operation, CE, OE, WE, D0 - D3 = V_IH; O0 - O3, RESET = Open

Include the Nonvolatile Store

Operation)

CAP is tied to V_CC; V_CC> V_TRIP

_CC2(Note 2) Average Active Supply Current V_IL= V_CCx 0.1, V_IH= V_CCx 0.9, SCL, SDA = V_IH; WP, S1, S2 = V_IL,

During Serial Nonvolatile Store CE, OE, WE, D0 - D3 = V_IH; O0 - O3, RESET = Open CAP is tied to

3.0

µA

Operation

V_CC. Test during the N.V. write cycle.

_CC3(Note 2) Active Supply Current Volatile

NOVRAM Read

V_IL= V_CCx 0.1, V_IH= V_CCx 0.9, SCL, SDA = V_IH; WP, S1, S2 = V_IL,

WE = V_IH; CE, OE = V_IL, D0 - D3, O0 - O3, RESET = Open CAP is

tied to V_CC; V_CC> V_TRIP

I_CC4(Note 2) Active Supply Current Volatile

NOVRAM Write

V_IL= V_CCx 0.1, V_IH= V_CCx 0.9, SCL, SDA = V_IH; WP, S1, S2 =V_IL,

OE = V_IH; CE, WE = V_IL,D0-D3 = V_ILor V_IH, O0 - O3, RESET = Open

CAP is tied to V_CC; V_CC> V_TRIP

_CC5(Note 2) Average Active Supply Current

V_IL= V_CCx 0.1, V_IH= V_CCx 0.9, SCL, SDA, V_IH; WP, S1, S2 = V_IL,

Over NOVRAM Store or Active WE, CE, OE = V_IH; D0 - D3, O0 - O3, RESET = Open CAP is tied

Current During Recall

to V_CC,V_CC< V_TRIPfor Store; V_CC> V_TRIPfor Recall

_SB1(Note 2) Standby Current

V_IL= V_CCx 0.1, V_IH= V_CCx 0.9, SCL, SDA, CE, WE, OE, D0 - D3,

= V_IH, WP = V_IL, O0 - O3,RESET = Open; CAP is tied to V_CC

I_LI

Input Leakage Current

Output Leakage Current

V_IN= GND to V_CC

µA

I_LO

V_SDA= GND to V_CC;Device is in Standby (Note 3)

V_IL(Note 4) Input LOW voltage

_IH(Note 4) Input HIGH voltage

-0.5

V_CCx 0.3

V_CCx 0.7 V_CC+ 0.5

0.05 x V_CC

0.4

V_HYS

V_OL

Schmitt Trigger Input Hysteresis

Output LOW Voltage

Output HIGH Voltage

I_OL= 2.0mA, V_CC= 3.3V

I_OH= -1mA, V_CC= 3.3V

V_OH

V_CC- 0.4

NOTES:

2. The device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave address byte

are incorrect; 200ns after a stop ending a read operation; or t_WCafter a stop ending a write operation.

3. The device goes into standby: 200ns after any stop, except those that initiate a high voltage write cycle; t_WCafter a stop that initiates a high voltage

cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte.

4. V_ILmin and V_IHmax are for reference only and are not tested.

Capacitance T_A= +25°C, f = 1.0 MHz, V_CC= 3.0V to 3.6V.

SYMBOL

C_I/O

PARAMETER

Input/Output Capacitance (SDA, D0 - D3, O0 - O3)

Input Capacitance (SCL, WP, CE, WE, OE, S1, S2)

TEST CONDITIONS

V_I/O= 0V

TYP

UNIT

C_IN

V_IN= 0V

FN8124 Rev 2.00

July 3, 2008

Page 8 of 15

X4C105

Serial Nonvolatile Write Cycle Timing

TYP

SYMBOL

PARAMETER

MIN

(Note 5)

MAX

UNIT

_WC(Note 5) Write Cycle Time

NOTE:

5. t_WCis the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the

minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used.

Equivalent AC Output Load Circuit for V = 3.0V to

3.6V

Serial Memory AC Characteristics

Serial AC Test Conditions

3.3V

Input pulse levels

V_CCx 0.1 to V_CCx 0.9

10ns

FOR V = 0.4V

Input rise and fall times

Input and output timing levels

Output load

1533

AND I = 2mA

V_CCx 0.5

SDA

Standard output load

100pF

Electrical Specifications T_A= -40°C to +85°C, V_CC= +3.0V to +3.6V, unless otherwise specified. Parameters with MIN and/or MAX limits

are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and

are not production tested.

400kHz OPTION

SYMBOL

f_SCL

PARAMETER

MIN

MAX

400

UNIT

kHz

SCL Clock Frequency

t_IN

Pulse Width of Spikes to be Suppressed by the Input Filter

SCL Low to SDA Data Out Valid

Time the Bus Must be Free Before a New Transmission Can Start

Clock Low Time

t_AA

0.1

0.9

µs

t_BUF

1.3

µs

t_LOW

1.3

µs

t_HIGH

Clock High Time

0.6

µs

t_SU:STA

t_HD:STA

t_SU:DAT

t_HD:DAT

t_SU:STO

t_DH

Start Condition Set-up Time

Start Condition Hold Time

0.6

µs

0.6

µs

Data In Set-up Time

100

Data In Hold Time

µs

Stop Condition Set-up Time

Data Output Hold Time

0.6

µs

t_R

SDA and SCL Rise Time

20 + 0.1Cb (Note 6)

300

t_F

SDA And SCL Fall Time

20 + 0.1Cb (Note 6)

t_{SU: S1, S2,WP}

t_{HD: S1, S2,WP}

S1, S2 and WP Set-up Time

S1, S2 and WP Hold Time

0.4

Capacitive Load for Each Bus Line

400

NOTES:

6. Cb = total capacitance of one bus line in pF.

FN8124 Rev 2.00

July 3, 2008

Page 9 of 15

X4C105

Serial Timing Diagrams

Bus Timing

HIGH

LOW

SCL

SU:DAT

SU:STO

SU:STA

HD:DAT

HD:STA

SDA IN

BUF

SDA OUT

S1, S2 and WP Pin Timing

START

SCL

CLK 1

CLK 9

SLAVE ADDRESS BYTE

SDA IN

HD: S1, S2, WP

SU: S1, S2, WP

S1, S2 AND WP

Write Cycle Timing

SCL

SDA

BIT OF LAST BYTE

ACK

STOP

START

CONDITION

NOVRAM Equivalent AC Load Circuits

NOVRAM AC Characteristics

NOVRAM AC Conditions of Test

3.3V

Input pulse levels

V_CCx 0.1 to V_CCx 0.9

10ns

Input rise and fall times

Input and output timing levels

1596

_CCx 0.5

3093

30pF

FN8124 Rev 2.00

July 3, 2008

Page 10 of 15

X4C105

NOVRAM Read Cycle Specifications

t_CE

t_OE

WES

WEH

OHZ

OLZ

D0 - D3

Electrical Specifications

Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature

limits established by characterization and are not production tested.

V_CC= 3.0V TO 3.6V

-40°C TO +85°C

SYMBOL

PARAMETER

MIN

MAX

120

UNIT

t_RC

t_CE

Read Cycle Time

Chip Enable Access Time

Output Enable Access Time

t_OE

t_OH

Output Hold From CE or OE High

Write Enable High Set-ups Time

Write Enable High Hold Time

t_WES

t_WEH

_LZ(Note 7) Chip Enable to Output in Low Z

_OLZ(Note 7) Output Enable to Output in Low Z

_HZ(Note 7) Chip Disable to Output in High Z

_OHZ(Note 7) Output Disable to Output in High Z

t_SOE(Note 7) OE Setup Prior to Operation in 2-wire Mode

_HOE(Note 7) OE Hold Following Operation in 2-wire Mode

NOTE:

100

7. t_LZand t_OLZmin.; t_SOEand t_HOEmin; and t_HZand t_OHZare periodically sampled and not 100% tested. t_HZmax. and t_OHZmax. are measured,

with CL = 5pF, from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven.

Electrical Specifications

V_CC= 3.0V to 3.6V, T_A= -40°C to +85°C. Parameters with MIN and/or MAX limits are 100% tested at +25°C,

unless otherwise specified. Temperature limits established by characterization and are not production

tested.

SYMBOL

PARAMETER

MIN

120

170

MAX

UNIT

t_WC

t_WC1

t_OES

t_OEH

Write Cycle Time

Output Enable HIGH Set-up Time

Output Enable HIGH Hold Time

FN8124 Rev 2.00

July 3, 2008

Page 11 of 15

X4C105

Electrical Specifications

V_CC= 3.0V to 3.6V, T_A= -40°C to +85°C. Parameters with MIN and/or MAX limits are 100% tested at +25°C,

unless otherwise specified. Temperature limits established by characterization and are not production

tested. (Continued)

SYMBOL

PARAMETER

MIN

MAX

UNIT

t_CW

t_CE

Chip Enable to End of Write Input

Write Set-up time

t_CH

Write Hold Time

t_WP

t_WP1

t_WPH

t_DS

Write Pulse Width

100

Write Pulse Width

Write Pulse HIGH Recovery Time

Data Set-up to End of Write

Data Hold Time

t_DH

t_NDO

New Data Output

t_SOE(Note 8) OE Set-up Prior to Operation In 2-wire Mode

100

_HOE(Note 8) OE Hold Following Operation in 2-wire Mode

t_WZ

t_OW

Write Enable to Output in HIGH-Z

Output Active From End of Write

_CHZ(Note 8) Chip Disable to Output in High Z

_OHZ(Note 8) Output Disable to Output in High Z

NOTE:

8. t_LZand t_OLZmin.; t_SOEand t_HOEmin; and t_HZand t_OHZare periodically sampled and not 100% tested. t_HZmax and t_OHZmax are measured, with

CL = 5pF, from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven.

NOVRAM WE Controlled Write Cycle

OES

OEH

WPH

D0-D3

DATA VALID

(DATA I/O)

NDO

O0-O3

NEW VALID DATA

PREVIOUS VALID DATA

(DATA OUT)

FN8124 Rev 2.00

July 3, 2008

Page 12 of 15

X4C105

NOVRAM CE Controlled Write Cycle

OES

OEH

WPH

D0-D3

DATA VALID

(DATA IN)

NDO

O0-O3

PREVIOUS VALID DATA

NEW VALID DATA

(DATA OUT)

Low Voltage Detect/Power Cycle Parameters Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise

specified. Temperature limits established by characterization and are not production

tested.

SYMBOLS

V_TRIP

t_RPD

PARAMETERS

MIN

TYP

MAX

2.95

500

UNIT

Reset Trip Voltage-blank

2.80

2.875

V_CCDetect to Reset Active

µs

t_PURST

t_F

Power-up Reset Time-Out Delay (t_PURSTOption 1)-Default

V_CCFall Time From V_CC= 3V to V_CC= 2.5V

V_CCRise Time From V_CC= 2.5V to V_CC= 3V

Output Pins Valid after V_CCExceeds V_TRIP

Reset valid V_CC

100

200

400

t_R

t_OVT

200

V_RVALID

FN8124 Rev 2.00

July 3, 2008

Page 13 of 15

X4C105

Low Voltage Detect and Output Pin Recall

TRIP

PURST

RPD

PURST

RVALID

RST

OVT

(min)

DATA VALID

O0-O3

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8124 Rev 2.00

July 3, 2008

Page 14 of 15

X4C105

Packaging Information

20-Lead Plastic, TSSOP, Package Type V

.025 (.65) BSC

.169 (4.3)

.177 (4.5)

.252 (6.4) BSC

.193 (4.9)

.200 (5.1)

.047 (1.20)

.0075 (.19)

.0118 (.30)

.002 (.05)

.006 (.15)

.010 (.25)

Gage Plane

0° - 8°

Seating Plane

.019 (.50)

.029 (.75)

Detail A (20X)

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

FN8124 Rev 2.00

July 3, 2008

Page 15 of 15

X4C105V相关文章

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X4C105V20产品参数

型号:	X4C105V20
是否Rohs认证：	不符合
生命周期：	Transferred
包装说明：	PLASTIC, TSSOP-20
Reach Compliance Code：	unknown
风险等级：	5.75
Is Samacsys：	N
可调阈值：	NO
模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e0
长度：	6.5 mm
信道数量：	1
功能数量：	1
端子数量：	20
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态：	Not Qualified
座面最大高度：	1.2 mm
最大供电电压 (Vsup)：	3.63 V
最小供电电压 (Vsup)：	2.97 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
宽度：	4.4 mm
Base Number Matches：	1

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