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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • XC2V3000-5FG676I
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    QQ:1594462451QQ:1594462451 复制
  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
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  • XC2V3000-5FG676I图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • XC2V3000-5FG676I 现货库存
  • 数量210 
  • 厂家XILINX 
  • 封装BGA 
  • 批号24+ 
  • 假一罚万,全新原装库存现货,可长期订货
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  • 755-83950019 QQ:800888908
  • XC2V3000-5FG676I图
  • 深圳市亿智腾科技有限公司

     该会员已使用本站8年以上
  • XC2V3000-5FG676I 现货库存
  • 数量8860 
  • 厂家XILINX 
  • 封装BGA 
  • 批号16+ 
  • 全新原装现货★★特价供应★★。★★特价★★假一赔十,工厂客户可放款
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  • 0755-82566711 QQ:799387964QQ:2777237833
  • XC2V3000-5FG676I图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • XC2V3000-5FG676I 现货库存
  • 数量5980 
  • 厂家XILINX 
  • 封装BGA/676 
  • 批号22+ 
  • 新到现货、一手货源、当天发货、bom配单
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  • 075584507705 QQ:2881512844
  • XC2V3000-5FG676I图
  • 千层芯半导体(深圳)有限公司

     该会员已使用本站9年以上
  • XC2V3000-5FG676I
  • 数量30617 
  • 厂家XILINX 
  • 封装aa 
  • 批号2018+ 
  • 主打XILINX品牌价格绝对优势
  • QQ:2685694974QQ:2685694974 复制
    QQ:2593109009QQ:2593109009 复制
  • 0755-83978748,0755-23611964,13760152475 QQ:2685694974QQ:2593109009
  • XC2V3000-5FG676I图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • XC2V3000-5FG676I
  • 数量3000 
  • 厂家XILINX 
  • 封装BGA 
  • 批号23+ 
  • 全新原装公司现货销售
  • QQ:1245773710QQ:1245773710 复制
    QQ:867789136QQ:867789136 复制
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  • XC2V3000-5FG676I图
  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • XC2V3000-5FG676I
  • 数量5600 
  • 厂家PLX 
  • 封装BGA-676 
  • 批号23+ 
  • 只做原装正品,深圳现货
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    QQ:1977615742QQ:1977615742 复制
  • 18929336553 QQ:2276916927QQ:1977615742
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • XC2V3000-5FG676I
  • 数量3258 
  • 厂家XILINX/赛灵思 
  • 封装NA/ 
  • 批号23+ 
  • 原厂直销,现货供应,账期支持!
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
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  • 北京耐芯威科技有限公司

     该会员已使用本站12年以上
  • XC2V3000-5FG676I
  • 数量
  • 厂家21+ 
  • 封装5000 
  • 批号 
  • 原装正品,公司现货
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 96-010-62104931 QQ:2880824479QQ:1344056792
  • XC2V3000-5FG676I图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • XC2V3000-5FG676I
  • 数量18530 
  • 厂家XILINX 
  • 封装BGA 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348339QQ:2885348339 复制
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  • 0755-82519391 QQ:2885348339QQ:2885348317
  • XC2V3000-5FG676I图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • XC2V3000-5FG676I
  • 数量8700 
  • 厂家xilinx 
  • 封装BGA 
  • 批号23+ 
  • 全新原装现货热卖
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    QQ:2885348339QQ:2885348339 复制
  • 0755-83209630 QQ:2885348317QQ:2885348339
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  • 深圳市恒益昌科技有限公司

     该会员已使用本站6年以上
  • XC2V3000-5FG676I
  • 数量4500 
  • 厂家XILINX 
  • 封装BGA 
  • 批号23+ 
  • 原装正品长期供货
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    QQ:974337758QQ:974337758 复制
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  • 首天国际(深圳)科技有限公司

     该会员已使用本站16年以上
  • XC2V3000-5FG676I
  • 数量1280 
  • 厂家XILINX 
  • 封装BGA 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:528164397QQ:528164397 复制
    QQ:1318502189QQ:1318502189 复制
  • 0755-82807802 QQ:528164397QQ:1318502189
  • XC2V3000-5FG676I图
  • 北京宏博智成电子有限公司

     该会员已使用本站16年以上
  • XC2V3000-5FG676I
  • 数量
  • 厂家XIL 
  • 封装 
  • 批号N/A 
  • 只做原装 原厂原装
  • QQ:584654416QQ:584654416 复制
    QQ:981827793QQ:981827793 复制
  • 010-63776410 QQ:584654416QQ:981827793
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  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • XC2V3000-5FG676I
  • 数量3000 
  • 厂家XILINX 
  • 封装BGA/676 
  • 批号22+ 
  • ★只做原装★正品现货★原盒原标★
  • QQ:2355507162QQ:2355507162 复制
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  • 86-755-83616256 QQ:2355507162QQ:2355507165
  • XC2V3000-5FG676I图
  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
  • XC2V3000-5FG676I
  • 数量72282 
  • 厂家XILINX/赛灵思 
  • 封装NA 
  • 批号23+ 
  • 一站式BOM配单,短缺料找现货,怕受骗,就找昂富电子.
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  • 0755-23611557【陈妙华 QQ:GTY82dX7
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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • XC2V3000-5FG676I
  • 数量65000 
  • 厂家XILINX 
  • 封装BGA 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
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  • 0755-23605827 QQ:2881495753
  • XC2V3000-5FG676I图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • XC2V3000-5FG676I
  • 数量3473 
  • 厂家XILINX 
  • 封装BGA 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894392QQ:2881894392 复制
    QQ:2881894393QQ:2881894393 复制
  • 0755-82556029 QQ:2881894392QQ:2881894393
  • XC2V3000-5FG676I图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • XC2V3000-5FG676I
  • 数量4325 
  • 厂家Xilinx 
  • 封装676-BGA 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894393QQ:2881894393 复制
    QQ:2881894392QQ:2881894392 复制
  • 0755- QQ:2881894393QQ:2881894392
  • XC2V3000-5FG676I图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • XC2V3000-5FG676I
  • 数量4325 
  • 厂家Xilinx 
  • 封装676-BGA 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894393QQ:2881894393 复制
    QQ:2881894392QQ:2881894392 复制
  • 0755- QQ:2881894393QQ:2881894392
  • XC2V3000-5FG676I图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • XC2V3000-5FG676I
  • 数量12300 
  • 厂家XILINX 
  • 封装BGA676 
  • 批号24+ 
  • ★原装真实库存★13点税!
  • QQ:2353549508QQ:2353549508 复制
    QQ:2885134615QQ:2885134615 复制
  • 0755-83201583 QQ:2353549508QQ:2885134615
  • XC2V3000-5FG676I图
  • 上海磐岳电子有限公司

     该会员已使用本站11年以上
  • XC2V3000-5FG676I
  • 数量5800 
  • 厂家XILINX 
  • 封装BGA 
  • 批号2024+ 
  • 全新原装现货,杜绝假货。
  • QQ:3003653665QQ:3003653665 复制
    QQ:1325513291QQ:1325513291 复制
  • 021-60341766 QQ:3003653665QQ:1325513291
  • XC2V3000-5FG676I图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站6年以上
  • XC2V3000-5FG676I
  • 数量6500 
  • 厂家XILINX 
  • 封装BGA 
  • 批号24+ 
  • 全新原装★真实库存★含13点增值税票!
  • QQ:2885134615QQ:2885134615 复制
    QQ:2353549508QQ:2353549508 复制
  • 0755-83201583 QQ:2885134615QQ:2353549508
  • XC2V3000-5FG676I图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • XC2V3000-5FG676I
  • 数量4321 
  • 厂家XILINX 
  • 封装BGA 
  • 批号24+ 
  • 全新原装现货,欢迎询购!
  • QQ:1950791264QQ:1950791264 复制
    QQ:221698708QQ:221698708 复制
  • 0755-83222787 QQ:1950791264QQ:221698708
  • XC2V3000-5FG676I图
  • 深圳市宏诺德电子科技有限公司

     该会员已使用本站8年以上
  • XC2V3000-5FG676I
  • 数量68000 
  • 厂家XILINX 
  • 封装BGA 
  • 批号22+ 
  • 全新进口原厂原装,优势现货库存,有需要联系电话:18818596997 QQ:84556259
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    QQ:783839662QQ:783839662 复制
  • 0755- QQ:84556259QQ:783839662
  • XC2V3000-5FG676I图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • XC2V3000-5FG676I
  • 数量1600 
  • 厂家XILINX 
  • 封装BGA 
  • 批号新年份 
  • 真实库存全新原装正品!代理此型号!
  • QQ:2881495751QQ:2881495751 复制
  • 0755-88917743 QQ:2881495751
  • XC2V3000-5FG676I图
  • 深圳市华芯盛世科技有限公司

     该会员已使用本站13年以上
  • XC2V3000-5FG676I
  • 数量865000 
  • 厂家XILINX 
  • 封装XILINX 
  • 批号最新批号 
  • 一级代理,原装特价现货!
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  • 0755-83225692 QQ:2881475757
  • XC2V3000-5FG676I图
  • 深圳市积美福电子科技有限公司

     该会员已使用本站4年以上
  • XC2V3000-5FG676I
  • 数量1560 
  • 厂家XILINX/赛灵思 
  • 封装BGA 
  • 批号21+ 
  • 只做原装正品,深圳现货库存
  • QQ:647176908QQ:647176908 复制
    QQ:499959596QQ:499959596 复制
  • 0755-83228296 QQ:647176908QQ:499959596
  • XC2V3000-5FG676I图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • XC2V3000-5FG676I
  • 数量2000 
  • 厂家XILINX 
  • 封装BGA 
  • 批号2021+ 
  • 原装假一赔十!可提供正规渠道证明!
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    QQ:3003819484QQ:3003819484 复制
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  • 深圳市美思瑞电子科技有限公司

     该会员已使用本站12年以上
  • XC2V3000-5FG676I
  • 数量9217 
  • 厂家XILINX 
  • 封装原厂原装 
  • 批号22+ 
  • 市场最低价!原厂原装假一罚十
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • XC2V3000-5FG676I
  • 数量18961 
  • 厂家XILINX 
  • 封装BGA 
  • 批号2023+ 
  • 绝对原装正品全新进口深圳现货
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    QQ:515102657QQ:515102657 复制
  • 深圳分公司0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
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  • 深圳市硅诺电子科技有限公司

     该会员已使用本站8年以上
  • XC2V3000-5FG676I
  • 数量22737 
  • 厂家XILINX 
  • 封装BGA676 
  • 批号17+ 
  • 原厂指定分销商,有意请来电或QQ洽谈
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    QQ:916896414QQ:916896414 复制
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  • 深圳市浩兴林电子有限公司

     该会员已使用本站16年以上
  • XC2V3000-5FG676I
  • 数量5000 
  • 厂家XILINX 
  • 封装SMD 
  • 批号2017+ 
  • 优势库存现货,部分无铅
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    QQ:351622092QQ:351622092 复制
  • 0755-82532799 QQ:382716594QQ:351622092
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  • 深圳市一呈科技有限公司

     该会员已使用本站9年以上
  • XC2V3000-5FG676I
  • 数量3210 
  • 厂家XILINX(赛灵思) 
  • 封装676-BBGA,FCBGA 
  • 批号23+ 
  • ▉原厂渠道▉支持实单
  • QQ:3003797048QQ:3003797048 复制
    QQ:3003797050QQ:3003797050 复制
  • 0755-82779553 QQ:3003797048QQ:3003797050
  • XC2V3000-5FG676I图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • XC2V3000-5FG676I
  • 数量12500 
  • 厂家XILINX 
  • 封装aa 
  • 批号24+ 
  • 原装假一赔十!可提供正规渠道证明!
  • QQ:3007947169QQ:3007947169 复制
    QQ:3007947210QQ:3007947210 复制
  • 755-83950895 QQ:3007947169QQ:3007947210
  • XC2V3000-5FG676I图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • XC2V3000-5FG676I
  • 数量210 
  • 厂家XILINX 
  • 封装BGA 
  • 批号24+ 
  • 假一罚万,全新原装库存现货,可长期订货
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  • 755-83950019 QQ:800888908
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  • 柒号芯城电子商务(深圳)有限公司

     该会员已使用本站13年以上
  • XC2V3000-5FG676I
  • 数量700000 
  • 厂家XILINX 
  • 封装676-BBGA,FCBGA 
  • 批号2023+ 
  • 柒号芯城跟原厂的距离只有0.07公分
  • QQ:2881677436QQ:2881677436 复制
    QQ:2881620402QQ:2881620402 复制
  • 18922803401 QQ:2881677436QQ:2881620402
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  • 上海熠富电子科技有限公司

     该会员已使用本站15年以上
  • XC2V3000-5FG676I
  • 数量7500 
  • 厂家XILINX 
  • 封装N/A 
  • 批号2024 
  • 上海原装现货库存,欢迎查询!
  • QQ:2719079875QQ:2719079875 复制
    QQ:2300949663QQ:2300949663 复制
  • 15821228847 QQ:2719079875QQ:2300949663
  • XC2V3000-5FG676I图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • XC2V3000-5FG676I
  • 数量12500 
  • 厂家XILINX 
  • 封装aa 
  • 批号24+ 
  • 原装假一赔十!可提供正规渠道证明!
  • QQ:3003818780QQ:3003818780 复制
    QQ:3003819484QQ:3003819484 复制
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  • 深圳市意好科技有限公司

     该会员已使用本站15年以上
  • XC2V3000-5FG676I
  • 数量9230 
  • 厂家XILINX 
  • 封装原厂 
  • 批号24+ 
  • 中华地区销售
  • QQ:2853107358QQ:2853107358 复制
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  • 深圳市斌腾达科技有限公司

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产品型号XC2V3000-5FG676I的概述

芯片XC2V3000-5FG676I的概述 芯片XC2V3000-5FG676I是由赛灵思(Xilinx)公司开发的专用集成电路(FPGA),属于其Virtex系列。这款FPGA具有高性能、灵活的可编程性和较强的并行处理能力,因此广泛应用于通信、消费电子、计算机、军事及工业控制等多个领域。XC2V3000-5FG676I特别适合于需要高带宽的信号处理应用,能够满足现代电子系统对灵活性和性能的要求。 随着数字技术的发展,针对不同应用需求,FPGA在嵌入式系统中的重要性日益提升。XC2V3000-5FG676I的设计使其支持复杂的逻辑运算和各种混合信号处理。FPGA的可重新编程特性,意味着用户可以根据具体的应用需求自行修改逻辑功能,这种优越性显著提高了设计的灵活性和适应能力。 芯片XC2V3000-5FG676I的详细参数 XC2V3000-5FG676I的主要技术参数包括以下几个方面: ...

产品型号XC2V3000-5FG676I的Datasheet PDF文件预览

0
R
Virtex-II 1.5V  
Field-Programmable Gate Arrays  
0
0
DS031-1 (v1.7) October 2, 2001  
Advance Product Specification  
®
Summary of Virtex -II Features  
Industry First Platform FPGA Solution  
-
-
-
Digitally Controlled Impedance (DCI) I/O: on-chip  
termination resistors for single-ended I/O standards  
IP-Immersion™ Architecture  
PCI-X @ 133 MHz, PCI @ 66 MHz and 33 MHz  
compliance, and CardBus compliant  
-
-
-
Densities from 40K to 8M system gates  
420 MHz internal clock speed (Advance Data)  
840+ Mb/s I/O (Advance Data)  
Differential Signaling  
·
840 Mb/s Low-Voltage Differential Signaling I/O  
(LVDS) with current mode drivers  
Bus LVDS I/O  
Lightning Data Transport (LDT) I/O with current  
driver buffers  
SelectRAM™ Memory Hierarchy  
-
3 Mb of True Dual-Port™ RAM in 18-Kbit block  
SelectRAM resources  
·
·
-
-
Up to 1.5 Mb of distributed SelectRAM resources  
High-performance interfaces to external memory  
·
Low-Voltage Positive Emitter-Coupled Logic  
(LVPECL) I/O  
·
·
·
·
DDR-SDRAM interface  
FCRAM interface  
QDR-SRAM interface  
Sigma RAM interface  
·
Built-in DDR Input and Output registers  
-
Proprietary high-performance SelectLink™  
Technology  
·
·
·
High-bandwidth data path  
Double Data Rate (DDR) link  
Web-based HDL generation methodology  
Arithmetic Functions  
-
-
Dedicated 18-bit x 18-bit multiplier blocks  
Fast look-ahead carry logic chains  
Supported by Xilinx Foundationand Alliance™  
Series Development Systems  
Flexible Logic Resources  
-
Up to 93,184 internal registers / latches with Clock  
-
-
-
Integrated VHDL and Verilog design flows  
Compilation of 10M system gates designs  
Internet Team Design (ITD) tool  
Enable  
-
Up to 93,184 look-up tables (LUTs) or cascadable  
16-bit shift registers  
SRAM-Based In-System Configuration  
-
-
Wide multiplexers and wide-input function support  
-
-
Fast SelectMAPconfiguration  
Horizontal cascade chain and Sum-of-Products  
support  
Triple Data Encryption Standard (DES) security  
option (Bitstream Encryption)  
-
Internal 3-state bussing  
-
-
-
-
IEEE1532 support  
High-Performance Clock Management Circuitry  
Partial reconfiguration  
Unlimited re-programmability  
Readback capability  
-
Up to 12 DCM (Digital Clock Manager) modules  
·
·
·
Precise clock de-skew  
Flexible frequency synthesis  
High-resolution phase shifting  
0.15 µm 8-Layer Metal process with 0.12 µm  
high-speed transistors  
-
16 global clock multiplexer buffers  
1.5 V (VCCINT) core power supply, dedicated 3.3 V  
CCAUX auxiliary and VCCO I/O power supplies  
Active InterconnectTechnology  
V
-
-
Fourth generation segmented routing structure  
Predictable, fast routing delay, independent of  
fanout  
IEEE 1149.1 compatible boundary-scan logic support  
Flip-Chip and Wire-Bond Ball Grid Array (BGA)  
packages in three standard fine pitches (0.80mm,  
1.00mm, and 1.27mm)  
SelectI/O-UltraTechnology  
-
-
Up to 1,108 user I/Os  
19 single-ended standards and six differential  
standards  
100% factory tested  
-
Programmable sink current (2 mA to 24 mA) per I/O  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS031-1 (v1.7) October 2, 2001  
Advance Product Specification  
www.xilinx.com  
1-800-255-7778  
Module 1 of 4  
1
R
Virtex-II 1.5V Field-Programmable Gate Arrays  
Table 1: Virtex-II Field-Programmable Gate Array Family Members  
CLB  
(1 CLB = 4 slices = Max 128 bits)  
SelectRAM Blocks  
Maximum  
System  
Gates Row x Col. Slices  
Array  
Distributed  
RAM Kbits  
Multiplier 18-Kbit Max RAM  
Max I/O  
Device  
XC2V40  
Blocks  
4
Blocks  
4
(Kbits)  
72  
DCMs Pads(1)  
40K  
80K  
250K  
500K  
1M  
8 x 8  
16 x 8  
256  
8
16  
4
4
88  
120  
200  
264  
432  
528  
624  
720  
912  
1,104  
1,108  
XC2V80  
512  
8
8
144  
XC2V250  
XC2V500  
XC2V1000  
XC2V1500  
XC2V2000  
XC2V3000  
XC2V4000  
XC2V6000  
XC2V8000  
Notes:  
24 x 16  
32 x 24  
40 x 32  
48 x 40  
56 x 48  
64 x 56  
80 x 72  
96 x 88  
112 x 104  
1,536  
3,072  
5,120  
7,680  
10,752  
14,336  
23,040  
33,792  
46,592  
48  
24  
24  
432  
8
96  
32  
32  
576  
8
160  
240  
336  
448  
720  
1,056  
1,456  
40  
40  
720  
8
1.5M  
2M  
48  
48  
864  
8
56  
56  
1,008  
1,728  
2,160  
2,592  
3,024  
8
3M  
96  
96  
12  
12  
12  
12  
4M  
120  
144  
168  
120  
144  
168  
6M  
8M  
1. See details in Table 2, Maximum Number of User I/O Pads.  
General Description  
The Virtex-II family is a platform FPGA developed for high  
performance from low-density to high-density designs that  
are based on IP cores and customized modules. The family  
delivers complete solutions for telecommunication, wire-  
less, networking, video, and DSP applications, including  
PCI, LVDS, and DDR interfaces.  
Table 2 shows the maximum number of user I/Os available.  
The Virtex-II device/package combination table (Table 6 at  
the end of this section) details the maximum number of I/Os  
for each device and package using wire-bond or flip-chip  
technology.  
Table 2: Maximum Number of User I/O Pads  
The leading-edge 0.15µm / 0.12µm CMOS 8-layer metal  
process and the Virtex-II architecture are optimized for high  
speed with low power consumption. Combining a wide vari-  
ety of flexible features and a large range of densities up to  
10 million system gates, the Virtex-II family enhances pro-  
grammable logic design capabilities and is a powerful alter-  
native to mask-programmed gates arrays. As shown in  
Table 1, the Virtex-II family comprises 12 members, ranging  
from 40K to 10M system gates.  
Device  
XC2V40  
Wire-Bond  
88  
Flip-Chip  
XC2V80  
120  
XC2V250  
XC2V500  
XC2V1000  
XC2V1500  
XC2V2000  
XC2V3000  
XC2V4000  
XC2V6000  
XC2V8000  
200  
264  
328  
432  
528  
392  
Packaging  
456  
624  
Offerings include ball grid array (BGA) packages with  
0.80mm, 1.00mm, and 1.27mm pitches. In addition to tradi-  
tional wire-bond interconnects, flip-chip interconnect is used  
in some of the BGA offerings. The use of flip-chip intercon-  
nect offers more I/Os than is possible in wire-bond versions  
of the similar packages. Flip-Chip construction offers the  
combination of high pin count with high thermal capacity.  
516  
720  
912  
1,104  
1,108  
Module 1 of 4  
2
www.xilinx.com  
1-800-255-7778  
DS031-1 (v1.7) October 2, 2001  
Advance Product Specification  
R
Virtex-II 1.5V Field-Programmable Gate Arrays  
Architecture  
Virtex-II Array Overview  
Virtex-II devices are user-programmable gate arrays with various configurable elements. The Virtex-II architecture is  
optimized for high-density and high-performance logic designs. As shown in Figure 1, the programmable device is  
comprised of input/output blocks (IOBs) and internal configurable logic blocks (CLBs).  
DCM  
DCM  
IOB  
Global Clock Mux  
Configurable Logic  
Programmable I/Os  
CLB  
Block SelectRAM  
Multiplier  
DS031_28_100900  
Figure 1: Virtex-II Architecture Overview  
Programmable I/O blocks provide the interface between  
package pins and the internal configurable logic. Most  
popular and leading-edge I/O standards are supported by  
the programmable IOBs.  
All programmable elements, including the routing  
resources, are controlled by values stored in static memory  
cells. These values are loaded in the memory cells during  
configuration and can be reloaded to change the functions  
of the programmable elements.  
The internal configurable logic includes four major elements  
organized in a regular array.  
Virtex-II Features  
Configurable Logic Blocks (CLBs) provide functional  
elements for combinatorial and synchronous logic,  
including basic storage elements. BUFTs (3-state  
buffers) associated with each CLB element drive  
dedicated segmentable horizontal routing resources.  
This section briefly describes Virtex-II features.  
Input/Output Blocks (IOBs)  
IOBs are programmable and can be categorized as follows:  
Input block with an optional single-data-rate or  
double-data-rate (DDR) register  
Block SelectRAM memory modules provide large  
18-Kbit storage elements of True Dual-Port RAM.  
Output block with an optional single-data-rate or DDR  
register, and an optional 3-state buffer, to be driven  
directly or through a single or DDR register  
Multiplier blocks are 18-bit x 18-bit dedicated  
multipliers.  
DCM (Digital Clock Manager) blocks provide  
self-calibrating, fully digital solutions for clock  
distribution delay compensation, clock multiplication  
and division, coarse and fine-grained clock phase  
shifting.  
Bi-directional block (any combination of input and  
output configurations)  
These registers are either edge-triggered D-type flip-flops  
or level-sensitive latches.  
A new generation of programmable routing resources called  
Active Interconnect Technology interconnects all of these  
elements. The general routing matrix (GRM) is an array of  
routing switches. Each programmable element is tied to a  
switch matrix, allowing multiple connections to the general  
routing matrix. The overall programmable interconnection is  
hierarchical and designed to support high-speed designs.  
IOBs support the following single-ended I/O standards:  
LVTTL, LVCMOS (3.3 V, 2.5 V, 1.8 V, and 1.5 V)  
PCI-X at 133 MHz, PCI (3.3 V at 33 MHz and 66 MHz)  
GTL and GTLP  
HSTL (Class I, II, III, and IV)  
DS031-1 (v1.7) October 2, 2001  
Advance Product Specification  
www.xilinx.com  
1-800-255-7778  
Module 1 of 4  
3
R
Virtex-II 1.5V Field-Programmable Gate Arrays  
SSTL (3.3 V and 2.5 V, Class I and II)  
AGP-2X  
A multiplier block is associated with each SelectRAM mem-  
ory block. The multiplier block is a dedicated 18 x 18-bit  
multiplier and is optimized for operations based on the block  
SelectRAM content on one port. The 18 x 18 multiplier can  
be used independently of the block SelectRAM resource.  
Read/multiply/accumulate operations and DSP filter struc-  
tures are extremely efficient.  
The digitally controlled impedance (DCI) I/O feature auto-  
matically provides on-chip termination for each I/O element.  
The IOB elements also support the following differential sig-  
naling I/O standards:  
LVDS  
Both the SelectRAM memory and the multiplier resource  
are connected to four switch matrices to access the general  
routing resources.  
BLVDS (Bus LVDS)  
ULVDS  
Global Clocking  
LDT  
LVPECL  
The DCM and global clock multiplexer buffers provide a  
complete solution for designing high-speed clocking  
schemes.  
Two adjacent pads are used for each differential pair. Two or  
four IOB blocks connect to one switch matrix to access the  
routing resources.  
Up to 12 DCM blocks are available. To generate de-skewed  
internal or external clocks, each DCM can be used to elimi-  
nate clock distribution delay. The DCM also provides 90-,  
180-, and 270-degree phase-shifted versions of its output  
clocks. Fine-grained phase shifting offers high-resolution  
phase adjustments in increments of 1/256 of the clock  
period. Very flexible frequency synthesis provides a clock  
output frequency equal to any M/D ratio of the input clock  
frequency, where M and D are two integers. For the exact  
timing parameters, see Virtex-II Electrical Characteris-  
tics.  
Configurable Logic Blocks (CLBs)  
CLB resources include four slices and two 3-state buffers.  
Each slice is equivalent and contains:  
Two function generators (F & G)  
Two storage elements  
Arithmetic logic gates  
Large multiplexers  
Wide function capability  
Fast carry look-ahead chain  
Horizontal cascade chain (OR gate)  
Virtex-II devices have 16 global clock MUX buffers, with up  
to eight clock nets per quadrant. Each global clock MUX  
buffer can select one of the two clock inputs and switch  
glitch-free from one clock to the other. Each DCM block is  
able to drive up to four of the 16 global clock MUX buffers.  
The function generators F & G are configurable as 4-input  
look-up tables (LUTs), as 16-bit shift registers, or as 16-bit  
distributed SelectRAM memory.  
Routing Resources  
In addition, the two storage elements are either edge-trig-  
gered D-type flip-flops or level-sensitive latches.  
The IOB, CLB, block SelectRAM, multiplier, and DCM ele-  
ments all use the same interconnect scheme and the same  
access to the global routing matrix. Timing models are  
shared, greatly improving the predictability of the perfor-  
mance of high-speed designs.  
Each CLB has internal fast interconnect and connects to a  
switch matrix to access general routing resources.  
Block SelectRAM Memory  
There are a total of 16 global clock lines, with eight available  
per quadrant. In addition, 24 vertical and horizontal long  
lines per row or column as well as massive secondary and  
local routing resources provide fast interconnect. Virtex-II  
buffered interconnects are relatively unaffected by net  
fanout and the interconnect layout is designed to minimize  
crosstalk.  
The block SelectRAM memory resources are 18 Kb of True  
Dual-Port RAM, programmable from 16K x 1 bit to 512 x 36  
bits, in various depth and width configurations. Each port is  
totally synchronous and independent, offering three  
"read-during-write" modes. Block SelectRAM memory is  
cascadable to implement large embedded storage blocks.  
Supported memory configurations for dual-port and sin-  
gle-port modes are shown in Table 3.  
Horizontal and vertical routing resources for each row or  
column include:  
Table 3: Dual-Port And Single-Port Configurations  
24 long lines  
16K x 1 bit  
8K x 2 bits  
4K x 4 bits  
2K x 9 bits  
1K x 18 bits  
512 x 36 bits  
120 hex lines  
40 double lines  
16 direct connect lines (total in all four directions)  
Module 1 of 4  
www.xilinx.com  
DS031-1 (v1.7) October 2, 2001  
4
1-800-255-7778  
Advance Product Specification  
R
Virtex-II 1.5V Field-Programmable Gate Arrays  
Boundary Scan  
Readback and Integrated Logic Analyzer  
Boundary scan instructions and associated data registers  
support a standard methodology for accessing and config-  
uring Virtex-II devices that complies with IEEE standards  
1149.1 - 1993 and 1532. A system mode and a test mode  
are implemented. In system mode, a Virtex-II device per-  
forms its intended mission even while executing non-test  
boundary-scan instructions. In test mode, boundary-scan  
test instructions control the I/O pins for testing purposes.  
The Virtex-II Test Access Port (TAP) supports BYPASS,  
PRELOAD, SAMPLE, IDCODE, and USERCODE non-test  
instructions. The EXTEST, INTEST, and HIGHZ test instruc-  
tions are also supported.  
Configuration data stored in Virtex-II configuration memory  
can be read back for verification. Along with the configura-  
tion data, the contents of all flip-flops/latches, distributed  
SelectRAM, and block SelectRAM memory resources can  
be read back. This capability is useful for real-time debug-  
ging.  
The Integrated Logic Analyzer (ILA) core and software pro-  
vides a complete solution for accessing and verifying  
Virtex-II devices.  
Virtex-II Device/Package Combinations  
and Maximum I/O  
Wire-bond and flip-chip packages are available. Table 4 and  
Table 5 show the maximum possible number of user I/Os in  
wire-bond and flip-chip packages, respectively. Table 6  
shows the number of available user I/Os for all device/pack-  
age combinations.  
Configuration  
Virtex-II devices are configured by loading data into internal  
configuration memory, using the following five modes:  
Slave-serial mode  
Master-serial mode  
CS denotes wire-bond chip-scale ball grid array (BGA)  
(0.80 mm pitch).  
Slave SelectMAP mode  
Master SelectMAP mode  
Boundary-Scan mode (IEEE 1532)  
FG denotes wire-bond fine-pitch BGA (1.00 mm pitch).  
FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).  
BG denotes standard BGA (1.27 mm pitch).  
A Data Encryption Standard (DES) decryptor is available  
on-chip to secure the bitstreams. One or two triple-DES key  
sets can be used to optionally encrypt the configuration  
information.  
BF denotes flip-chip BGA (1.27 mm pitch).  
The number of I/Os per package include all user I/Os except  
the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,  
PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,  
DXP, AND RSVD) and VBATT.  
Table 4: Wire-Bond Packages Information  
Package  
Pitch (mm)  
CS144  
0.80  
FG256  
1.00  
FG456  
1.00  
FG676  
1.00  
BG575  
1.27  
BG728  
1.27  
Size (mm)  
I/Os  
12 x 12  
92  
17 x 17  
172  
23 x 23  
324  
27 x 27  
484  
31 x 31  
408  
35 x 35  
516  
Table 5: Flip-Chip Packages Information  
Package FF896  
Pitch (mm) 1.00  
FF1152  
1.00  
FF1517  
1.00  
BF957  
1.27  
40 x 40  
684  
Size (mm)  
I/Os  
31 x 31  
624  
35 x 35  
824  
40 x 40  
1,108  
DS031-1 (v1.7) October 2, 2001  
www.xilinx.com  
Module 1 of 4  
Advance Product Specification  
1-800-255-7778  
5
R
Virtex-II 1.5V Field-Programmable Gate Arrays  
Table 6: Virtex-II Device/Package Combinations and Maximum Number of Available I/Os (Advance Information)  
Available I/Os  
XC2V XC2V  
XC2V  
250  
XC2V  
500  
XC2V  
1000  
XC2V  
1500  
XC2V  
2000  
XC2V  
3000  
XC2V  
4000  
XC2V  
6000  
XC2V  
8000  
Package  
CS144  
FG256  
FG456  
FG676  
FF896  
40  
88  
88  
80  
92  
92  
120  
172  
200  
172  
264  
172  
324  
392  
528  
456  
624  
484  
720  
432  
328  
FF1152  
FF1517  
BG575  
BG728  
BF957  
Notes:  
824  
912  
824  
824  
1,104  
1,108  
392  
408  
456  
624  
516  
684  
684  
684  
684  
1. All devices in a particular package are pin-out (footprint) compatible. In addition, the FG456 and FG676 packages are compatible, as  
are the FF896 and FF1152 packages.  
Virtex-II Ordering Information  
Virtex-II ordering information is shown in Figure 2  
Example: XC2V1000-5FG456C  
Device Type  
Temperature Range  
C = Commercial (Tj = 0˚C to +85˚C)  
I = Industrial (Tj = -40˚C to +100˚C)  
Speed Grade  
(-4, -5, -6)  
Number of Pins  
Package Type  
DS031_35_033001  
Figure 2: Virtex-II Ordering Information  
Module 1 of 4  
6
www.xilinx.com  
1-800-255-7778  
DS031-1 (v1.7) October 2, 2001  
Advance Product Specification  
R
Virtex-II 1.5V Field-Programmable Gate Arrays  
Revision History  
This section records the change history for this module of the data sheet.  
Date  
Version  
1.0  
Revision  
11/07/00  
12/06/00  
01/15/01  
Early access draft.  
Initial release.  
1.1  
1.2  
Added values to the tables in the Virtex-II Performance Characteristics and Virtex-II  
Switching Characteristics sections.  
01/25/01  
04/02/01  
07/30/01  
10/02/01  
1.3  
1.5  
1.6  
1.7  
The data sheet was divided into four modules (per the current style standard).  
Skipped v1.4 to sync up modules. Reverted to traditional double-column format.  
Made minor changes to items listed under Summary of Virtex®-II Features.  
Minor edits.  
Virtex-II Data Sheet  
The Virtex-II Data Sheet contains the following modules:  
DS031-1, Virtex-II 1.5V FPGAs: Introduction and  
Ordering Information (Module 1)  
DS031-3, Virtex-II 1.5V FPGAs: DC and Switching  
Characteristics (Module 3)  
DS031-4, Virtex-II 1.5V FPGAs: Pinout Tables  
(Module 4)  
DS031-2, Virtex-II 1.5V FPGAs: Functional Description  
(Module 2)  
DS031-1 (v1.7) October 2, 2001  
Advance Product Specification  
www.xilinx.com  
1-800-255-7778  
Module 1 of 4  
7
配单直通车
XC2V3000-5FG676I产品参数
型号:XC2V3000-5FG676I
是否无铅: 含铅
是否Rohs认证: 不符合
生命周期:Obsolete
零件包装代码:BGA
包装说明:27 X 27 MM, 1 MM PITCH, MS-034AAL-1, FBGA-676
针数:676
Reach Compliance Code:not_compliant
ECCN代码:3A991.D
HTS代码:8542.39.00.01
风险等级:5.79
最大时钟频率:750 MHz
CLB-Max的组合延迟:0.39 ns
JESD-30 代码:S-PBGA-B676
JESD-609代码:e0
长度:27 mm
湿度敏感等级:3
可配置逻辑块数量:3584
等效关口数量:3000000
输入次数:484
逻辑单元数量:32256
输出次数:484
端子数量:676
组织:3584 CLBS, 3000000 GATES
封装主体材料:PLASTIC/EPOXY
封装代码:BGA
封装等效代码:BGA676,26X26,40
封装形状:SQUARE
封装形式:GRID ARRAY
峰值回流温度(摄氏度):225
电源:1.5,1.5/3.3,3.3 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified
座面最大高度:2.6 mm
子类别:Field Programmable Gate Arrays
最大供电电压:1.575 V
最小供电电压:1.425 V
标称供电电压:1.5 V
表面贴装:YES
技术:CMOS
端子面层:Tin/Lead (Sn63Pb37)
端子形式:BALL
端子节距:1 mm
端子位置:BOTTOM
处于峰值回流温度下的最长时间:30
宽度:27 mm
Base Number Matches:1
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