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Spartan-7 FPGAs Data Sheet:

DC and AC Switching Characteristics

DS189 (v1.8) September 28, 2018

Product Specification

Introduction

Spartan®-7 FPGAs are available in -2, -1, and -1L speed grades, with -2 having the highest performance.

The Spartan-7 FPGAs predominantly operate at a 1.0V core voltage. The -1L devices are screened for lower

maximum static power and can operate at lower core voltages for lower dynamic power than the -1

devices. The -1L devices operate only at V_CCINT= V_CCBRAM= 0.95V and have the same speed

specifications as the -1 speed grade.

Spartan-7 FPGA DC and AC characteristics are specified in commercial (C), industrial (I), and expanded (Q)

temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC

electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1Q

expanded speed grade device are the same as for a -1C commercial speed grade device). However, only

selected speed grades and/or devices are available in each temperature range. For example, the -1L speed

grade is only available in the industrial (I) temperature range.

All supply voltage and junction temperature specifications are representative of worst-case conditions.

The parameters included are common to popular designs and typical applications.

Available device and package combinations can be found in:

•

7 Series FPGAs Overview (DS180) [Ref 1]

XA Spartan-7 Automotive FPGA Data Sheet: Overview (DS171) [Ref 2]

This Spartan-7 FPGA data sheet, part of an overall set of documentation on the 7 series FPGAs, is available

on the Xilinx website at www.xilinx.com/documentation.

DC Characteristics

Table 1: Absolute Maximum Ratings⁽¹⁾

Symbol

Description

Min

Max

Units

FPGA Logic

V_CCINT

V_CCAUX

V_CCBRAM

V_CCO

Internal supply voltage.

Auxiliary supply voltage.

–0.5

1.1

2.0

1.1

3.6

2.0

V

Supply voltage for the block RAM memories.

Output drivers supply voltage for HR I/O banks.

Input reference voltage.

V_REF

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1

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 1: Absolute Maximum Ratings⁽¹⁾(Cont’d)

Symbol

Description

Min

Max

Units

I/O input voltage.

–0.4

V_CCO+ 0.55

V

(2)(3)(4)

V_IN

I/O input voltage (when V_CCO= 3.3V) for V_REFand differential I/O

standards except TMDS_33.⁽⁵⁾

–0.4

–0.5

2.625

2.0

V

V_CCBATT

XADC

Key memory battery backup supply.

V_CCADC

V_REFP

XADC supply relative to GNDADC.

–0.5

2.0

V

XADC reference input relative to GNDADC.

Temperature

T_STG

Storage temperature (ambient).

–65

–

150

°C

Maximum soldering temperature for Pb/Sn component bodies.⁽⁶⁾

Maximum soldering temperature for Pb-free component bodies.⁽⁶⁾

Maximum junction temperature.⁽⁶⁾

+220

+260

+125

T_SOL

–

T_j

–

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.

Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.

2. The lower absolute voltage specification always applies.

3. For I/O operation, refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471) [Ref 3].

4. The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4.

5. See Table 9 for TMDS_33 specifications.

6. For soldering guidelines and thermal considerations, see the 7 Series FPGA Packaging and Pinout Specification (UG475) [Ref 4].

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2

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 2: Recommended Operating Conditions⁽¹⁾⁽²⁾

Symbol

Description

Min

Typ

Max

Units

FPGA Logic

For -2 and -1 (1.0V) devices: internal supply voltage.

For -1L (0.95V) devices: internal supply voltage.

Auxiliary supply voltage.

0.95

0.92

1.71

0.95

0.92

1.14

–0.20

1.00

0.95

1.80

1.00

0.95

–

1.05

0.98

V

(3)

V_CCINT

V_CCAUX

1.89

For -2 and -1 (1.0V) devices: block RAM supply voltage.

For -1L (0.95V) devices: block RAM supply voltage.

Supply voltage for HR I/O banks.

1.05

(3)

V_CCBRAM

0.98

(4)(5)

V_CCO

3.465

I/O input voltage.

–

V_CCO+ 0.20

(6)

V_IN

I/O input voltage (when V_CCO= 3.3V) for V_REFand

differential I/O standards except TMDS_33.⁽⁷⁾

–0.20

–

2.625

V

Maximum current through any pin in a powered or unpowered

bank when forward biasing the clamp diode.

(8)

I_IN

–

10

mA

V

(9)

V_CCBATT

Battery voltage.

1.0

1.89

XADC

V_CCADC

V_REFP

XADC supply relative to GNDADC.

1.71

1.20

1.80

1.25

1.89

1.30

V

Externally supplied reference voltage.

Temperature

Junction temperature operating range for commercial (C)

temperature devices.

0

–

85

°C

Junction temperature operating range for industrial (I)

temperature devices.

–40

100

T_j

Junction temperature operating range for expanded (Q)

temperature devices.

–40

–

125

°C

Notes:

1. All voltages are relative to ground.

2. For the design of the power distribution system consult the 7 Series FPGAs PCB Design Guide (UG483) [Ref 5].

3. If V and V are operating at the same voltage, V and V should be connected to the same supply.

CCINT

CCBRAM

CCINT

CCBRAM

4. Configuration data is retained even if V

drops to 0V.

CCO

5. Includes V

of 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, and 3.3V at ±5%.

CCO

6. The lower absolute voltage specification always applies.

7. See Table 9 for TMDS_33 specifications.

8. A total of 200 mA per bank should not be exceeded.

9.

V

is required only when using bitstream encryption. If battery is not used, connect V

to either ground or V

.

CCBATT

CCAUX

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3

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 3: DC Characteristics Over Recommended Operating Conditions

Symbol

Description

Min

Typ⁽¹⁾

Max

Units

Data retention V_CCINTvoltage (below which configuration

data might be lost).

V_DRINT

0.75

–

V

Data retention V_CCAUXvoltage (below which configuration

data might be lost).

V_DRI

1.5

–

V

I_REF

I_L

V_REFleakage current per pin.

–

15

µA

pF

Input or output leakage current per pin (sample-tested).

Die input capacitance at the pad.

(2)

C_IN

–

8

Pad pull-up (when selected) at V_IN= 0V, V_CCO= 3.3V.

Pad pull-up (when selected) at V_IN= 0V, V_CCO= 2.5V.

Pad pull-up (when selected) at V_IN= 0V, V_CCO= 1.8V.

Pad pull-up (when selected) at V_IN= 0V, V_CCO= 1.5V.

Pad pull-up (when selected) at V_IN= 0V, V_CCO= 1.2V.

Pad pull-down (when selected) at V_IN= 3.3V.

Analog supply current, analog circuits in powered up state.

Battery supply current.

90

68

34

23

12

68

–

330

250

220

150

120

330

25

µA

mA

nA

I_RPU

I_RPD

I_CCADC

(3)

I_BATT

–

150

Thevenin equivalent resistance of programmable input

termination to V_CCO/2 (UNTUNED_SPLIT_40).

28

35

44

40

50

60

55

65

83

Ω

Thevenin equivalent resistance of programmable input

termination to V_CCO/2 (UNTUNED_SPLIT_50).

(4)

R_{IN_TERM}

Thevenin equivalent resistance of programmable input

termination to V_CCO/2 (UNTUNED_SPLIT_60).

n

r

Temperature diode ideality factor.

Temperature diode series resistance.

–

1.010

2

–

Ω

Notes:

1. Typical values are specified at nominal voltage, 25°C.

2. This measurement represents the die capacitance at the pad, not including the package.

3. Maximum value specified for worst case process at 25°C.

4. Termination resistance to a V

/2 level.

CCO

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Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 4: V_INMaximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks⁽¹⁾⁽²⁾

AC Voltage Overshoot

% of UI at –40°C to 125°C

AC Voltage Undershoot

–0.40

% of UI at –40°C to 125°C

100

61.7

25.8

11.0

4.77

2.10

0.94

0.43

0.20

0.09

0.04

0.02

–0.45

V_CCO+ 0.55

100

–0.50

–0.55

V

_CCO+ 0.60

_CCO+ 0.65

_CCO+ 0.70

_CCO+ 0.75

_CCO+ 0.80

_CCO+ 0.85

_CCO+ 0.90

_CCO+ 0.95

46.6

21.2

9.75

4.55

2.15

1.02

0.49

0.24

–0.60

–0.65

–0.70

–0.75

–0.80

–0.85

–0.90

–0.95

Notes:

1. A total of 200 mA per bank should not be exceeded.

2. The peak voltage of the overshoot or undershoot, and the duration above V

+ 0.20V or below GND – 0.20V, must not exceed the values

CCO

in this table.

Table 5: Typical Quiescent Supply Current^(1)(2)(3)

Speed Grade

Symbol

Description

Device

1.0V

0.95V Units

-1LI

-2C

36

-2I

36

-1C

36

-1I

36

-1Q

36

XC7S6

32

mA

XC7S15

XC7S25

XC7S50

XC7S75

XC7S100

XA7S6

36

48

43

95

59

148

N/A

148

36

148

N/A

148

36

148

36

134

N/A

I_CCINTQ

Quiescent V_CCINTsupply current.

XA7S15

XA7S25

XA7S50

XA7S75

XA7S100

36

48

95

148

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5

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 5: Typical Quiescent Supply Current^(1)(2)(3)(Cont’d)

Speed Grade

1.0V

Symbol

Description

Device

0.95V Units

-1LI

-2C

1

-2I

1

-1C

1

-1I

1

-1Q

1

XC7S6

1

mA

XC7S15

XC7S25

XC7S50

XC7S75

XC7S100

XA7S6

1

4

I_CCOQ

Quiescent V_CCOsupply current.

N/A

10

1

N/A

10

1

N/A

10

XA7S15

XA7S25

XA7S50

XA7S75

XA7S100

XC7S6

1

4

10

13

22

43

10

13

22

43

10

13

22

43

10

13

22

43

10

13

22

43

10

13

22

43

XC7S15

XC7S25

XC7S50

XC7S75

XC7S100

XA7S6

10

13

22

20

43

I_CCAUXQ

Quiescent V_CCAUXsupply current.

N/A

XA7S15

XA7S25

XA7S50

XA7S75

XA7S100

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Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 5: Typical Quiescent Supply Current^(1)(2)(3)(Cont’d)

Speed Grade

1.0V

Symbol

Description

Device

0.95V Units

-1LI

-2C

1

-2I

1

2

9

1

2

9

-1C

1

-1I

1

2

9

1

2

9

-1Q

1

XC7S6

1

mA

XC7S15

XC7S25

XC7S50

XC7S75

XC7S100

XA7S6

1

2

1

9

8

9

8

I_CCBRAMQQuiescent V_CCBRAMsupply current.

N/A

1

N/A

XA7S15

XA7S25

XA7S50

XA7S75

XA7S100

1

2

9

Notes:

1. Typical values are specified at nominal voltage, 85°C junction temperature (T ) with single-ended SelectIO™ resources.

j

2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and

floating.

3. Use the Xilinx Power Estimator spreadsheet tool [Ref 6] to estimate static power consumption for conditions other than those specified.

Power-On/Off Power Supply Sequencing

The recommended power-on sequence is V_CCINT, V_CCBRAM, V_CCAUX, and V_CCOto achieve minimum current

draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the

reverse of the power-on sequence. If V_CCINTand V_CCBRAMhave the same recommended voltage levels then

both can be powered by the same supply and ramped simultaneously. If V_CCAUXand V_CCOhave the same

recommended voltage levels then both can be powered by the same supply and ramped simultaneously.

For V_CCOvoltages of 3.3V in HR I/O banks and configuration bank 0 the following conditions apply.

•

The voltage difference between V_CCOand V_CCAUXmust not exceed 2.625V for longer than

T_VCCO2VCCAUXfor each power-on/off cycle to maintain device reliability levels.

The T_VCCO2VCCAUXtime can be allocated in any percentage between the power-on and power-off

ramps.

There is no recommended sequence for supplies not discussed in this section.

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Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 6 shows the minimum current, in addition to I_CCQmaximum, that is required by Spartan-7 devices for

proper power-on and configuration. If the current minimums shown in Table 6 are met, the device powers

on after all four supplies have passed through their power-on reset threshold voltages. The FPGA must not

be configured until after V_CCINTis applied. Once initialized and configured, use the Xilinx Power Estimator

spreadsheet tool [Ref 6] to estimate current drain on these supplies.

Table 6: Power-On Current

Device

I_CCINTMIN

I_CCAUXMIN

I_CCOMIN

I_CCBRAMMIN

Units

mA

XC7S6

I_CCINTQ+ 120

I_CCAUXQ+ 40

I_CCAUXQ+ 140

I_CCAUXQ+ 40

I_CCAUXQ+ 140

I_CCOQ+ 40 mA per bank

I_CCBRAMQ+ 60

XC7S15

XC7S25

XC7S50

XC7S75

XC7S100

XA7S6

I

_CCINTQ+ 120

_CCINTQ+ 300

_CCINTQ+ 120

_CCINTQ+ 300

XA7S15

XA7S25

XA7S50

XA7S75

XA7S100

Table 7: Power Supply Ramp Time

Symbol

Description

Conditions

Min

0.2

–

Max Units

T_VCCINT

T_VCCO

T_VCCAUX

T_VCCBRAM

Ramp time from GND to 90% of V_CCINT

Ramp time from GND to 90% of V_CCO

Ramp time from GND to 90% of V_CCAUX

Ramp time from GND to 90% of V_CCBRAM

.

50

ms

.

50

.

50

T_J= 125°C⁽¹⁾

300

500

800

T_VCCO2VCCAUXAllowed time per power cycle for V_CCO– V_CCAUX> 2.625V. T_J= 100°C⁽¹⁾

T_J= 85°C⁽¹⁾

–

Notes:

1. Based on 240,000 power cycles with a nominal V

of 3.3V or 36,500 power cycles with a worst case V

of 3.465V.

CCO

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8

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

DC Input and Output Levels

Values for V_ILand V_IHare recommended input voltages. Values for I_OLand I_OHare guaranteed over the

recommended operating conditions at the V_OLand V_OHtest points. Only selected standards are tested.

These are chosen to ensure that all standards meet their specifications. The selected standards are tested

at a minimum V_CCOwith the respective V_OLand V_OHvoltage levels shown. Other standards are sample

tested.

Table 8: SelectIO DC Input and Output Levels^(1)(2)(3)

V_IL

V, Max

V_IH

V_OL

V_OH

I_OL

I_OH

I/O Standard

V, Min

V, Max

0.400

V, Min

mA, Max mA, Min

HSTL_I

–0.300 V_REF– 0.100 V_REF+ 0.100 V_CCO+ 0.300

–0.300 V_REF– 0.130 V_REF+ 0.130 V_CCO+ 0.300

V_CCO– 0.400

80% V_CCO

8.00

–8.00

HSTL_I_18

HSTL_II

0.400

16.00

0.10

–16.00

–0.10

HSTL_II_18

HSUL_12

LVCMOS12

LVCMOS15

LVCMOS18

LVCMOS25

LVCMOS33

LVTTL

0.400

20% V_CCO

0.400

–0.300 35% V_CCO

65% V_CCOV_CCO+ 0.300

V_CCO– 0.400

75% V_CCO

Note 4 Note 4

Note 5 Note 5

Note 6 Note 6

Note 5 Note 5

Note 6 Note 6

25% V_CCO

0.450

V_CCO– 0.450

V_CCO– 0.400

–0.300

0.7

0.8

1.700

2.000

V

_CCO+ 0.300

3.450

0.400

V

_CCO– 0.400

3.450

0.400

2.400

MOBILE_DDR –0.300 20% V_CCO

80% V_CCOV_CCO+ 0.300

50% V_CCOV_CCO+ 0.500

10% V_CCO

90% V_CCO

0.10

1.50

–0.10

–0.50

–13.00

–8.90

–13.00

–8.90

–8.00

–13.40

PCI33_3

–0.400 30% V_CCO

SSTL135

SSTL135_R

SSTL15

–0.300 V_REF– 0.090 V_REF+ 0.090 V_CCO+ 0.300 V_CCO/2 – 0.150 V_CCO/2 + 0.150 13.00

–0.300 V_REF– 0.090 V_REF+ 0.090 V_CCO+ 0.300 V_CCO/2 – 0.150 V_CCO/2 + 0.150 8.90

–0.300 V_REF– 0.100 V_REF+ 0.100 V_CCO+ 0.300 V_CCO/2 – 0.175 V_CCO/2 + 0.175 13.00

SSTL15_R

SSTL18_I

SSTL18_II

–0.300 V_REF– 0.100 V_REF+ 0.100 V_CCO+ 0.300 V_CCO/2 – 0.175 V_CCO/2 + 0.175

–0.300 V_REF– 0.125 V_REF+ 0.125 V_CCO+ 0.300 V_CCO/2 – 0.470 V_CCO/2 + 0.470

8.90

8.00

–0.300 V_REF– 0.125 V_REF+ 0.125 V_CCO+ 0.300 V_CCO/2 – 0.600 V_CCO/2 + 0.600 13.40

Notes:

1. Tested according to relevant specifications.

2. 3.3V and 2.5V standards are only supported in HR I/O banks.

3. For detailed interface specific DC voltage levels, see the 7 Series FPGAs SelectIO Resources User Guide (UG471) [Ref 3].

4. Supported drive strengths of 4, 8, or 12 mA in HR I/O banks.

5. Supported drive strengths of 4, 8, 12, or 16 mA in HR I/O banks.

6. Supported drive strengths of 4, 8, 12, 16, or 24 mA in HR I/O banks.

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Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 9: Differential SelectIO DC Input and Output Levels

(1)

(2)

(3)

(4)

V_ICM

V,

V_ID

V_OCM

V,

V_OD

V,

I/O Standard

V,

Min

V,

Max

V,

Min Typ Max Min Typ Max

Typ

Min Typ Max

BLVDS_25

0.300 1.200 1.425 0.100

–

1.250

1.200

0.950

1.200

–

Note 5

MINI_LVDS_25 0.300 1.200 V_CCAUX0.200 0.400 0.600

1.000

0.500

1.000

1.400

0.300 0.450 0.600

0.100 0.250 0.400

0.100 0.350 0.600

PPDS_25

RSDS_25

TMDS_33

0.200 0.900 V_CCAUX0.100 0.250 0.400

0.300 0.900 1.500 0.100 0.350 0.600

2.700 2.965 3.230 0.150 0.675 1.200 V_CCO– 0.405 V_CCO– 0.300 V_CCO– 0.190 0.400 0.600 0.800

Notes:

1.

2.

3.

4.

5.

V

is the input common mode voltage.

is the input differential voltage (Q – Q).

ICM

ID

is the output common mode voltage.

OCM

is the output differential voltage (Q – Q).

for BLVDS will vary significantly depending on topology and loading.

OD

Table 10: Complementary Differential SelectIO DC Input and Output Levels

(1)

(2)

(3)

(4)

V_ICM

V, Min V, Typ V, Max V, Min V, Max

V_ID

V_OL

V_OH

I_OL

I_OH

I/O Standard

V, Max

0.400

V, Min

mA, Max mA, Min

DIFF_HSTL_I

0.300 0.750 1.125 0.100

0.300 0.900 1.425 0.100

0.300 0.750 1.125 0.100

0.300 0.900 1.425 0.100

0.300 0.600 0.850 0.100

–

V

_CCO– 0.400

80% V_CCO

90% V_CCO

8.00

16.00

0.100

13.0

8.9

–8.00

–16.00

–0.100

–13.0

–8.9

DIFF_HSTL_I_18

DIFF_HSTL_II

DIFF_HSTL_II_18

DIFF_HSUL_12

0.400

20% V_CCO

10% V_CCO

DIFF_MOBILE_DDR 0.300 0.900 1.425 0.100

DIFF_SSTL135

DIFF_SSTL135_R

DIFF_SSTL15

0.300 0.675 1.000 0.100

0.300 0.750 1.125 0.100

0.300 0.900 1.425 0.100

(V_CCO/2) – 0.150 (V_CCO/2) + 0.150

(V_CCO/2) – 0.175 (V_CCO/2) + 0.175

(V_CCO/2) – 0.470 (V_CCO/2) + 0.470

(V_CCO/2) – 0.600 (V_CCO/2) + 0.600

13.0

8.9

–13.0

–8.9

DIFF_SSTL15_R

DIFF_SSTL18_I

DIFF_SSTL18_II

8.00

13.4

–8.00

–13.4

Notes:

1.

2.

3.

4.

V

is the input common mode voltage.

is the input differential voltage (Q – Q).

is the single-ended low-output voltage.

ICM

ID

OL

OH

is the single-ended high-output voltage.

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Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

LVDS DC Specifications (LVDS_25)

Table 11: LVDS_25 DC Specifications⁽¹⁾

Symbol

V_CCO

V_OH

DC Parameter

Conditions

Min

Typ

Max Units

Supply voltage.

Output High voltage for Q and Q. R_T= 100Ω across Q and Q signals.

2.375 2.500 2.625

V

–

1.675

–

V_OL

Output Low voltage for Q and Q. R_T= 100Ω across Q and Q signals. 0.700

Differential output voltage:

V_ODIFF

(Q – Q), Q = High

R_T= 100Ω across Q and Q signals.

247

350

600

mV

V

(Q – Q), Q = High

V_OCM

Output common-mode voltage.

Differential input voltage:

(Q – Q), Q = High

R_T= 100Ω across Q and Q signals. 1.000 1.250 1.425

V_IDIFF

100

350

600

mV

V

(Q – Q), Q = High

V_ICM

Input common-mode voltage.

0.300 1.200 1.500

Notes:

1. Differential inputs for LVDS_25 can be placed in banks with V

levels that are different from the required level for outputs. Consult the

CCO

7 Series FPGAs SelectIO Resources User Guide (UG471) [Ref 3] for more information.

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11

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

AC Switching Characteristics

All values represented in this data sheet are based on the speed specifications from the Vivado® Design

Suite as outlined in Table 12.

Table 12: Speed Specification Version By Device

2018.2.1

1.23

Device

XC7S6, XC7S15, XC7S25, XC7S50, XC7S75, XC7S100

XA7S6, XA7S15, XA7S25, XA7S50, XA7S75, XA7S100

1.16

Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance,

Preliminary, or Production. Each designation is defined as follows.

Advance Product Specification

These specifications are based on simulations only and are typically available soon after device design

specifications are frozen. Although speed grades with this designation are considered relatively stable and

conservative, some under-reporting might still occur.

Preliminary Product Specification

These specifications are based on complete ES (engineering sample) silicon characterization. Devices and

speed grades with this designation are intended to give a better indication of the expected performance

of production silicon. The probability of under-reporting delays is greatly reduced as compared to

Advance data.

Production Product Specification

These specifications are released once enough production silicon of a particular device family member has

been characterized to provide full correlation between specifications and devices over numerous

production lots. There is no under-reporting of delays, and customers receive formal notification of any

subsequent changes. Typically, the slowest speed grades transition to Production before faster speed

grades.

Testing of AC Switching Characteristics

Internal timing parameters are derived from measuring internal test patterns. All AC switching

characteristics are representative of worst-case supply voltage and junction temperature conditions.

For more specific, more precise, and worst-case guaranteed data, use the values reported by the static

timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all

Spartan-7 FPGAs.

DS189 (v1.8) September 28, 2018

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12

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Speed Grade Designations

Since individual family members are produced at different times, the migration from one category to

another depends completely on the status of the fabrication process for each device. Table 13 correlates

the current status of each Spartan-7 device on a per speed grade basis.

Table 13: Spartan-7 Device Speed Grade Designations

Speed Grade, Temperature Range, and V_CCINTOperating Voltage

Device

Advance

Preliminary

Production

-2C (1.0V), -2I (1.0V), -1C (1.0V),

-1I (1.0V), -1Q (1.0V), and -1LI (0.95V)⁽¹⁾

XC7S6

-2C (1.0V), -2I (1.0V), -1C (1.0V),

XC7S15

XC7S25

XC7S50

XC7S75

XC7S100

-1I (1.0V), -1Q (1.0V), and -1LI (0.95V)⁽¹⁾

-2C (1.0V), -2I (1.0V), -1C (1.0V),

-1I (1.0V), -1Q (1.0V), and -1LI (0.95V)⁽¹⁾

-2C (1.0V), -2I (1.0V), -1C (1.0V),

-1I (1.0V), -1Q (1.0V), and -1LI (0.95V)⁽¹⁾

-2C (1.0V), -2I (1.0V), -1C (1.0V),

-1I (1.0V), -1Q (1.0V), and -1LI (0.95V)⁽¹⁾

-2C (1.0V), -2I (1.0V), -1C (1.0V),

-1I (1.0V), -1Q (1.0V), and -1LI (0.95V)⁽¹⁾

XA7S6

-2I (1.0V), -1I (1.0V), -1Q (1.0V)

XA7S15

XA7S25

XA7S50

XA7S75

XA7S100

Notes:

1. The lowest power -1LI devices, where V

= 0.95V, are listed in the Vivado Design Suite as -1IL.

CCINT

Production Silicon and Software Status

In some cases, a particular family member (and speed grade) is released to production before a speed

specification is released with the correct label (Advance, Preliminary, Production). Any labeling

discrepancies are corrected in subsequent speed specification releases.

Table 14 lists the production released Spartan-7 device, speed grade, and the minimum corresponding

supported speed specification version and software revisions. The software and speed specifications

listed are the minimum releases required for production. All subsequent releases of software and speed

specifications are valid.

DS189 (v1.8) September 28, 2018

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13

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 14: Spartan-7 Device Production Software and Speed Specification Release

V_CCINTOperating Voltage, Speed Grade, and Temperature Range

Device

1.0V

-1C

0.95V

-1LI

-2C

-2I

-1I

-1Q

Vivado tools

XC7S6

Vivado tools 2018.2 v1.22

Vivado tools 2017.4 v1.20

Vivado tools 2017.2 v1.17

Vivado tools 2018.1 v1.21

2018.2.1 v1.23 2018.2 v1.22

Vivado tools Vivado tools

2018.2.1 v1.23 2018.2 v1.22

XC7S15

XC7S25

XC7S50

XC7S75

XC7S100

XA7S6

Vivado tools

2018.1 v1.21

Vivado tools

2017.4 v1.20

Vivado tools

2017.3 v1.19

Vivado tools

2017.2 v1.17

Vivado tools

2018.2.1 v1.23 2018.1 v1.21

Vivado tools Vivado tools

2018.2.1 v1.23 2018.1 v1.21

Vivado tools

N/A

Vivado tools 2018.2.1 v1.16

Vivado tools 2018.1 v1.15

Vivado tools 2017.3 v1.12

Vivado tools 2018.2.1 v1.16

N/A

2018.2.1 v1.16

Vivado tools

N/A

XA7S15

XA7S25

XA7S50

XA7S75

XA7S100

2018.2.1 v1.16

Vivado tools

N/A

2018.1 v1.15

Vivado tools

N/A

2017.3 v1.12

Vivado tools

N/A

2018.2.1 v1.16

Vivado tools

N/A

2018.2.1 v1.16

Performance Characteristics

This section provides the performance characteristics of some common functions and designs

implemented in Spartan-7 FPGAs. These values are subject to the same guidelines as the AC Switching

Characteristics, page 12.

Table 15: Networking Applications Interface Performances

V_CCINTOperating Voltage, Speed

Grade, and Temperature Range

Description

Units

1.0V

-1C/-1I/-1Q

0.95V

-2C/-2I

680

-1LI

600

950

600

SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8)

DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14)

SDR LVDS receiver⁽¹⁾

600

950

600

Mb/s

1250

680

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14

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 15: Networking Applications Interface Performances (Cont’d)

V

_CCINTOperating Voltage, Speed

Grade, and Temperature Range

Description

Units

1.0V

-1C/-1I/-1Q

0.95V

-1LI

-2C/-2I

DDR LVDS receiver⁽¹⁾

1250

950

Mb/s

Notes:

1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate

deterministic performance.

Table 16: Maximum Physical Interface (PHY) Rate for Memory Interface IP available with the Memory Interface

Generator⁽¹⁾

V

_CCINTOperating Voltage, Speed Grade,

and Temperature Range

Memory Standard

Units

1.0V

-1C/-1I/-1Q

0.95V

-1LI

-2C/-2I

4:1 Memory Controllers

DDR3

800⁽²⁾

667

Mb/s

DDR3L

DDR2

2:1 Memory Controllers

DDR3

800⁽²⁾

667

533

667

533

Mb/s

DDR3L

DDR2

LPDDR2

Notes:

1.

V

tracking is required. For more information, see the Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions User Guide (UG586)

REF

[Ref 7].

2. The maximum PHY rate is 667 Mb/s in the FTGB196 package.

IOB Pad Input/Output/3-State

Table 17 summarizes the values of standard-specific data input delay adjustments, output delays

terminating at pads (based on standard) and 3-state delays.

•

T_IOPIis described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The

delay varies depending on the capability of the SelectIO input buffer.

T_IOOPis described as the delay from the O pin to the IOB pad through the output buffer of an IOB

pad. The delay varies depending on the capability of the SelectIO output buffer.

T_IOTPis described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad,

when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer.

In HR I/O banks, the IN_TERM termination turn-on time is always faster than T_IOTPwhen the

INTERMDISABLE pin is used.

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15

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 17: IOB High Range (HR) Switching Characteristics

T_IOPI

T_IOOP

T_IOTP

V

_CCINTOperating Voltage and Speed Grade

I/O Standard

Units

1.0V

0.95V

1.0V

0.95V

1.0V

0.95V

-2

-1

-1L

-2

-1

-1L

-2

-1

-1L

LVTTL_S4

1.34

0.81

1.41

0.88

1.39

0.82

0.83

0.91

0.85

0.82

0.80

0.82

0.81

0.83

0.86

0.85

0.82

0.80

0.82

1.41

0.88

1.39

0.82

0.83

0.91

0.85

0.82

0.80

0.82

0.81

0.83

0.86

0.85

0.82

0.80

0.82

3.93

3.66

3.65

3.19

3.41

3.38

2.87

2.85

2.68

2.65

1.41

1.40

1.96

1.40

1.41

1.54

3.22

1.93

1.41

1.93

1.41

1.80

1.51

1.82

1.57

1.74

1.54

1.41

1.54

1.71

1.63

1.51

1.58

1.22

1.24

1.26

4.18

3.92

3.90

3.45

3.67

3.64

3.12

3.10

2.93

2.90

1.67

1.65

2.21

1.65

1.67

1.79

3.48

2.18

1.67

2.18

1.67

2.06

1.76

2.07

1.82

1.99

1.79

1.67

1.79

1.96

1.88

1.76

1.84

1.48

1.49

1.51

4.18

3.92

3.90

3.45

3.67

3.64

3.12

3.10

2.93

2.90

1.67

1.65

2.21

1.65

1.67

1.79

3.48

2.18

1.67

2.18

1.67

2.06

1.76

2.07

1.82

1.99

1.79

1.67

1.79

1.96

1.88

1.76

1.84

1.48

1.49

1.51

3.96

3.69

3.68

3.22

3.44

3.41

2.90

2.88

2.71

2.68

1.44

1.43

1.99

1.43

1.44

1.57

3.25

1.96

1.44

1.96

1.44

1.83

1.54

1.85

1.60

1.77

1.57

1.44

1.57

1.74

1.66

1.54

1.61

1.25

1.27

1.29

4.20

3.93

3.91

3.46

3.68

3.65

3.13

3.12

2.95

2.91

1.68

1.66

2.23

1.66

1.68

1.80

3.49

2.20

1.68

2.20

1.68

2.07

1.77

2.09

1.84

2.01

1.80

1.68

1.80

1.98

1.90

1.77

1.85

1.49

1.51

1.52

4.20

3.93

3.91

3.46

3.68

3.65

3.13

3.12

2.95

2.91

1.68

1.66

2.23

1.66

1.68

1.80

3.49

2.20

1.68

2.20

1.68

2.07

1.77

2.09

1.84

2.01

1.80

1.68

1.80

1.98

1.90

1.77

1.85

1.49

1.51

1.52

ns

LVTTL_S8

LVTTL_S12

LVTTL_S16

LVTTL_S24

LVTTL_F4

LVTTL_F8

LVTTL_F12

LVTTL_F16

LVTTL_F24

LVDS_25

MINI_LVDS_25

BLVDS_25

RSDS_25 (point to point) 0.81

PPDS_25

0.81

1.32

0.75

0.76

0.84

0.78

0.75

0.73

0.75

0.76

0.79

0.78

0.75

0.73

0.75

TMDS_33

PCI33_3

HSUL_12_S

HSUL_12_F

DIFF_HSUL_12_S

DIFF_HSUL_12_F

MOBILE_DDR_S

MOBILE_DDR_F

DIFF_MOBILE_DDR_S

DIFF_MOBILE_DDR_F

HSTL_I_S

HSTL_II_S

HSTL_I_18_S

HSTL_II_18_S

DIFF_HSTL_I_S

DIFF_HSTL_II_S

DIFF_HSTL_I_18_S

DIFF_HSTL_II_18_S

HSTL_I_F

HSTL_II_F

HSTL_I_18_F

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16

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 17: IOB High Range (HR) Switching Characteristics (Cont’d)

T_IOPI

T_IOOP

T_IOTP

V

_CCINTOperating Voltage and Speed Grade

I/O Standard

Units

1.0V

0.95V

1.0V

0.95V

1.0V

0.95V

-2

-1

-1L

-2

-1

-1L

-2

-1

-1L

HSTL_II_18_F

0.75

0.76

0.79

0.78

1.34

1.20

0.83

0.86

0.81

0.83

0.86

0.85

1.41

1.27

0.89

0.93

0.81

0.83

0.86

0.85

1.41

1.27

0.89

0.93

1.24

1.30

1.33

3.93

3.65

3.21

3.52

3.38

2.87

2.68

3.26

3.01

2.60

2.94

2.87

2.30

2.29

2.13

1.74

2.30

1.65

1.72

1.57

1.80

1.52

1.46

2.18

2.21

1.71

1.97

1.49

1.56

1.59

4.18

3.90

3.46

3.77

3.64

3.12

2.93

3.51

3.26

2.85

3.20

3.12

2.56

2.54

2.39

1.99

2.56

1.90

1.98

1.82

2.06

1.77

1.71

2.43

2.46

1.96

2.23

1.49

1.56

1.59

4.18

3.90

3.46

3.77

3.64

3.12

2.93

3.51

3.26

2.85

3.20

3.12

2.56

2.54

2.39

1.99

2.56

1.90

1.98

1.82

2.06

1.77

1.71

2.43

2.46

1.96

2.23

1.27

1.33

1.36

3.96

3.68

3.24

3.55

3.41

2.90

2.71

3.29

3.04

2.63

2.97

2.90

2.33

2.32

2.16

1.77

2.33

1.68

1.75

1.60

1.83

1.55

1.49

2.21

2.24

1.74

2.00

1.51

1.57

1.60

4.20

3.91

3.48

3.79

3.65

3.13

2.95

3.52

3.27

2.87

3.21

3.13

2.57

2.55

2.40

2.01

2.57

1.91

1.99

1.84

2.07

1.79

1.73

2.45

2.48

1.98

2.24

1.51

1.57

1.60

4.20

3.91

3.48

3.79

3.65

3.13

2.95

3.52

3.27

2.87

3.21

3.13

2.57

2.55

2.40

2.01

2.57

1.91

1.99

1.84

2.07

1.79

1.73

2.45

2.48

1.98

2.24

ns

DIFF_HSTL_I_F

DIFF_HSTL_II_F

DIFF_HSTL_I_18_F

DIFF_HSTL_II_18_F

LVCMOS33_S4

LVCMOS33_S8

LVCMOS33_S12

LVCMOS33_S16

LVCMOS33_F4

LVCMOS33_F8

LVCMOS33_F12

LVCMOS33_F16

LVCMOS25_S4

LVCMOS25_S8

LVCMOS25_S12

LVCMOS25_S16

LVCMOS25_F4

LVCMOS25_F8

LVCMOS25_F12

LVCMOS25_F16

LVCMOS18_S4

LVCMOS18_S8

LVCMOS18_S12

LVCMOS18_S16

LVCMOS18_S24

LVCMOS18_F4

LVCMOS18_F8

LVCMOS18_F12

LVCMOS18_F16

LVCMOS18_F24

LVCMOS15_S4

LVCMOS15_S8

LVCMOS15_S12

LVCMOS15_S16

LVCMOS15_F4

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17

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 17: IOB High Range (HR) Switching Characteristics (Cont’d)

T_IOPI

T_IOOP

T_IOTP

V

_CCINTOperating Voltage and Speed Grade

I/O Standard

Units

1.0V

0.95V

1.0V

0.95V

1.0V

0.95V

-2

-1

-1L

-2

-1

-1L

-2

-1

-1L

LVCMOS15_F8

0.86

0.95

0.75

0.68

0.75

0.76

0.79

0.75

0.68

0.75

0.76

0.79

0.93

1.02

0.82

0.75

0.82

0.83

0.86

0.82

0.75

0.82

0.83

0.86

0.93

1.02

0.82

0.75

0.82

0.83

0.86

0.82

0.75

0.82

0.83

0.86

1.72

1.47

1.46

2.69

2.21

1.91

2.10

1.66

1.51

1.47

1.43

1.79

1.43

1.47

1.43

1.80

1.51

1.24

1.19

1.24

1.19

1.35

1.33

1.98

1.73

1.71

2.95

2.46

2.17

2.35

1.92

1.76

1.73

1.68

2.04

1.68

1.73

1.68

2.06

1.76

1.49

1.45

1.49

1.45

1.60

1.59

1.98

1.73

1.71

2.95

2.46

2.17

2.35

1.92

1.76

1.73

1.68

2.04

1.68

1.73

1.68

2.06

1.76

1.49

1.45

1.49

1.45

1.60

1.59

1.75

1.50

1.49

2.72

2.24

1.94

2.13

1.69

1.54

1.50

1.46

1.82

1.46

1.50

1.46

1.83

1.54

1.27

1.22

1.27

1.22

1.38

1.36

1.99

1.74

1.73

2.96

2.48

2.18

2.37

1.93

1.77

1.74

1.69

2.06

1.70

1.74

1.69

2.07

1.77

1.51

1.46

1.51

1.46

1.62

1.60

1.99

1.74

1.73

2.96

2.48

2.18

2.37

1.93

1.77

1.74

1.69

2.06

1.70

1.74

1.69

2.07

1.77

1.51

1.46

1.51

1.46

1.62

1.60

ns

LVCMOS15_F12

LVCMOS15_F16

LVCMOS12_S4

LVCMOS12_S8

LVCMOS12_S12

LVCMOS12_F4

LVCMOS12_F8

LVCMOS12_F12

SSTL135_S

SSTL15_S

SSTL18_I_S

SSTL18_II_S

DIFF_SSTL135_S

DIFF_SSTL15_S

DIFF_SSTL18_I_S

DIFF_SSTL18_II_S

SSTL135_F

SSTL15_F

SSTL18_I_F

SSTL18_II_F

DIFF_SSTL135_F

DIFF_SSTL15_F

DIFF_SSTL18_I_F

DIFF_SSTL18_II_F

Table 18 specifies the values of T_IOTPHZand T_{IOIBUFDISABLE}. T_IOTPHZis described as the delay from the T pin

to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance

state). T_{IOIBUFDISABLE}is described as the IOB delay from IBUFDISABLE to O output. In HR I/O banks, the

internal IN_TERM termination turn-off time is always faster than T_IOTPHZwhen the INTERMDISABLE pin is

used.

DS189 (v1.8) September 28, 2018

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18

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 18: IOB 3-state Output Switching Characteristics

V_CCINTOperating Voltage and

Speed Grade

Symbol

Description

Units

1.0V

0.95V

-2

-1

-1L

T_IOTPHZ

T input to pad high-impedance.

2.19

2.30

2.37

2.60

2.37

2.60

ns

T_{IOIBUFDISABLE}IBUF turn-on time from IBUFDISABLE to O output.

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19

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

I/O Standard Adjustment Measurement Methodology

Input Delay Measurements

Table 19 shows the test setup parameters used for measuring input delay.

Table 19: Input Delay Measurement Methodology

(1)

(3)(5)

(2)(4)

Description

I/O Standard Attribute

LVCMOS12

LVCMOS15

LVCMOS18

LVCMOS25

LVCMOS33

LVTTL

V_L

V_H

V_MEAS

V_REF

LVCMOS, 1.2V

0.1

1.1

0.6

–

LVCMOS, 1.5V

LVCMOS, 1.8V

LVCMOS, 2.5V

LVCMOS, 3.3V

LVTTL, 3.3V

1.4

1.7

2.4

3.2

1.7

3.2

0.75

0.9

–

1.25

1.65

0.9

MOBILE_DDR, 1.8V

PCI33, 3.3V

MOBILE_DDR

PCI33_3

1.65

HSTL (high-speed transceiver

logic), Class I, 1.2V

HSTL_I_12

V

_REF– 0.5

V_REF+ 0.5

V_REF+ 0.65

V_REF+ 0.8

V_REF

0.60

0.75

0.90

HSTL, Class I & II, 1.5V

HSTL_I, HSTL_II

V_REF– 0.65

V_REF– 0.8

HSTL_I_18,

HSTL_II_18

HSTL, Class I & II, 1.8V

HSUL (high-speed

unterminated logic), 1.2V

HSUL_12

SSTL12

V_REF– 0.5

V_REF+ 0.5

V_REF

0.60

SSTL (stub-terminated

transceiver logic), 1.2V

V

_REF– 0.5

SSTL, 1.35V

SSTL135, SSTL135_R

SSTL15, SSTL15_R

SSTL18_I, SSTL18_II

DIFF_MOBILE_DDR

DIFF_HSTL_I_12

V_REF– 0.575 V_REF+ 0.575

V_REF

0⁽⁵⁾

0.675

0.75

0.90

–

SSTL, 1.5V

V_REF– 0.65

V_REF+ 0.65

V_REF+ 0.8

0.9 + 0.125

0.6 + 0.125

SSTL, Class I & II, 1.8V

DIFF_MOBILE_DDR, 1.8V

DIFF_HSTL, Class I, 1.2V

V_REF– 0.8

0.9 – 0.125

0.6 – 0.125

0⁽⁵⁾

–

DIFF_HSTL_I,

DIFF_HSTL_II

DIFF_HSTL, Class I & II,1.5V

0.75 – 0.125 0.75 + 0.125

0⁽⁵⁾

–

DIFF_HSTL_I_18,

DIFF_HSTL_II_18

DIFF_HSTL, Class I & II, 1.8V

DIFF_HSUL, 1.2V

0.9 – 0.125

0.6 – 0.125

0.9 + 0.125

0.6 + 0.125

0⁽⁵⁾

–

DIFF_HSUL_12

DIFF_SSTL135/

DIFF_SSTL135_R, 1.35V

DIFF_SSTL135,

DIFF_SSTL135_R

0.675 – 0.125 0.675 + 0.125

0.75 – 0.125 0.75 + 0.125

DIFF_SSTL15/

DIFF_SSTL15_R, 1.5V

DIFF_SSTL15,

DIFF_SSTL15_R

0⁽⁵⁾

–

DIFF_SSTL18_I/

DIFF_SSTL18_II, 1.8V

DIFF_SSTL18_I,

DIFF_SSTL18_II

0.9 – 0.125

1.2 – 0.125

0.9 + 0.125

1.2 + 0.125

LVDS_25, 2.5V

LVDS_25

0⁽⁵⁾

–

BLVDS_25, 2.5V

MINI_LVDS_25, 2.5V

BLVDS_25

1.25 – 0.125 1.25 + 0.125

MINI_LVDS_25

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20

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 19: Input Delay Measurement Methodology (Cont’d)

(1)

(3)(5)

(2)(4)

Description

I/O Standard Attribute

PPDS_25

V_L

V_H

V_MEAS

V_REF

PPDS_25

RSDS_25

TMDS_33

1.25 – 0.125 1.25 + 0.125

0⁽⁵⁾

–

RSDS_25

–

TMDS_33

3 – 0.125

3 + 0.125

Notes:

1. Input waveform switches between V and V .

L

H

2. Measurements are made at typical, minimum, and maximum V

values. Reported delays reflect worst case of these measurements. V

REF

values listed are typical.

3. Input voltage level from which measurement starts.

4. This is an input voltage reference that bears no relation to the V

5. The value given is the differential input voltage.

/ V

parameters found in IBIS models and/or noted in Figure 1.

MEAS

REF

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21

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Output Delay Measurements

Output delays are measured with short output traces. Standard termination was used for all testing. The

propagation delay of the trace is characterized separately and subtracted from the final measurement, and

is therefore not included in the generalized test setups shown in Figure 1 and Figure 2.

X-Ref Target - Figure 1

V_REF

R_REF

Output

V_MEAS(voltage level when taking delay measurement)

C_REF(probe capacitance)

X16654-092616

Figure 1: Single-ended Test Setup

X-Ref Target - Figure 2

Output

+

C_REF

R_REF

V_MEAS

–

X16640-092616

Figure 2: Differential Test Setup

Parameters V_REF, R_REF, C_REF, and V_MEASfully describe the test conditions for each I/O standard. The most

accurate prediction of propagation delay in any given application can be obtained through IBIS

simulation, using this method:

1. Simulate the output driver of choice into the generalized test setup using values from Table 20.

2. Record the time to V_MEAS

.

3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS

model or capacitance value to represent the load.

4. Record the time to V_MEAS

.

5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual

propagation delay of the PCB trace.

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22

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 20: Output Delay Measurement Methodology

(1)

R_REFC_REF

V_MEASV_REF

Description

I/O Standard Attribute

(Ω)

1M

25

50

25

50

25

50

(pF)

(V)

LVCMOS, 1.2V

LVCMOS, 1.5V

LVCMOS, 1.8V

LVCMOS, 2.5V

LVCMOS, 3.3V

LVTTL, 3.3V

LVCMOS12

0

0.6

0

LVCMOS15

LVCMOS18

LVCMOS25

LVCMOS33

LVTTL

0

0.75

0.9

0

1.25

1.65

V_REF

0

PCI33, 3.3V

PCI33_3

10

0

HSTL (high-speed transceiver logic), Class I, 1.2V HSTL_I_12

0.6

0.75

0.9

0.6

HSTL, Class I, 1.5V

HSTL_I

0

HSTL, Class II, 1.5V

HSTL_II

0

HSTL, Class I, 1.8V

HSTL_I_18

HSTL_II_18

HSUL_12

0

HSTL, Class II, 1.8V

0

HSUL (high-speed unterminated logic), 1.2V

SSTL12, 1.2V

0

SSTL12

0

SSTL135/SSTL135_R, 1.35V

SSTL15/SSTL15_R, 1.5V

SSTL135, SSTL135_R

SSTL15, SSTL15_R

0

V_REF0.675

0

V_REF

0.75

SSTL (stub-series terminated logic),

Class I & Class II, 1.8V

SSTL18_I, SSTL18_II

50

0

V_REF

0.9

DIFF_MOBILE_DDR, 1.8V

DIFF_HSTL, Class I, 1.2V

DIFF_HSTL, Class I & II, 1.5V

DIFF_MOBILE_DDR

50

0

V_REF

0.9

0.6

DIFF_HSTL_I_12

DIFF_HSTL_I, DIFF_HSTL_II

0.75

DIFF_HSTL_I_18,

DIFF_HSTL_II_18

DIFF_HSTL, Class I & II, 1.8V

DIFF_HSUL_12, 1.2V

50

0

V_REF

0.9

0.6

DIFF_HSUL_12

DIFF_SSTL135,

DIFF_SSTL135_R

DIFF_SSTL135/DIFF_SSTL135_R, 1.35V

DIFF_SSTL15/DIFF_SSTL15_R, 1.5V

DIFF_SSTL18, Class I & II, 1.8V

V_REF0.675

DIFF_SSTL15, DIFF_SSTL15_R

V_REF

0.75

0.9

DIFF_SSTL18_I,

DIFF_SSTL18_II

LVDS, 2.5V

LVDS_25

100

50

0

0⁽²⁾

0

BLVDS (Bus LVDS), 2.5V

Mini LVDS, 2.5V

PPDS_25

BLVDS_25

MINI_LVDS_25

PPDS_25

0

RSDS_25

0

TMDS_33

3.3

Notes:

1.

C

is the capacitance of the probe, nominally 0 pF.

REF

2. The value given is the differential output voltage.

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23

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Input/Output Logic Switching Characteristics

Table 21: ILOGIC Switching Characteristics

V_CCINTOperating Voltage and

Speed Grade

Symbol

Description

Units

1.0V

0.95V

-1L

-2

-1

Setup/Hold

T_ICE1CK/T_ICKCE1

CE1 pin setup/hold with respect to CLK.

SR pin setup/hold with respect to CLK.

0.54/0.02 0.76/0.02 0.76/0.02

0.70/0.01 1.13/0.01 1.13/0.01

ns

T

_ISRCK/T_ICKSR

D pin setup/hold with respect to CLK without

delay.

T_IDOCK/T_IOCKD

0.01/0.29 0.01/0.33 0.01/0.33

0.02/0.29 0.02/0.33 0.02/0.33

ns

DDLY pin setup/hold with respect to CLK (using

IDELAY).

T_IDOCKD/T_IOCKDD

Combinatorial

T_IDI

D pin to O pin propagation delay, no delay.

0.11

0.12

0.13

0.14

0.13

0.14

ns

DDLY pin to O pin propagation delay (using

IDELAY).

T_IDID

Sequential Delays

T_IDLO

D pin to Q1 pin using flip-flop as a latch without

delay.

0.44

0.51

ns

DDLY pin to Q1 pin using flip-flop as a latch (using

IDELAY).

T_IDLOD

T_ICKQ

CLK to Q outputs.

0.57

1.08

7.60

0.66

1.32

0.66

1.32

ns

T_{RQ_ILOGIC}

T_{GSRQ_ILOGIC}

Set/Reset

T_{RPW_ILOGIC}

SR pin to OQ/TQ out.

Global set/reset to Q outputs.

10.51

Minimum pulse width, SR inputs.

0.72

ns, Min

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24

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 22: OLOGIC Switching Characteristics

V_CCINTOperating Voltage and Speed

Grade

Symbol

Description

Units

1.0V

0.95V

-1L

-2

-1

Setup/Hold

T_ODCK/T_OCKD

D1/D2 pins setup/hold with respect to CLK.

0.71/–0.11 0.84/–0.11 0.84/–0.11

0.34/0.58 0.51/0.58 0.51/0.58

0.44/0.21 0.80/0.21 0.80/0.21

0.73/–0.14 0.89/–0.14 0.89/–0.14

0.34/0.01 0.51/0.01 0.51/0.01

ns

T

_OOCECK/T_OCKOCEOCE pin setup/hold with respect to CLK.

_OSRCK/T_OCKSR

_OTCK/T_OCKT

SR pin setup/hold with respect to CLK.

T1/T2 pins setup/hold with respect to CLK.

_OTCECK/T_OCKTCETCE pin setup/hold with respect to CLK.

Combinatorial

T_ODQ

D1 to OQ out or T1 to TQ out.

0.96

1.16

ns

Sequential Delays

T_OCKQ

CLK to OQ/TQ out.

0.49

0.80

7.60

0.56

0.95

0.56

0.95

ns

T_{RQ_OLOGIC}

T_{GSRQ_OLOGIC}

Set/Reset

SR pin to OQ/TQ out.

Global set/reset to Q outputs.

10.51

T_{RPW_OLOGIC}

Minimum pulse width, SR inputs.

0.74

ns, Min

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Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Input Serializer/Deserializer Switching Characteristics

Table 23: ISERDES Switching Characteristics

V_CCINTOperating Voltage and Speed

Grade

Symbol

Description

Units

1.0V

0.95V

-1L

-2

-1

Setup/Hold for Control Lines

T_{ISCCK_BITSLIP}

T_{ISCKC_BITSLIP}

T_{ISCCK_CE}

T_{ISCKC_CE}

T_{ISCCK_CE2}

T_{ISCKC_CE2}

/

BITSLIP pin setup/hold with respect to

CLKDIV.

0.02/0.15 0.02/0.17 0.02/0.17

0.50/–0.01 0.72/–0.01 0.72/–0.01

–0.10/0.36 –0.10/0.40 –0.10/0.40

ns

/

CE pin setup/hold with respect to CLK

(for CE1).

/

CE pin setup/hold with respect to CLKDIV

(for CE2).

Setup/Hold for Data Lines

T_{ISDCK_D}

T_{ISCKD_D}

T_{ISDCK_DDLY}

T_{ISCKD_DDLY}

T_{ISDCK_D_DDR}

T_{ISCKD_D_DDR}

/

D pin setup/hold with respect to CLK.

–0.02/0.14 –0.02/0.17 –0.02/0.17

0.14/0.14 0.17/0.17 0.17/0.17

ns

/

DDLY pin setup/hold with respect to CLK

(using IDELAY).⁽¹⁾

/

D pin setup/hold with respect to CLK at

DDR mode.

T_{ISDCK_DDLY_DDR}/ D pin setup/hold with respect to CLK at

T_{ISCKD_DDLY_DDR}DDR mode (using IDELAY).⁽¹⁾

Sequential Delays

T_{ISCKO_Q}

CLKDIV to out at Q pin.

D input to DO output pin.

0.54

0.11

0.66

0.13

0.66

0.13

ns

Propagation Delays

T_{ISDO_DO}

Notes:

1. Recorded at 0 tap value.

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Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Output Serializer/Deserializer Switching Characteristics

Table 24: OSERDES Switching Characteristics

V_CCINTOperating Voltage and Speed

Grade

Symbol

Description

Units

1.0V

0.95V

-1L

-2

-1

Setup/Hold

T_{OSDCK_D}

T_{OSCKD_D}

T_{OSDCK_T}

T_{OSCKD_T}

T_{OSDCK_T2}

T_{OSCKD_T2}

T_{OSCCK_OCE}

T_{OSCKC_OCE}

/

D input setup/hold with respect to CLKDIV.

T input setup/hold with respect to CLK.

T input setup/hold with respect to CLKDIV.

0.45/0.03 0.63/0.03 0.63/0.03

0.73/–0.13 0.88/–0.13 0.88/–0.13

0.34/–0.13 0.39/–0.13 0.39/–0.13

0.34/0.58 0.51/0.58 0.51/0.58

ns

/

OCE input setup/hold with respect to CLK.

SR (reset) input setup with respect to CLKDIV.

TCE input setup/hold with respect to CLK.

ns

T_{OSCCK_S}

0.52

0.85

T_{OSCCK_TCE}

T_{OSCKC_TCE}

/

0.34/0.01 0.51/0.01 0.51/0.01

Sequential Delays

T_{OSCKO_OQ}

T_{OSCKO_TQ}

Combinatorial

T_{OSDO_TTQ}

Clock to out from CLK to OQ.

0.42

0.49

0.48

0.56

0.48

0.56

ns

Clock to out from CLK to TQ.

T input to TQ out.

0.92

1.11

ns

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27

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Input/Output Delay Switching Characteristics

Table 25: Input/Output Delay Switching Characteristics

V_CCINTOperating Voltage and

Speed Grade

Symbol

Description

Units

1.0V

0.95V

-1L

-2

-1

IDELAYCTRL

T_{DLYCCO_RDY}

Reset to ready for IDELAYCTRL.

3.67

200.00

300.00

N/A

3.67

200.00

300.00

N/A

µs

Attribute REFCLK frequency = 200.00.⁽¹⁾

Attribute REFCLK frequency = 300.00.⁽¹⁾

Attribute REFCLK frequency = 400.00.⁽¹⁾

200.00

300.00

400.00

MHz

F_{IDELAYCTRL_REF}

IDELAYCTRL_REF_

PRECISION

REFCLK precision

±10

MHz

ns

T_{IDELAYCTRL_RPW}

Minimum reset pulse width.

59.28

IDELAY

T_{IDELAYRESOLUTION}IDELAY chain delay resolution.

1/(32 x 2 x F_REF

)

µs

Pattern dependent period jitter in delay chain for

clock pattern.⁽²⁾

ps

per tap

0

Pattern dependent period jitter in delay chain for

random data pattern (PRBS 23).⁽³⁾

ps

per tap

T_{IDELAYPAT_JIT}

±5

±9

±5

±9

±5

Pattern dependent period jitter in delay chain for

random data pattern (PRBS 23).⁽⁴⁾

ps

per tap

±9

T_{IDELAY_CLK_MAX}

Maximum frequency of CLK input to IDELAY.

680.00

600.00

MHz

T_{IDCCK_CE}

T_{IDCKC_CE}

T_{IDCCK_INC}

T_{IDCKC_INC}

T_{IDCCK_RST}

T_{IDCKC_RST}

/

CE pin setup/hold with respect to C for IDELAY. 0.16/0.13 0.21/0.16 0.21/0.16

INC pin setup/hold with respect to C for IDELAY. 0.14/0.18 0.16/0.22 0.16/0.22

RST pin setup/hold with respect to C for IDELAY. 0.16/0.11 0.18/0.14 0.18/0.14

ns

/

ns

/

ns

ps

T_{IDDO_IDATAIN}

Propagation delay through IDELAY.

Note 5

Notes:

1. Average tap delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps.

2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE.

3. When HIGH_PERFORMANCE mode is set to TRUE.

4. When HIGH_PERFORMANCE mode is set to FALSE.

5. Delay depends on IDELAY tap setting. See the timing report for actual values.

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28

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 26: IO_FIFO Switching Characteristics

Symbol

V_CCINTOperating Voltage and Speed

Grade

Description

Units

1.0V

0.95V

-1L

-2

-1

IO_FIFO Clock to Out Delays

T_{OFFCKO_DO}

T_{CKO_FLAGS}

Setup/Hold

T_{CCK_D}/T_{CKC_D}

RDCLK to Q outputs.

0.60

0.61

0.68

0.77

0.68

0.77

ns

Clock to IO_FIFO flags.

D inputs to WRCLK.

WREN to WRCLK.

0.51/0.02 0.58/0.02 0.58/0.02

0.47/–0.01 0.53/–0.01 0.53/–0.01

ns

T_{IFFCCK_WREN}

T_{IFFCKC_WREN}

T_{OFFCCK_RDEN}

T_{OFFCKC_RDEN}

/

RDEN to RDCLK.

0.58/0.02 0.66/0.02 0.66/0.02

ns

Minimum Pulse Width

T_{PWH_IO_FIFO}

RESET, RDCLK, WRCLK.

2.15

ns

T_{PWL_IO_FIFO}

Maximum Frequency

F_MAX

RDCLK and WRCLK.

200.00

MHz

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Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

CLB Switching Characteristics

Table 27: CLB Switching Characteristics

V_CCINTOperating Voltage and Speed

Grade

Units

Symbol

Description

1.0V

0.95V

-1L

-2

-1

Combinatorial Delays

T_ILO

An – Dn LUT address to A.

0.11

0.30

0.46

1.05

0.69

0.66

0.68

0.75

0.57

0.69

0.48

0.59

0.58

0.13

0.36

0.55

1.27

0.84

0.83

0.82

0.90

0.69

0.82

0.58

0.71

0.70

0.13

0.36

0.55

1.27

0.84

0.83

0.82

0.90

0.69

0.82

0.58

0.71

0.70

ns, Max

T_{ILO_2}

T_{ILO_3}

T_ITO

An – Dn LUT address to AMUX/CMUX.

An – Dn LUT address to BMUX_A.

An – Dn inputs to A – D Q outputs.

AX inputs to AMUX output.

AX inputs to BMUX output.

AX inputs to CMUX output.

AX inputs to DMUX output.

BX inputs to BMUX output.

BX inputs to DMUX output.

CX inputs to CMUX output.

CX inputs to DMUX output.

DX inputs to DMUX output.

T_AXA

T_AXB

T_AXC

T_AXD

T_BXB

T_BXD

T_CXC

T_CXD

T_DXD

Sequential Delays

T_CKO

Clock to AQ – DQ outputs.

Clock to AMUX – DMUX outputs.

0.44

0.53

0.66

0.53

0.66

ns, Max

T_SHCKO

Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK

T_AS/T_AH

AN – DN input to CLK on A – D flip-flops.

AX – DX input to CLK on A – D flip-flops.

0.09/0.14 0.11/0.18 0.11/0.18 ns, Min

0.07/0.21 0.09/0.26 0.09/0.26 ns, Min

T

_DICK/T_CKDI

AX – DX input through MUXs and/or carry logic to

CLK on A – D flip-flops.

0.66/0.09 0.81/0.11 0.81/0.11 ns, Min

T_{CECK_CLB}

T_{CKCE_CLB}

/

CE input to CLK on A – D flip-flops.

0.17/0.00 0.21/0.01 0.21/0.01 ns, Min

0.43/0.04 0.53/0.05 0.53/0.05 ns, Min

T

_SRCK/T_CKSRSR input to CLK on A – D flip-flops.

Set/Reset

T_SRMIN

T_RQ

SR input minimum pulse width.

0.78

0.59

0.58

1286

1.04

0.71

0.70

1098

1.04

0.71

0.70

1098

ns, Min

ns, Max

MHz

Delay from SR input to AQ – DQ flip-flops.

Delay from CE input to AQ – DQ flip-flops.

Toggle frequency (for export control).

T_CEO

F_TOG

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30

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

CLB Distributed RAM Switching Characteristics (SLICEM Only)

Table 28: CLB Distributed RAM Switching Characteristics

V_CCINTOperating Voltage and

Speed Grade

Symbol

Description

Units

1.0V

0.95V

-1L

-2

-1

Sequential Delays

T_SHCKO

Clock to A – B outputs.

Clock to AMUX – BMUX outputs.

1.09

1.53

1.32

1.86

1.32

1.86

ns, Max

T_{SHCKO_1}

Setup and Hold Times Before/After Clock CLK

T_{DS_LRAM}/T_{DH_LRAM}

T_{AS_LRAM}/T_{AH_LRAM}

T_{WS_LRAM}/T_{WH_LRAM}

A – D inputs to CLK.

0.60/0.30 0.72/0.35 0.72/0.35 ns, Min

0.30/0.60 0.37/0.70 0.37/0.70 ns, Min

Address An inputs to clock.

Address An inputs through MUXs and/or

carry logic to clock.

0.77/0.21 0.94/0.26 0.94/0.26 ns, Min

WE input to clock.

0.43/0.12 0.53/0.17 0.53/0.17 ns, Min

0.44/0.11 0.53/0.17 0.53/0.17 ns, Min

T

_{CECK_LRAM}/T_{CKCE_LRAM}CE input to CLK.

Clock CLK

T_{MPW_LRAM}

T_MCP

Minimum pulse width.

Minimum clock period.

1.13

2.26

1.25

2.50

1.25

2.50

ns, Min

Notes:

1.

T

also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path.

SHCKO

CLB Shift Register Switching Characteristics (SLICEM Only)

Table 29: CLB Shift Register Switching Characteristics

V_CCINTOperating Voltage and

Speed Grade

Symbol

Description

Units

1.0V

0.95V

-1L

-2

-1

Sequential Delays

T_REG

Clock to A – D outputs.

1.33

1.77

1.23

1.61

2.15

1.46

1.61

2.15

1.46

ns, Max

T_{REG_MUX}

T_{REG_M31}

Clock to AMUX – DMUX output.

Clock to DMUX output via M31 output.

Setup and Hold Times Before/After Clock CLK

T_{WS_SHFREG}/ T_{WH_SHFREG}

T_{CECK_SHFREG}

T_{CKCE_SHFREG}

_{DS_SHFREG}/ T_{DH_SHFREG}

WE input.

0.41/0.12 0.51/0.17 0.51/0.17 ns, Min

0.42/0.11 0.52/0.17 0.52/0.17 ns, Min

0.37/0.37 0.44/0.43 0.44/0.43 ns, Min

/

CE input to CLK.

A – D inputs to CLK.

T

Clock CLK

T_{MPW_SHFREG}

Minimum pulse width.

0.86

0.98

ns, Min

DS189 (v1.8) September 28, 2018

Product Specification

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31

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Block RAM and FIFO Switching Characteristics

Table 30: Block RAM and FIFO Switching Characteristics

V_CCINTOperating Voltage and Speed

Grade

Symbol

Description

Units

1.0V

0.95V

-1L

-2

-1

Block RAM and FIFO Clock-to-Out Delays

Clock CLK to DOUT output (without

output register).⁽¹⁾⁽²⁾

2.13

0.74

3.04

0.81

2.88

1.28

2.46

0.89

3.84

0.94

3.30

1.46

2.46

0.89

3.84

0.94

3.30

1.46

ns, Max

T_{RCKO_DO}and

T_{RCKO_DO_REG}

Clock CLK to DOUT output (with output

register).⁽³⁾⁽⁴⁾

Clock CLK to DOUT output with ECC

(without output register).⁽¹⁾⁽²⁾

T_{RCKO_DO_ECC}and

T_{RCKO_DO_ECC_REG}

Clock CLK to DOUT output with ECC

(with output register).⁽³⁾⁽⁴⁾

Clock CLK to DOUT output with cascade

(without output register).⁽¹⁾

_{RCKO_DO_CASCOUT}and

T

T_{RCKO_DO_CASCOUT_REG}

Clock CLK to DOUT output with cascade

(with output register).⁽³⁾

T_{RCKO_FLAGS}

Clock CLK to FIFO flags outputs.⁽⁵⁾

Clock CLK to FIFO pointers outputs.⁽⁶⁾

0.87

1.02

1.05

1.15

1.05

1.15

ns, Max

T_{RCKO_POINTERS}

Clock CLK to ECCPARITY in ECC encode

only mode.

T_{RCKO_PARITY_ECC}

0.85

2.81

0.76

0.88

0.93

0.94

3.55

0.89

1.07

1.08

0.94

3.55

0.89

1.07

1.08

ns, Max

Clock CLK to BITERR (without output

register).

T_{RCKO_SDBIT_ECC}and

T_{RCKO_SDBIT_ECC_REG}

Clock CLK to BITERR (with output

register).

Clock CLK to RDADDR output with ECC

(without output register).

T_{RCKO_RDADDR_ECC}and

T_{RCKO_RDADDR_ECC_REG}

Clock CLK to RDADDR output with ECC

(with output register).

Setup and Hold Times Before/After Clock CLK

T_{RCCK_ADDRA}

T_{RCKC_ADDRA}

/

ADDR inputs.⁽⁷⁾

0.49/0.33 0.57/0.36 0.57/0.36 ns, Min

0.65/0.63 0.74/0.67 0.74/0.67 ns, Min

Data input setup/hold time when block

RAM is configured in WRITE_FIRST or

NO_CHANGE mode.⁽⁸⁾

T_{RDCK_DI_WF_NC}

T_{RCKD_DI_WF_NC}

/

Data input setup/hold time when block

RAM is configured in READ_FIRST

mode.⁽⁸⁾

T_{RDCK_DI_RF}

T_{RCKD_DI_RF}

/

0.22/0.34 0.25/0.41 0.25/0.41 ns, Min

T_{RDCK_DI_ECC}

T_{RCKD_DI_ECC}

T_{RDCK_DI_ECCW}

T_{RCKD_DI_ECCW}

/

DIN inputs with block RAM ECC in

standard mode.⁽⁸⁾

0.55/0.46 0.63/0.50 0.63/0.50 ns, Min

1.02/0.46 1.17/0.50 1.17/0.50 ns, Min

/

DIN inputs with block RAM ECC encode

only.⁽⁸⁾

DS189 (v1.8) September 28, 2018

Product Specification

www.xilinx.com

32

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 30: Block RAM and FIFO Switching Characteristics (Cont’d)

V

_CCINTOperating Voltage and Speed

Grade

Symbol

Description

Units

1.0V

0.95V

-1L

-2

-1

T_{RDCK_DI_ECC_FIFO}

T_{RCKD_DI_ECC_FIFO}

T_{RCCK_INJECTBITERR}

T_{RCKC_INJECTBITERR}

T_{RCCK_EN}/T_{RCKC_EN}

T_{RCCK_REGCE}

T_{RCKC_REGCE}

T_{RCCK_RSTREG}

T_{RCKC_RSTREG}

T_{RCCK_RSTRAM}

T_{RCKC_RSTRAM}

/

DIN inputs with FIFO ECC in standard

mode.⁽⁸⁾

1.15/0.59 1.32/0.64 1.32/0.64 ns, Min

/

Inject single/double bit error in ECC

mode.

0.64/0.37 0.74/0.40 0.74/0.40 ns, Min

0.39/0.21 0.45/0.23 0.45/0.23 ns, Min

0.29/0.15 0.36/0.16 0.36/0.16 ns, Min

Block RAM enable (EN) input.

/

CE input of output register.

/

Synchronous RSTREG input.

Synchronous RSTRAM input.

0.32/0.07 0.35/0.07 0.35/0.07 ns, Min

0.34/0.43 0.36/0.46 0.36/0.46 ns, Min

0.48/0.19 0.54/0.20 0.54/0.20 ns, Min

0.46/0.35 0.47/0.43 0.47/0.43 ns, Min

0.43/0.35 0.43/0.43 0.43/0.43 ns, Min

/

Write enable (WE) input (block RAM

only).

T_{RCCK_WEA}/T_{RCKC_WEA}

T_{RCCK_WREN}

T_{RCKC_WREN}

T_{RCCK_RDEN}

T_{RCKC_RDEN}

/

WREN FIFO inputs.

RDEN FIFO inputs.

/

Reset Delays

T_{RCO_FLAGS}

Reset RST to FIFO flags/pointers.⁽⁹⁾

0.98

1.10

ns, Max

FIFO reset recovery and removal

timing.⁽¹⁰⁾

T

_{RREC_RST}/T_{RREM_RST}

2.07/–0.81 2.37/–0.81 2.37/–0.81 ns, Max

Maximum Frequency

Block RAM (write first and no change

modes) when not in SDP RF mode.

F_{MAX_BRAM_WF_NC}

460.83

388.20

MHz

Block RAM (read first, performance

mode) when in SDP RF mode but no

address overlap between port A and

port B.

F_{MAX_BRAM_RF_}

PERFORMANCE

Block RAM (read first, delayed write

mode) when in SDP RF mode and there

is possibility of overlap between port A

and port B addresses.

F_{MAX_BRAM_RF_}

404.53

418.59

339.67

345.78

339.67

345.78

MHz

DELAYED_WRITE

Block RAM cascade (write first, no

change mode) when cascade but not in

RF mode.

F_{MAX_CAS_WF_NC}

Block RAM cascade (read first,

F_{MAX_CAS_RF_}

performance mode) when in cascade

with RF mode and no possibility of

address overlap/one port is disabled.

PERFORMANCE

DS189 (v1.8) September 28, 2018

Product Specification

www.xilinx.com

33

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 30: Block RAM and FIFO Switching Characteristics (Cont’d)

V

_CCINTOperating Voltage and Speed

Grade

Symbol

Description

Units

1.0V

0.95V

-1L

-2

-1

When in cascade RF mode and there is a

possibility of address overlap between

port A and port B.

F_{MAX_CAS_RF_}

362.19

297.35

MHz

DELAYED_WRITE

F_{MAX_FIFO}

FIFO in all modes without ECC.

460.83

365.10

388.20

297.53

388.20

297.53

MHz

Block RAM and FIFO in ECC

configuration.

F_{MAX_ECC}

Notes:

1.

2. These parameters also apply to synchronous FIFO with DO_REG = 0.

3. includes T as well as the B port equivalent timing parameters.

4. These parameters also apply to multi-rate (asynchronous) and synchronous FIFO with DO_REG = 1.

T

includes T

, T

, and T

as well as the B port equivalent timing parameters.

RCKO_DOR

RCKO_DOW RCKO_DOPR

RCKO_DOPW

T

RCKO_DO

RCKO_DOP

5.

6.

T

includes the following parameters: T

, T

.

RCKO_FLAGS

RCKO_AEMPTY RCKO_AFULL RCKO_EMPTY RCKO_FULL RCKO_RDERR RCKO_WRERR

includes both T

and T

.

RCKO_POINTERS

RCKO_RDCOUNT

RCKO_WRCOUNT

7. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible.

8. These parameters include both A and B inputs as well as the parity inputs of A and B.

9.

T

includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.

RCO_FLAGS

10. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the

slowest clock (WRCLK or RDCLK).

DS189 (v1.8) September 28, 2018

Product Specification

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34

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics

DSP48E1 Switching Characteristics

Table 31: DSP48E1 Switching Characteristics

V_CCINTOperating

Voltage and Speed

Grade

Symbol

Description

Units

1.0V

0.95V

-1L

-2

-1

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