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产品型号XC95144XL-10TQG100C的概述

--- XC95144XL-10TQG100C 芯片概述 XC95144XL-10TQG100C 是 Xilinx 公司在 CPLD（Complex Programmable Logic Device，复杂可编程逻辑器件）系列中推出的一款高性能芯片。该芯片以其可编程性和灵活性，广泛应用于数码电路设计、系统加速、信号处理等领域。XC95144XL 系列是 Xilinx 的 CPLD 产品线之一，旨在提供高性能和低功耗的解决方案，适用于各种嵌入式系统和数据处理应用。 1. 基本功能 XC95144XL-10TQG100C 芯片具备以下几个基本功能： - 可编程逻辑单元（PLU）：提供丰富的逻辑单元供设计者进行组合，支持逻辑门、触发器和更复杂的逻辑结构。 - 输入/输出引脚：通过灵活的配置，可以实现多种输入输出功能。 - 快速响应时间：适合高频信号处理，能够在短时间内完成逻辑运算。 2. ...

产品型号XC95144XL-10TQG100C的Datasheet PDF文件预览

XC95144XL High Performance

CPLD

DS056 (v2.0) April 3, 2007

Product Specification

54V18 Function Blocks, providing 3,200 usable gates with

propagation delays of 5 ns. See Figure 2 for overview.

Features

•

5 ns pin-to-pin logic delays

Power Estimation

System frequency up to 178 MHz

144 macrocells with 3,200 usable gates

Available in small footprint packages

Power dissipation in CPLDs can vary substantially depend-

ing on the system frequency, design application and output

loading. To help reduce power dissipation, each macrocell

in a XC9500XL device may be configured for low-power

mode (from the default high-performance mode). In addi-

tion, unused product-terms and macrocells are automati-

cally deactivated by the software to further conserve power.

100-pin TQFP (81 user I/O pins)

144-pin TQFP (117 user I/O pins)

144-CSP (117 user I/O pins)

Pb-free available for all packages

•

Optimized for high-performance 3.3V systems

Low power operation

5V tolerant I/O pins accept 5V, 3.3V, and 2.5V

signals

For a general estimate of I_CC, the following equation may be

used:

_CC(mA) = MC_HS(0.175*PT_HS+ 0.345) + MC_LP(0.052*PT_LP

+ 0.272) + 0.04 * MC_TOG(MC_HS+MC_LP)* f

3.3V or 2.5V output capability

Advanced 0.35 micron feature size CMOS

Fast FLASH™ technology

where:

MC_HS= # macrocells in high-speed configuration

PT_HS= average number of high-speed product terms

per macrocell

MC_LP= # macrocells in low power configuration

PT_LP= average number of low power product terms per

macrocell

f = maximum clock frequency

MCTOG = average % of flip-flops toggling per clock

(~12%)

Advanced system features

In-system programmable

Superior pin-locking and routability with

Fast CONNECT™ II switch matrix

Extra wide 54-input Function Blocks

Up to 90 product-terms per macrocell with

individual product-term allocation

Local clock inversion with three global and one

product-term clocks

Individual output enable per output pin with local

inversion

Input hysteresis on all user and boundary-scan pin

inputs

This calculation was derived from laboratory measurements

of an XC9500XL part filled with 16-bit counters and allowing

a single output (the LSB) to be enabled. The actual I_CC

value varies with the design application and should be veri-

fied during normal system operation. Figure 1 shows the

above estimation in a graphical form. For a more detailed

discussion of power consumption in this device, see Xilinx

Bus-hold circuitry on all user pin inputs

Full IEEE Standard 1149.1 boundary-scan (JTAG)

•

Fast concurrent programming

Slew rate control on individual outputs

Enhanced data security features

Excellent quality and reliability

Endurance exceeding 10,000 program/erase

cycles

20 year data retention

ESD protection exceeding 2,000V

•

Pin-compatible with 5V-core XC95144 device in the

100-pin TQFP package

WARNING: Programming temperature range of

T_A= 0° C to +70° C

Description

The XC95144XL is a 3.3V CPLD targeted for high-perfor-

mance, low-voltage applications in leading-edge communi-

cations and computing systems. It is comprised of eight

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS056 (v2.0) April 3, 2007

www.xilinx.com

Product Specification

XC95144XL High Performance CPLD

application note XAPP114, “Understanding XC9500XL

CPLD Power.”

250

178 MHz

200

150

104 MHz

100

Clock Frequency (MHz)

200

150

Figure 1: Typical I_CCvs. Frequency for XC95144XL

www.xilinx.com

DS056 (v2.0) April 3, 2007

Product Specification

XC95144XL High Performance CPLD

JTAG

In-System Programming Controller

JTAG Port

Controller

Function

Block 1

I/O

Macrocells

1 to 18

I/O

Function

Block 2

Macrocells

1 to 18

I/O

Blocks

I/O

Function

Block 3

Macrocells

1 to 18

I/O

I/O/GCK

I/O/GSR

I/O/GTS

Function

Block 4

Macrocells

1 to 18

Function

Block 8

Macrocells

1 to 18

DS056_02_101300

Figure 2: XC95144XL Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

DS056 (v2.0) April 3, 2007

www.xilinx.com

Product Specification

XC95144XL High Performance CPLD

(2)

Absolute Maximum Ratings

Symbol

Description

Value

–0.5 to 4.0

–0.5 to 5.5

–65 to +150

+150

Units

V_CC

V_IN

Supply voltage relative to GND

Input voltage relative to GND⁽¹⁾

Voltage applied to 3-state output⁽¹⁾

Storage temperature (ambient)⁽³⁾

Junction temperature

V_TS

T_STG

T_J

^oC

Notes:

1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the

device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the

forcing current being limited to 200 mA. External I/O voltage may not exceed V_CCINTby 4.0V.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions

is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free

packages, see XAPP427.

Recommended Operation Conditions

Symbol

Parameter

Supply voltage for internal logic

and input buffers

Min

3.0

2.3

Max

3.6

Units

V_CCINT

Commercial T_A= 0^oC to 70^oC

Industrial T_A= –40^oC to +85^oC

3.6

V_CCIO

Supply voltage for output drivers for 3.3V operation

Supply voltage for output drivers for 2.5V operation

Low-level input voltage

3.6

2.7

V_IL

V_IH

V_O

0.80

5.5

High-level input voltage

2.0

Output voltage

V_CCIO

Quality and Reliability Characteristics

Symbol

Parameter

Min

Max

Units

T_DR

Data Retention

Years

Cycles

Volts

N_PE

Program/Erase Cycles (Endurance)

Electrostatic Discharge (ESD)

10,000

2,000

V_ESD

DC Characteristic Over Recommended Operating Conditions

Symbol

Parameter

Test Conditions

I_OH= –4.0 mA

_OH= –500 μA

I_OL= 8.0 mA

_OL= 500 μA

Min

Max

Units

V_OH

Output high voltage for 3.3V outputs

Output high voltage for 2.5V outputs

Output low voltage for 3.3V outputs

Output low voltage for 2.5V outputs

Input leakage current

2.4

90% V_CCIO

V_OL

0.4

±10

I_IL

V_CC= Max; V_IN= GND or V_CC

μA

I_IH

I/O high-Z leakage current

www.xilinx.com

DS056 (v2.0) April 3, 2007

Product Specification

XC95144XL High Performance CPLD

Symbol

Parameter

Test Conditions

Min

Max

Units

I_IH

I/O high-Z leakage current

V_CC= Max; V_CCIO= Max;

±10

μA

V_IN= GND or 3.6V

_CCMin < V_IN< 5.5V

±50

μA

C_IN

I_CC

I/O capacitance

V_IN= GND; f = 1.0 MHz

Operating supply current

(low power mode, active)

V_IN= GND, No load; f = 1.0 MHz

45 (Typical)

AC Characteristics

XC95144XL-5

XC95144XL-7

XC95144XL-10

Symbol

Parameter

Min

Max

5.0

Min

Max

7.5

Min

Max

10.0

Units

T_PD

T_SU

T_H

I/O to output valid

I/O setup time before GCK

I/O hold time after GCK

GCK to output valid

3.7

4.8

6.5

T_CO

3.5

178.6

4.5

125.0

5.8

100.0

f_SYSTEMMultiple FB internal operating frequency

MHz

T_PSU

T_PH

I/O setup time before p-term clock input

I/O hold time after p-term clock input

P-term clock output valid

1.7

1.6

2.1

2.0

3.2

4.4

T_PCO

T_OE

5.5

4.0

7.0

10.0

10.5

7.7

5.0

9.5

12.0

12.6

10.2

7.0

11.0

14.5

15.3

GTS to output valid

T_OD

GTS to output disable

T_POE

T_POD

T_AO

Product term OE to output enabled

Product term OE to output disabled

GSR to output valid

T_PAO

T_WLH

P-term S/R to output valid

GCK pulse width (High or Low)

2.8

5.0

4.0

6.5

4.5

7.0

T_APRPWAsynchronous preset/reset pulse width

(High or Low)

T_PLH

P-term clock pulse width (High or Low)

5.0

6.5

7.0

TEST

Output Type

CCIO

TEST

Device Output

3.3V

2.5V

320 Ω

250 Ω

360 Ω

660 Ω

35 pF

2.5V

DS058_03_081500

Figure 3: AC Load Circuit

DS056 (v2.0) April 3, 2007

www.xilinx.com

Product Specification

XC95144XL High Performance CPLD

Internal Timing Parameters

XC95144XL-5

XC95144XL-7

XC95144XL-10

Symbol

Parameter

Min

Max

Min

Max

Min

Max

Units

Buffer Delays

T_IN

Input buffer delay

GCK buffer delay

1.5

1.1

2.0

4.0

2.0

2.3

1.5

3.1

5.0

2.5

3.5

1.8

4.5

7.0

3.0

T_GCK

T_GSR

T_GTS

T_OUT

T_EN

GSR buffer delay

GTS buffer delay

Output buffer delay

Output buffer enable/disable

delay

Product Term Control Delays

T_PTCKProduct term clock delay

T_PTSRProduct term set/reset delay

1.6

1.0

5.5

2.4

1.4

7.2

2.7

1.8

7.5

T_PTTS

Product term 3-state delay

Internal Register and Combinatorial Delays

T_PDI

T_SUI

T_HI

Combinatorial logic propagation delay

2.3

1.4

2.3

1.4

0.5

2.6

2.2

2.6

2.2

1.3

3.0

3.5

3.0

3.5

1.7

T_ECSURegister clock enable setup time

T_ECHORegister clock enable hold time

T_COI

T_AOI

Internal logic delay

0.4

6.0

0.5

6.4

1.0

7.0

T_RAI

5.0

7.5

10.0

T_LOGI

1.0

5.0

1.4

6.4

1.8

7.3

T_LOGILPInternal low power logic delay

Feedback Delays

T_F

Fast CONNECT II feedback delay

1.9

3.5

4.2

Time Adders

T_PTA

Incremental product term allocator delay

0.7

3.0

0.8

4.0

1.0

4.5

T_SLEWSlew-rate limited delay

www.xilinx.com

DS056 (v2.0) April 3, 2007

Product Specification

XC95144XL High Performance CPLD

(2)

XC95144XL I/O Pins

Function Macro-

BScan

TQ100 TQ144 CS144 Order

Function Macro-

BScan

Block

cell

Block

cell

TQ100 TQ144 CS144 Order

429

426

423

420

417

414

411

408

405

402

399

396

393

390

387

384

381

378

375

372

369

366

363

360

357

354

351

348

345

342

339

336

333

330

327

324

23⁽¹⁾

32⁽¹⁾

L1⁽¹⁾

N2⁽¹⁾

321

318

315

312

309

306

303

300

297

294

291

288

285

282

279

276

273

270

267

264

261

258

255

252

249

246

243

240

237

234

231

228

225

222

219

216

2⁽¹⁾

27⁽¹⁾

8⁽¹⁾

38⁽¹⁾

17⁽¹⁾

30⁽¹⁾

K2⁽¹⁾

22⁽¹⁾

142

143⁽¹⁾

A2⁽¹⁾

118

126

133

2⁽¹⁾

99⁽¹⁾

B1⁽¹⁾

C2⁽¹⁾

5⁽¹⁾

6⁽¹⁾

1⁽¹⁾

2⁽¹⁾

3⁽¹⁾

4⁽¹⁾

2⁽¹⁾

3⁽¹⁾

5⁽¹⁾

6⁽¹⁾

128

129

8⁽¹⁾

9⁽¹⁾

D4⁽¹⁾

D3⁽¹⁾

130

131

135

132

134

137

136

138

139

140

Notes:

1. Global control pin.

2. The pin-outs are the same for Pb-free versions of packages.

DS056 (v2.0) April 3, 2007

www.xilinx.com

Product Specification

XC95144XL High Performance CPLD

XC95144XL (Continued)

Function Macro-

BScan

TQ100 TQ144 CS144 Order

Function Macro-

BScan

Block

cell

Block

cell

TQ100 TQ144 CS144 Order

213

210

207

204

201

198

195

192

189

186

183

180

177

174

171

168

165

162

159

156

153

150

147

144

141

138

135

132

129

126

123

120

117

114

111

108

105

102

N12

L12

M10

N11

L11

M13

L13

K10

K11

K13

K12

J11

H10

J10

H11

H12

J12

H13

–-

M11

106

C11

G11

F11

E13

G10

F13

111

110

112

B11

A12

A11

113

116

115

119

120

D10

A10

B10

101

100

103

102

104

107

105

F12

F10

D13

E12

E10

D11

D12

C13

B13

C12

121

124

117

125

Notes:

1. The pin-outs are the same for Pb-free versions of packages.

www.xilinx.com

DS056 (v2.0) April 3, 2007

Product Specification

XC95144XL High Performance CPLD

(1)

XC95144XL Global, JTAG and Power Pins

Pin Type

I/O/GCK1

I/O/GCK2

I/O/GCK3

I/O/GTS1

I/O/GTS2

I/O/GTS3

I/O/GTS4

I/O/GSR

TCK

TQ100

TQ144

CS144

143

122

L10

TDI

TDO

N10

TMS

_CCINT3.3V

_CCIO2.5V/3.3V

GND

5, 57, 98

26, 38, 51, 88

8, 42, 84, 141

B3, D1, J13, L4

A1, A13, C7, L7, N1, N13

1, 37, 55, 73, 109, 127

21, 31, 44, 62, 69, 75, 84, 100 18, 29, 36, 47, 62, 72, 89, 90, 99, B2, B8, B12, C10, E11, G1, G12,

108, 114, 123, 144

G13, K1, M2, M5, M9, M12

No Connects

–

Notes:

1. The pin-outs are the same for Pb-free versions of packages.

DS056 (v2.0) April 3, 2007

www.xilinx.com

Product Specification

XC95144XL High Performance CPLD

Device Part Marking and Ordering Combination Information.

Device Type

Package

XC95xxxXL

TQ144

This line not

related to device

part number

Speed

Operating Range

Sample package with part marking.

Speed

Device Ordering and

(pin-to-pin

delay)

Pkg.

Symbol

No. of

Pins

Operating

Range⁽¹⁾

Part Marking Number

XC95144XL-5TQ100C

XC95144XL-5TQ144C

XC95144XL-5CS144C

XC95144XL-7TQ100C

XC95144XL-7TQ144C

XC95144XL-7CS144C

XC95144XL-7TQ100I

XC95144XL-7TQ144I

XC95144XL-7CS144I

XC95144XL-10TQ100C

XC95144XL-10TQ144C

XC95144XL-10CS144C

XC95144XL-10TQ100I

XC95144XL-10TQ144I

XC95144XL-10CS144I

XC95144XL-5TQG100C

XC95144XL-5TQG144C

XC95144XL-5CSG144C

XC95144XL-7TQG100C

XC95144XL-7TQG144C

XC95144XL-7CSG144C

XC95144XL-7TQG100I

XC95144XL-7TQG144I

XC95144XL-7CSG144I

Package Type

5 ns

TQ100 100-pin

TQ144 144-pin

CS144 144-ball

TQ100 100-pin

TQ144 144-pin

CS144 144-ball

TQ100 100-pin

TQ144 144-pin

CS144 144-ball

TQ100 100-pin

TQ144 144-pin

CS144 144-ball

TQ100 100-pin

TQ144 144-pin

CS144 144-ball

TQG100 100-pin

TQG144 144-pin

CSG144 144-ball

TQG100 100-pin

TQG144 144-pin

CSG144 144-ball

TQG100 100-pin

TQG144 144-pin

CSG144 144-ball

Thin Quad Flat Pack (TQFP)

5 ns

Chip Scale Package (CSP)

7.5 ns

10 ns

5 ns

Thin Quad Flat Pack (TQFP)

Chip Scale Package (CSP)

Thin Quad Flat Pack (TQFP)

Chip Scale Package (CSP)

Thin Quad Flat Pack (TQFP)

Chip Scale Package (CSP)

Thin Quad Flat Pack (TQFP)

Chip Scale Package (CSP)

Thin Quad Flat Pack (TQFP); Pb-free

Chip Scale Package (CSP); Pb-free

Thin Quad Flat Pack (TQFP); Pb-free

Chip Scale Package (CSP); Pb-free

Thin Quad Flat Pack (TQFP); Pb-free

Chip Scale Package (CSP); Pb-free

5 ns

7.5 ns

www.xilinx.com

DS056 (v2.0) April 3, 2007

Product Specification

XC95144XL High Performance CPLD

Operating

Speed

(pin-to-pin

delay)

Device Ordering and

Part Marking Number

Pkg.

Symbol

No. of

Pins

Package Type

Range⁽¹⁾

XC95144XL-10TQG100C

XC95144XL-10TQG144C

XC95144XL-10CSG144C

XC95144XL-10TQG100I

XC95144XL-10TQG144I

XC95144XL-10CSG144I

Notes:

10 ns

TQG100 100-pin

TQG144 144-pin

CSG144 144-ball

TQG100 100-pin

TQG144 144-pin

CSG144 144-ball

Thin Quad Flat Pack (TQFP); Pb-free

Chip Scale Package (CSP); Pb-free

Thin Quad Flat Pack (TQFP); Pb-free

Chip Scale Package (CSP); Pb-free

1. C = Commercial: T_A= 0° to +70°C; I = Industrial: T_A= –40° to +85°C

Pb-

-4 TQ

144

XC95144XL

Free Example:

Standard Example: XC95144XL -4 TQ 144

Device

Speed Grade

Package Type

Speed Grade

Package Type

Number of Pins

Temperature Range

-Free

Number of Pins

Temperature Range

Warranty Disclaimer

THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED

AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE

PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE

THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE

AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF

LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO

APPLICABLE LAWS AND REGULATIONS.

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XC95144XL-10TQG100C产品参数

型号:	XC95144XL-10TQG100C
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	QFP
包装说明：	LFQFP, QFP100,.63SQ,20
针数：	100
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	12 weeks
风险等级：	0.93
其他特性：	YES
系统内可编程：	YES
JESD-30 代码：	S-PQFP-G100
JESD-609代码：	e3
JTAG BST：	YES
长度：	14 mm
湿度敏感等级：	3
专用输入次数：
I/O 线路数量：	81
宏单元数：	144
端子数量：	100
最高工作温度：	70 °C
最低工作温度：
组织：	0 DEDICATED INPUTS, 81 I/O
输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP
封装等效代码：	QFP100,.63SQ,20
封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260
电源：	2.5/3.3,3.3 V
可编程逻辑类型：	FLASH PLD
传播延迟：	10 ns
认证状态：	Not Qualified
座面最大高度：	1.6 mm
子类别：	Programmable Logic Devices
最大供电电压：	3.6 V
最小供电电压：	3 V
标称供电电压：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	30
宽度：	14 mm
Base Number Matches：	1

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