XC95144XL-5TQ144C中文资料应用文章市场行情现货热卖使用介绍-中国IC网-芯三七

0

R

XC95144XL High Performance

CPLD

0

5

DS056 (v1.5) August 21, 2003

Preliminary Product Specification

Features

Power Estimation

Power dissipation in CPLDs can vary substantially depend-

ing on the system frequency, design application and output

loading. To help reduce power dissipation, each macrocell

in a XC9500XL device may be configured for low-power

mode (from the default high-performance mode). In addi-

tion, unused product-terms and macrocells are automati-

cally deactivated by the software to further conserve power.

•

5 ns pin-to-pin logic delays

System frequency up to 178 MHz

144 macrocells with 3,200 usable gates

Available in small footprint packages

-

100-pin TQFP (81 user I/O pins)

144-pin TQFP (117 user I/O pins)

144-CSP (117 user I/O pins)

For a general estimate of I , the following equation may be

•

Optimized for high-performance 3.3V systems

CC

used:

-

Low power operation

5V tolerant I/O pins accept 5V, 3.3V, and 2.5V

signals

I

(mA) = MC (0.175*PT + 0.345) + MC (0.052*PT

CC

HS HS LP LP

+ 0.272) + 0.04 * MC

(MC +MC )* f

TOG

HS

LP

where:

-

3.3V or 2.5V output capability

Advanced 0.35 micron feature size CMOS

Fast FLASH™ technology

MC = # macrocells in high-speed configuration

HS

PT = average number of high-speed product terms

HS

Advanced system features

per macrocell

-

In-system programmable

MC = # macrocells in low power configuration

LP

Superior pin-locking and routability with

Fast CONNECT™ II switch matrix

Extra wide 54-input Function Blocks

Up to 90 product-terms per macrocell with

individual product-term allocation

Local clock inversion with three global and one

product-term clocks

Individual output enable per output pin with local

inversion

Input hysteresis on all user and boundary-scan pin

inputs

PT = average number of low power product terms per

LP

macrocell

f = maximum clock frequency

MCTOG = average % of flip-flops toggling per clock

(~12%)

-

This calculation was derived from laboratory measurements

of an XC9500XL part filled with 16-bit counters and allowing

a single output (the LSB) to be enabled. The actual I

value varies with the design application and should be veri-

fied during normal system operation. Figure 1 shows the

above estimation in a graphical form. For a more detailed

discussion of power consumption in this device, see Xilinx

application note XAPP114, “Understanding XC9500XL

CPLD Power.”

CC

-

Bus-hold circuitry on all user pin inputs

Full IEEE Standard 1149.1 boundary-scan (JTAG)

•

Fast concurrent programming

Slew rate control on individual outputs

Enhanced data security features

Excellent quality and reliability

250

178 MHz

200

-

Endurance exceeding 10,000 program/erase

cycles

-

20 year data retention

ESD protection exceeding 2,000V

150

104 MHz

•

Pin-compatible with 5V-core XC95144 device in the

100-pin TQFP package

100

50

0

Description

The XC95144XL is a 3.3V CPLD targeted for high-perfor-

mance, low-voltage applications in leading-edge communi-

cations and computing systems. It is comprised of eight

54V18 Function Blocks, providing 3,200 usable gates with

propagation delays of 5 ns. See Figure 2 for architecture

overview.

100

Clock Frequency (MHz)

200

50

150

DS056_01_121501

Figure 1: Typical I vs. Frequency for XC95144XL

CC

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS056 (v1.5) August 21, 2003

www.xilinx.com

1

Preliminary Product Specification

1-800-255-7778

R

XC95144XL High Performance CPLD

3

JTAG

In-System Programming Controller

1

JTAG Port

Controller

54

Function

18

Block 1

I/O

Macrocells

1 to 18

I/O

54

Function

Block 2

Macrocells

1 to 18

I/O

Blocks

I/O

Function

Block 3

Macrocells

1 to 18

I/O

3

I/O/GCK

I/O/GSR

I/O/GTS

Function

Block 4

1

4

Macrocells

1 to 18

54

Function

Block 8

18

Macrocells

1 to 18

DS056_02_101300

Figure 2: XC95144XL Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

2

www.xilinx.com

DS056 (v1.5) August 21, 2003

1-800-255-7778

Preliminary Product Specification

R

XC95144XL High Performance CPLD

Absolute Maximum Ratings

Symbol

Description

Value

–0.5 to 4.0

–0.5 to 5.5

–65 to +150

+220

Units

V

Supply voltage relative to GND

V

CC

(1)

V

Input voltage relative to GND

IN

(1)

V

Voltage applied to 3-state output

Storage temperature (ambient)

TS

o

T

C

STG

SOL

o

Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)

Junction temperature

C

o

T

+150

C

J

Notes:

1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the

device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the

forcing current being limited to 200 mA.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions

is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Recommended Operation Conditions

Symbol

Parameter

Min

3.0

2.3

0

Max

3.6

Units

o

V

Supply voltage for internal logic

and input buffers

Commercial T = 0 C to 70 C

V

CCINT

A

o

Industrial T = –40 C to +85 C

3.6

A

V

Supply voltage for output drivers for 3.3V operation

Supply voltage for output drivers for 2.5V operation

Low-level input voltage

3.6

CCIO

2.7

V

0.80

5.5

IL

V

High-level input voltage

2.0

0

IH

V

Output voltage

V

CCIO

O

Quality and Reliability Characteristics

Symbol

Parameter

Min

20

Max

Units

T

Data Retention

-

Years

Cycles

Volts

DR

N

Program/Erase Cycles (Endurance)

Electrostatic Discharge (ESD)

10,000

2,000

PE

V

ESD

DC Characteristic Over Recommended Operating Conditions

Symbol

Parameter

Test Conditions

Min

Max

Units

V

Output high voltage for 3.3V outputs

Output high voltage for 2.5V outputs

Output low voltage for 3.3V outputs

Output low voltage for 2.5V outputs

Input leakage current

I

= –4.0 mA

2.4

-

OH

OL

= –500 µA

= 8.0 mA

= 500 µA

90% V

-

V

CCIO

V

-

0.4

±10

V

OL

V

I

V

= Max; V = GND or V

µA

IL

CC

IN

CC

I

I/O high-Z leakage current

= Max; V = GND or V

IN

IH

I/O high-Z leakage current

V

= Max; V

= Max;

CCIO

= GND or 3.6V

IN

V

Min < V < 5.5V

-

±50

10

µA

pF

CC

IN

C

I/O capacitance

= GND; f = 1.0 MHz

-

IN

I

Operating supply current

(low power mode, active)

= GND, No load; f = 1.0 MHz

45 (Typical)

mA

CC

DS056 (v1.5) August 21, 2003

www.xilinx.com

3

Preliminary Product Specification

1-800-255-7778

R

XC95144XL High Performance CPLD

AC Characteristics

XC95144XL-5

XC95144XL-7

XC95144XL-10

Symbol

Parameter

I/O to output valid

Min

Max

5.0

-

Min

Max

7.5

-

Min

Max

10.0

-

Units

ns

T

-

PD

SU

I/O setup time before GCK

I/O hold time after GCK

3.7

4.8

6.5

ns

T

0

-

0

-

0

-

ns

H

T

GCK to output valid

-

3.5

178.6

-

4.5

125.0

-

5.8

100.0

-

ns

CO

f

Multiple FB internal operating frequency

I/O setup time before p-term clock input

I/O hold time after p-term clock input

P-term clock output valid

-

MHz

ns

SYSTEM

T

1.7

1.6

2.1

PSU

T

2.0

-

3.2

-

4.4

-

ns

PH

T

-

5.5

4.0

7.0

10.0

10.5

-

7.7

5.0

9.5

12.0

12.6

-

10.2

7.0

11.0

14.5

15.3

-

ns

PCO

T

GTS to output valid

-

ns

OE

T

GTS to output disable

-

ns

OD

T

Product term OE to output enabled

Product term OE to output disabled

GSR to output valid

-

ns

POE

POD

ns

T

-

ns

AO

T

P-term S/R to output valid

-

ns

PAO

WLH

T

GCK pulse width (High or Low)

P-term clock pulse width (High or Low)

2.8

5.0

4.0

6.5

4.5

7.0

ns

T

-

ns

PLH

V

TEST

R

1

Output Type

V

R

1

R

2

C

L

CCIO

TEST

Device Output

3.3V

2.5V

320 Ω

250 Ω

360 Ω

660 Ω

35 pF

2.5V

C

L

R

2

DS058_03_081500

Figure 3: AC Load Circuit

4

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DS056 (v1.5) August 21, 2003

1-800-255-7778

Preliminary Product Specification

R

XC95144XL High Performance CPLD

Internal Timing Parameters

XC95144XL-5

XC95144XL-7

XC95144XL-10

Symbol

Parameter

Min

Max

Min

Max

Min

Max

Units

Buffer Delays

T

Input buffer delay

-

1.5

1.1

2.0

4.0

2.0

0

-

2.3

1.5

3.1

5.0

2.5

0

-

3.5

1.8

4.5

7.0

3.0

0

ns

IN

T

GCK buffer delay

GSR buffer delay

GTS buffer delay

Output buffer delay

GCK

GSR

GTS

OUT

T

Output buffer enable/disable

delay

EN

Product Term Control Delays

T

Product term clock delay

Product term set/reset delay

Product term 3-state delay

-

1.6

1.0

5.5

-

2.4

1.4

7.2

-

2.7

1.8

7.5

ns

PTCK

PTSR

PTTS

Internal Register and Combinatorial Delays

T

Combinatorial logic propagation delay

Register setup time

-

2.3

1.4

2.3

1.4

-

0.5

-

2.6

2.2

2.6

2.2

-

1.3

-

3.0

3.5

3.0

3.5

-

1.7

ns

PDI

SUI

-

T

Register hold time

HI

T

Register clock enable setup time

Register clock enable hold time

Register clock to output valid time

Register async. S/R to output delay

Register async. S/R recover before clock

Internal logic delay

-

ECSU

ECHO

-

T

0.4

6.0

0.5

6.4

1.0

7.0

COI

T

-

AOI

T

5.0

-

7.5

-

10.0

-

RAI

T

1.0

5.0

1.4

6.4

1.8

7.3

LOGI

T

Internal low power logic delay

-

LOGILP

Feedback Delays

Fast CONNECT II feedback delay

Time Adders

T

-

1.9

-

3.5

-

4.2

ns

F

T

Incremental product term allocator delay

Slew-rate limited delay

-

0.7

3.0

-

0.8

4.0

-

1.0

4.5

ns

PTA

T

SLEW

DS056 (v1.5) August 21, 2003

www.xilinx.com

5

Preliminary Product Specification

1-800-255-7778

R

XC95144XL High Performance CPLD

XC95144XL I/O Pins

Function Macro-

BScan

TQ100 TQ144 CS144 Order

Function Macro-

BScan

Block

cell

Block

cell

TQ100 TQ144 CS144 Order

1

-

23

16

17

25

19

20

-

H3

F1

G2

J1

G3

G4

-

429

426

423

420

417

414

411

408

405

402

399

396

393

390

387

384

381

378

375

372

369

366

363

360

357

354

351

348

345

342

339

336

333

330

327

324

3

1

-

39

M3

321

318

315

312

309

306

303

300

297

294

291

288

285

282

279

276

273

270

267

264

261

258

255

252

249

246

243

240

237

234

231

228

225

222

219

216

(1)

1

2

11

12

-

3

2

23

32

L1

1

3

4

5

6

7

-

41

44

33

34

46

K4

N4

L2

L3

L5

1

4

3

1

5

13

14

-

3

24

25

-

1

6

3

1

7

3

(1)

1

8

15

16

-

21

22

31

24

26

-

H1

H2

K3

H4

J2

-

3

8

27

38

N2

1

9

3

9

28

-

40

48

N3

N5

M4

K5

-

1

10

11

12

13

14

15

16

3

10

11

12

13

14

15

16

17

18

1

17

18

-

3

29

30

-

43

1

3

45

1

3

-

1

19

20

-

27

28

35

J3

J4

M1

3

32

33

-

49

K6

L6

-

1

3

50

1

3

-

(1)

1

17

22

30

K2

3

34

-

51

M6

-

1

18

1

-

3

-

2

142

C3

4

-

118

126

133

-

C9

A7

A5

-

(1)

2

99

143

A2

4

2

87

-

2

3

4

-

4

3

2

-

(1)

4

C1

4

-

(1)

2

5

1

2

B1

C2

-

4

5

89

90

-

128

129

-

D7

A6

-

(1)

2

6

3

4

6

2

7

-

(1)

-

4

7

(1)

2

8

3

4

5

6

D4

D3

4

8

91

92

-

130

131

135

132

134

137

136

138

139

140

-

B6

C6

C5

D6

B5

A4

D5

B4

C4

A3

-

(1)

2

9

4

9

2

10

11

12

13

14

15

16

17

18

-

7

D2

4

10

11

12

13

14

15

16

17

18

2

6

7

-

9

E4

E3

E1

E2

F4

F3

F2

-

4

93

94

-

2

10

12

11

13

14

15

-

4

2

4

2

8

9

-

4

95

96

-

2

4

2

4

2

10

-

4

97

-

2

4

Notes:

1. Global control pin.

6

www.xilinx.com

1-800-255-7778

DS056 (v1.5) August 21, 2003

Preliminary Product Specification

R

XC95144XL High Performance CPLD

XC95144XL (Continued)

Function

Block

Macro-

cell

BScan

Function Macro-

BScan

TQ100 TQ144 CS144 Order

Block

cell

TQ100 TQ144 CS144 Order

5

6

1

2

-

35

-

N6

L8

213

210

207

204

201

198

195

192

189

186

183

180

177

174

171

168

165

162

159

156

153

150

147

144

141

138

135

132

129

126

123

120

117

114

111

108

7

1

-

50

-

71

75

-

105

102

99

96

93

90

87

84

81

78

75

72

69

66

63

60

57

54

51

48

45

42

39

36

33

30

27

24

21

18

15

12

9

52

59

-

7

2

N12

L12

-

3

7

3

4

-

7

4

-

5

36

37

-

53

54

66

56

57

68

58

60

70

61

64

-

M7

N7

M10

K7

N8

N11

M8

K8

L11

N9

K9

-

7

5

52

53

-

74

76

77

78

80

79

82

85

81

86

87

83

88

-

M13

L13

K10

K11

K13

K12

J11

H10

J10

H11

H12

J12

H13

-

6

7

6

7

8

39

40

–-

41

42

-

7

8

54

55

-

9

7

9

10

11

12

13

14

15

16

17

18

1

7

10

11

12

13

14

15

16

17

18

1

7

56

58

-

7

43

46

-

7

59

60

-

7

49

-

69

-

M11

-

7

61

-

7

-

8

-

2

74

-

106

-

C11

-

8

2

63

-

91

95

97

92

93

-

G11

F11

E13

G10

F13

-

3

8

3

4

-

111

110

112

-

B11

A12

A11

-

8

4

-

5

76

77

-

8

5

64

65

-

6

8

6

7

8

7

8

78

79

-

113

116

115

119

120

-

D10

A10

B10

B9

A9

-

8

66

67

-

94

96

101

98

100

103

102

104

107

105

-

F12

F10

D13

E12

E10

D11

D12

C13

B13

C12

-

9

8

9

10

11

12

13

14

15

16

17

18

8

10

11

12

13

14

15

16

17

18

80

81

-

8

68

70

-

8

82

85

-

121

124

117

125

-

D8

A8

D9

B7

-

8

71

72

-

8

6

86

-

8

73

-

3

8

0

DS056 (v1.5) August 21, 2003

www.xilinx.com

7

Preliminary Product Specification

1-800-255-7778

R

XC95144XL High Performance CPLD

XC95144XL Global, JTAG and Power Pins

Pin Type

I/O/GCK1

I/O/GCK2

I/O/GCK3

I/O/GTS1

I/O/GTS2

I/O/GTS3

I/O/GTS4

I/O/GSR

TCK

TQ100

TQ144

CS144

22

30

K2

23

32

L1

27

38

N2

3

5

D4

4

6

D3

1

2

B1

2

3

C2

99

143

A2

48

67

L10

TDI

45

83

63

L9

TDO

122

65

C8

N10

TMS

47

V_CCINT3.3V

V_CCIO2.5V/3.3V

GND

5, 57, 98

26, 38, 51, 88

8, 42, 84, 141

1, 37, 55, 73, 109, 127

B3, D1, J13, L4

A1, A13, C7, L7, N1, N13

21, 31, 44, 62, 69, 75, 84, 100 18, 29, 36, 47, 62, 72, 89, 90, 99,

108, 114, 123, 144

B2, B8, B12, C10, E11, G1,

G12, G13, K1, M2, M5, M9, M12

No Connects

-

–

8

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DS056 (v1.5) August 21, 2003

1-800-255-7778

Preliminary Product Specification

R

XC95144XL High Performance CPLD

Device Part Marking and Ordering Combination Information

R

Device Type

Package

XC95xxxXL

TQ144

This line not

related to device

part number

Speed

7C

Operating Range

1

Sample package with part marking.

Speed

Device Ordering and

(pin-to-pin

delay)

Pkg.

Symbol

No. of

Pins

Operating

Range

(1)

Part Marking Number

XC95144XL-5TQ100C

XC95144XL-5TQ144C

XC95144XL-5CS144C

XC95144XL-7TQ100C

XC95144XL-7TQ144C

XC95144XL-7CS144C

XC95144XL-7TQ100I

XC95144XL-7TQ144I

XC95144XL-7CS144I

XC95144XL-10TQ100C

XC95144XL-10TQ144C

XC95144XL-10CS144C

XC95144XL-10TQ100I

XC95144XL-10TQ144I

XC95144XL-10CS144I

Notes:

Package Type

5 ns

TQ100 100-pin

TQ144 144-pin

CS144 144-ball

TQ100 100-pin

TQ144 144-pin

CS144 144-ball

TQ100 100-pin

TQ144 144-pin

CS144 144-ball

TQ100 100-pin

TQ144 144-pin

CS144 144-ball

TQ100 100-pin

TQ144 144-pin

CS144 144-ball

Thin Quad Flat Pack (TQFP)

Chip Scale Package (CSP)

Thin Quad Flat Pack (TQFP)

Chip Scale Package (CSP)

Thin Quad Flat Pack (TQFP)

Chip Scale Package (CSP)

Thin Quad Flat Pack (TQFP)

Chip Scale Package (CSP)

Thin Quad Flat Pack (TQFP)

Chip Scale Package (CSP)

C

I

5 ns

7.5 ns

10 ns

I

C

I

1. C = Commercial: T = 0° to +70°C; I = Industrial: T = –40° to +85°C

A

DS056 (v1.5) August 21, 2003

www.xilinx.com

9

Preliminary Product Specification

1-800-255-7778

R

XC95144XL High Performance CPLD

Revision History

The following table shows the revision history for this document.

Date

Version

1.1

Revision

10/30/98

11/13/98

06/20/02

Minor corrections to CS144 pinout table.

V1.2 minor correction in CS144 pinout table.

Updated I_CCequation, page 1. Updated DC Characteristics: I to 45 (typical). Updated

1.2

1.3

CC

Component Availability chart.Added additional I test conditions and measurements to DC

IH

Characteristics table.

o

06/20/03

08/21/03

1.4

1.5

Updated T

from 260 to 220 C. Added Part Marking and updated Ordering Information.

SOL

Updated Package Device Marking Pin 1 orientation.

10

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Preliminary Product Specification

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