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产品型号XC95144XL的概述

XC95144XL芯片概述 XC95144XL是一种来自Xilinx公司的复杂可编程逻辑设备（CPLD），属于XC9500系列。这款芯片是专为实现灵活和可重新配置的数字逻辑设计而设计的，广泛应用于各类电子产品中。XC95144XL通过其兼具高性能与低功耗的特点，适应了现代数字系统对于更加复杂逻辑功能的需求。CPLD产品因其可以在没有硬件更改的情况下重新编程，能够迅速适应市场变化，从而极大提高了产品的可用性和寿命。 Xilinx的XC95144XL芯片采用了先进的处理工艺与结构设计，支持动态重配置和并行操作，使得设备在执行复杂的逻辑操作时能够实现更高的效率。同时，它还向设计师提供了灵活的开发环境，可通过VHDL或Verilog来进行逻辑设计。 XC95144XL的详细参数 XC95144XL的主要技术参数如下： - 逻辑单元数量：最多144个逻辑单元，每个逻辑单元都可以执行复杂的逻辑功能...

产品型号XC95144XL的Datasheet PDF文件预览

XC95144XL High Performance

CPLD

DS056 (v1.5) August 21, 2003

Preliminary Product Specification

Features

Power Estimation

Power dissipation in CPLDs can vary substantially depend-

ing on the system frequency, design application and output

loading. To help reduce power dissipation, each macrocell

in a XC9500XL device may be configured for low-power

mode (from the default high-performance mode). In addi-

tion, unused product-terms and macrocells are automati-

cally deactivated by the software to further conserve power.

•

5 ns pin-to-pin logic delays

System frequency up to 178 MHz

144 macrocells with 3,200 usable gates

Available in small footprint packages

100-pin TQFP (81 user I/O pins)

144-pin TQFP (117 user I/O pins)

144-CSP (117 user I/O pins)

For a general estimate of I , the following equation may be

•

Optimized for high-performance 3.3V systems

used:

Low power operation

5V tolerant I/O pins accept 5V, 3.3V, and 2.5V

signals

(mA) = MC (0.175*PT + 0.345) + MC (0.052*PT

HS HS LP LP

+ 0.272) + 0.04 * MC

(MC +MC )* f

TOG

where:

3.3V or 2.5V output capability

Advanced 0.35 micron feature size CMOS

Fast FLASH™ technology

MC = # macrocells in high-speed configuration

PT = average number of high-speed product terms

Advanced system features

per macrocell

In-system programmable

MC = # macrocells in low power configuration

Superior pin-locking and routability with

Fast CONNECT™ II switch matrix

Extra wide 54-input Function Blocks

Up to 90 product-terms per macrocell with

individual product-term allocation

Local clock inversion with three global and one

product-term clocks

Individual output enable per output pin with local

inversion

Input hysteresis on all user and boundary-scan pin

inputs

PT = average number of low power product terms per

macrocell

f = maximum clock frequency

MCTOG = average % of flip-flops toggling per clock

(~12%)

This calculation was derived from laboratory measurements

of an XC9500XL part filled with 16-bit counters and allowing

a single output (the LSB) to be enabled. The actual I

value varies with the design application and should be veri-

fied during normal system operation. Figure 1 shows the

above estimation in a graphical form. For a more detailed

discussion of power consumption in this device, see Xilinx

application note XAPP114, “Understanding XC9500XL

CPLD Power.”

Bus-hold circuitry on all user pin inputs

Full IEEE Standard 1149.1 boundary-scan (JTAG)

•

Fast concurrent programming

Slew rate control on individual outputs

Enhanced data security features

Excellent quality and reliability

250

178 MHz

200

Endurance exceeding 10,000 program/erase

cycles

20 year data retention

ESD protection exceeding 2,000V

150

104 MHz

•

Pin-compatible with 5V-core XC95144 device in the

100-pin TQFP package

100

Description

The XC95144XL is a 3.3V CPLD targeted for high-perfor-

mance, low-voltage applications in leading-edge communi-

cations and computing systems. It is comprised of eight

54V18 Function Blocks, providing 3,200 usable gates with

propagation delays of 5 ns. See Figure 2 for architecture

overview.

100

Clock Frequency (MHz)

200

150

DS056_01_121501

Figure 1: Typical I vs. Frequency for XC95144XL

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS056 (v1.5) August 21, 2003

www.xilinx.com

Preliminary Product Specification

1-800-255-7778

XC95144XL High Performance CPLD

JTAG

In-System Programming Controller

JTAG Port

Controller

Function

Block 1

I/O

Macrocells

1 to 18

I/O

Function

Block 2

Macrocells

1 to 18

I/O

Blocks

I/O

Function

Block 3

Macrocells

1 to 18

I/O

I/O/GCK

I/O/GSR

I/O/GTS

Function

Block 4

Macrocells

1 to 18

Function

Block 8

Macrocells

1 to 18

DS056_02_101300

Figure 2: XC95144XL Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

www.xilinx.com

DS056 (v1.5) August 21, 2003

1-800-255-7778

Preliminary Product Specification

XC95144XL High Performance CPLD

Absolute Maximum Ratings

Symbol

Description

Value

–0.5 to 4.0

–0.5 to 5.5

–65 to +150

+220

Units

Supply voltage relative to GND

(1)

Input voltage relative to GND

(1)

Voltage applied to 3-state output

Storage temperature (ambient)

STG

SOL

Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)

Junction temperature

+150

Notes:

1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the

device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the

forcing current being limited to 200 mA.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions

is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Recommended Operation Conditions

Symbol

Parameter

Min

3.0

2.3

Max

3.6

Units

Supply voltage for internal logic

and input buffers

Commercial T = 0 C to 70 C

CCINT

Industrial T = –40 C to +85 C

3.6

Supply voltage for output drivers for 3.3V operation

Supply voltage for output drivers for 2.5V operation

Low-level input voltage

3.6

CCIO

2.7

0.80

5.5

High-level input voltage

2.0

Output voltage

CCIO

Quality and Reliability Characteristics

Symbol

Parameter

Min

Max

Units

Data Retention

Years

Cycles

Volts

Program/Erase Cycles (Endurance)

Electrostatic Discharge (ESD)

10,000

2,000

ESD

DC Characteristic Over Recommended Operating Conditions

Symbol

Parameter

Test Conditions

Min

Max

Units

Output high voltage for 3.3V outputs

Output high voltage for 2.5V outputs

Output low voltage for 3.3V outputs

Output low voltage for 2.5V outputs

Input leakage current

= –4.0 mA

2.4

= –500 µA

= 8.0 mA

= 500 µA

90% V

CCIO

0.4

±10

= Max; V = GND or V

µA

I/O high-Z leakage current

= Max; V = GND or V

I/O high-Z leakage current

= Max; V

= Max;

CCIO

= GND or 3.6V

Min < V < 5.5V

±50

µA

I/O capacitance

= GND; f = 1.0 MHz

Operating supply current

(low power mode, active)

= GND, No load; f = 1.0 MHz

45 (Typical)

DS056 (v1.5) August 21, 2003

www.xilinx.com

Preliminary Product Specification

1-800-255-7778

XC95144XL High Performance CPLD

AC Characteristics

XC95144XL-5

XC95144XL-7

XC95144XL-10

Symbol

Parameter

I/O to output valid

Min

Max

5.0

Min

Max

7.5

Min

Max

10.0

Units

I/O setup time before GCK

I/O hold time after GCK

3.7

4.8

6.5

GCK to output valid

3.5

178.6

4.5

125.0

5.8

100.0

Multiple FB internal operating frequency

I/O setup time before p-term clock input

I/O hold time after p-term clock input

P-term clock output valid

MHz

SYSTEM

1.7

1.6

2.1

PSU

2.0

3.2

4.4

5.5

4.0

7.0

10.0

10.5

7.7

5.0

9.5

12.0

12.6

10.2

7.0

11.0

14.5

15.3

PCO

GTS to output valid

GTS to output disable

Product term OE to output enabled

Product term OE to output disabled

GSR to output valid

POE

POD

P-term S/R to output valid

PAO

WLH

GCK pulse width (High or Low)

P-term clock pulse width (High or Low)

2.8

5.0

4.0

6.5

4.5

7.0

PLH

TEST

Output Type

CCIO

TEST

Device Output

3.3V

2.5V

320 Ω

250 Ω

360 Ω

660 Ω

35 pF

2.5V

DS058_03_081500

Figure 3: AC Load Circuit

www.xilinx.com

DS056 (v1.5) August 21, 2003

1-800-255-7778

Preliminary Product Specification

XC95144XL High Performance CPLD

Internal Timing Parameters

XC95144XL-5

XC95144XL-7

XC95144XL-10

Symbol

Parameter

Min

Max

Min

Max

Min

Max

Units

Buffer Delays

Input buffer delay

1.5

1.1

2.0

4.0

2.0

2.3

1.5

3.1

5.0

2.5

3.5

1.8

4.5

7.0

3.0

GCK buffer delay

GSR buffer delay

GTS buffer delay

Output buffer delay

GCK

GSR

GTS

OUT

Output buffer enable/disable

delay

Product Term Control Delays

Product term clock delay

Product term set/reset delay

Product term 3-state delay

1.6

1.0

5.5

2.4

1.4

7.2

2.7

1.8

7.5

PTCK

PTSR

PTTS

Internal Register and Combinatorial Delays

Combinatorial logic propagation delay

2.3

1.4

2.3

1.4

0.5

2.6

2.2

2.6

2.2

1.3

3.0

3.5

3.0

3.5

1.7

PDI

SUI

Internal logic delay

ECSU

ECHO

0.4

6.0

0.5

6.4

1.0

7.0

COI

AOI

5.0

7.5

10.0

RAI

1.0

5.0

1.4

6.4

1.8

7.3

LOGI

Internal low power logic delay

LOGILP

Feedback Delays

Fast CONNECT II feedback delay

Time Adders

1.9

3.5

4.2

Incremental product term allocator delay

Slew-rate limited delay

0.7

3.0

0.8

4.0

1.0

4.5

PTA

SLEW

DS056 (v1.5) August 21, 2003

www.xilinx.com

Preliminary Product Specification

1-800-255-7778

XC95144XL High Performance CPLD

XC95144XL I/O Pins

Function Macro-

BScan

TQ100 TQ144 CS144 Order

Function Macro-

BScan

Block

cell

Block

cell

TQ100 TQ144 CS144 Order

429

426

423

420

417

414

411

408

405

402

399

396

393

390

387

384

381

378

375

372

369

366

363

360

357

354

351

348

345

342

339

336

333

330

327

324

321

318

315

312

309

306

303

300

297

294

291

288

285

282

279

276

273

270

267

264

261

258

255

252

249

246

243

240

237

234

231

228

225

222

219

216

(1)

142

118

126

133

(1)

143

(1)

128

129

(1)

130

131

135

132

134

137

136

138

139

140

(1)

Notes:

1. Global control pin.

www.xilinx.com

1-800-255-7778

DS056 (v1.5) August 21, 2003

Preliminary Product Specification

XC95144XL High Performance CPLD

XC95144XL (Continued)

Function

Block

Macro-

cell

BScan

Function Macro-

BScan

TQ100 TQ144 CS144 Order

Block

cell

TQ100 TQ144 CS144 Order

213

210

207

204

201

198

195

192

189

186

183

180

177

174

171

168

165

162

159

156

153

150

147

144

141

138

135

132

129

126

123

120

117

114

111

108

105

102

N12

L12

M10

N11

L11

M13

L13

K10

K11

K13

K12

J11

H10

J10

H11

H12

J12

H13

–-

M11

106

C11

G11

F11

E13

G10

F13

111

110

112

B11

A12

A11

113

116

115

119

120

D10

A10

B10

101

100

103

102

104

107

105

F12

F10

D13

E12

E10

D11

D12

C13

B13

C12

121

124

117

125

DS056 (v1.5) August 21, 2003

www.xilinx.com

Preliminary Product Specification

1-800-255-7778

XC95144XL High Performance CPLD

XC95144XL Global, JTAG and Power Pins

Pin Type

I/O/GCK1

I/O/GCK2

I/O/GCK3

I/O/GTS1

I/O/GTS2

I/O/GTS3

I/O/GTS4

I/O/GSR

TCK

TQ100

TQ144

CS144

143

L10

TDI

TDO

122

N10

TMS

V_CCINT3.3V

V_CCIO2.5V/3.3V

GND

5, 57, 98

26, 38, 51, 88

8, 42, 84, 141

1, 37, 55, 73, 109, 127

B3, D1, J13, L4

A1, A13, C7, L7, N1, N13

21, 31, 44, 62, 69, 75, 84, 100 18, 29, 36, 47, 62, 72, 89, 90, 99,

108, 114, 123, 144

B2, B8, B12, C10, E11, G1,

G12, G13, K1, M2, M5, M9, M12

No Connects

–

www.xilinx.com

DS056 (v1.5) August 21, 2003

1-800-255-7778

Preliminary Product Specification

XC95144XL High Performance CPLD

Device Part Marking and Ordering Combination Information

Device Type

Package

XC95xxxXL

TQ144

This line not

related to device

part number

Speed

Operating Range

Sample package with part marking.

Speed

Device Ordering and

(pin-to-pin

delay)

Pkg.

Symbol

No. of

Pins

Operating

Range

(1)

Part Marking Number

XC95144XL-5TQ100C

XC95144XL-5TQ144C

XC95144XL-5CS144C

XC95144XL-7TQ100C

XC95144XL-7TQ144C

XC95144XL-7CS144C

XC95144XL-7TQ100I

XC95144XL-7TQ144I

XC95144XL-7CS144I

XC95144XL-10TQ100C

XC95144XL-10TQ144C

XC95144XL-10CS144C

XC95144XL-10TQ100I

XC95144XL-10TQ144I

XC95144XL-10CS144I

Notes:

Package Type

5 ns

TQ100 100-pin

TQ144 144-pin

CS144 144-ball

TQ100 100-pin

TQ144 144-pin

CS144 144-ball

TQ100 100-pin

TQ144 144-pin

CS144 144-ball

TQ100 100-pin

TQ144 144-pin

CS144 144-ball

TQ100 100-pin

TQ144 144-pin

CS144 144-ball

Thin Quad Flat Pack (TQFP)

Chip Scale Package (CSP)

Thin Quad Flat Pack (TQFP)

Chip Scale Package (CSP)

Thin Quad Flat Pack (TQFP)

Chip Scale Package (CSP)

Thin Quad Flat Pack (TQFP)

Chip Scale Package (CSP)

Thin Quad Flat Pack (TQFP)

Chip Scale Package (CSP)

5 ns

7.5 ns

10 ns

1. C = Commercial: T = 0° to +70°C; I = Industrial: T = –40° to +85°C

DS056 (v1.5) August 21, 2003

www.xilinx.com

Preliminary Product Specification

1-800-255-7778

XC95144XL High Performance CPLD

Revision History

The following table shows the revision history for this document.

Date

Version

1.1

Revision

10/30/98

11/13/98

06/20/02

Minor corrections to CS144 pinout table.

V1.2 minor correction in CS144 pinout table.

Updated I_CCequation, page 1. Updated DC Characteristics: I to 45 (typical). Updated

1.2

1.3

Component Availability chart.Added additional I test conditions and measurements to DC

Characteristics table.

06/20/03

08/21/03

1.4

1.5

Updated T

from 260 to 220 C. Added Part Marking and updated Ordering Information.

SOL

Updated Package Device Marking Pin 1 orientation.

www.xilinx.com

DS056 (v1.5) August 21, 2003

1-800-255-7778

Preliminary Product Specification

XC95144XL相关文章

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XC95144XL-10CS144C产品参数

型号:	XC95144XL-10CS144C
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Active
IHS 制造商：	XILINX INC
零件包装代码：	BGA
包装说明：	TFBGA, BGA144,13X13,32
针数：	144
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	12 weeks
风险等级：	5.17
其他特性：	YES
系统内可编程：	YES
JESD-30 代码：	S-PBGA-B144
JESD-609代码：	e0
JTAG BST：	YES
长度：	12 mm
湿度敏感等级：	3
专用输入次数：
I/O 线路数量：	117
宏单元数：	144
端子数量：	144
最高工作温度：	70 °C
最低工作温度：
组织：	0 DEDICATED INPUTS, 117 I/O
输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY
封装代码：	TFBGA
封装等效代码：	BGA144,13X13,32
封装形状：	SQUARE
封装形式：	GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	240
电源：	2.5/3.3,3.3 V
可编程逻辑类型：	FLASH PLD
传播延迟：	10 ns
认证状态：	Not Qualified
座面最大高度：	1.2 mm
子类别：	Programmable Logic Devices
最大供电电压：	3.6 V
最小供电电压：	3 V
标称供电电压：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn63Pb37)
端子形式：	BALL
端子节距：	0.8 mm
端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30
宽度：	12 mm
Base Number Matches：	1

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