XC95288XL-7PQ208C中文资料应用文章市场行情现货热卖使用介绍-中国IC网-芯三七

0

R

XC95288XL High Performance

CPLD

0

5

DS055 (v2.1 April 3, 2007

Product Specification

cations and computing systems. It is comprised of 16

54V18 Function Blocks, providing 6,400 usable gates with

propagation delays of 6 ns. See Figure 2 for architecture

overview.

Features

•

6 ns pin-to-pin logic delays

System frequency up to 208 MHz

288 macrocells with 6,400 usable gates

Available in small footprint packages

Power Estimation

-

144-pin TQFP (117 user I/O pins)

208-pin PQFP (168 user I/O pins)

256-pin BGA (192 user I/O pins)

256-pin FBGA (192 user I/O pins)

280-pin CSP (192 user I/O pins)

Pb-free available for all packages

Power dissipation in CPLDs can vary substantially depend-

ing on the system frequency, design application and output

loading. To help reduce power dissipation, each macrocell

in a XC9500XL device may be configured for low-power

mode (from the default high-performance mode). In addi-

tion, unused product-terms and macrocells are automati-

cally deactivated by the software to further conserve power.

•

Optimized for high-performance 3.3V systems

-

Low power operation

5V tolerant I/O pins accept 5V, 3.3V, and 2.5V

signals

For a general estimate of I_CC, the following equation may be

used:

I

_CC(mA) = MC_HS(0.175*PT_HS+ 0.345) + MC_LP(0.052*PT_LP

+ 0.272) + 0.04 * MC_TOG(MC_HS+MC_LP)* f

-

3.3V or 2.5V output capability

Advanced 0.35 micron feature size CMOS

Fast FLASH™ technology

where:

MC_HS= # macrocells in high-speed configuration

Advanced system features

PT_HS= average number of high-speed product terms

per macrocell

MC_LP= # macrocells in low power configuration

PT_LP= average number of low power product terms per

macrocell

f = maximum clock frequency

MCTOG = average % of flip-flops toggling per clock

(~12%)

-

In-system programmable

Superior pin-locking and routability with

Fast CONNECT™ II switch matrix

Extra wide 54-input Function Blocks

Up to 90 product-terms per macrocell with

individual product-term allocation

Local clock inversion with three global and one

product-term clocks

Individual output enable per output pin with local

inversion

Input hysteresis on all user and boundary-scan pin

inputs

-

This calculation was derived from laboratory measurements

of an XC9500XL part filled with 16-bit counters and allowing

a single output (the LSB) to be enabled. The actual I_CC

value varies with the design application and should be veri-

fied during normal system operation. Figure 1 shows the

above estimation in a graphical form. For a more detailed

discussion of power consumption in this device, see Xilinx

-

Bus-hold circuitry on all user pin inputs

Full IEEE Standard 1149.1 boundary-scan (JTAG)

•

Fast concurrent programming

Slew rate control on individual outputs

Enhanced data security features

Excellent quality and reliability

-

Endurance exceeding 10,000 program/erase

cycles

-

20 year data retention

ESD protection exceeding 2,000V

•

Pin-compatible with 5V-core XC95288 device in the

208-pin HQFP package

WARNING: Programming temperature range of

T_A= 0° C to +70° C

Description

The XC95288XL is a 3.3V CPLD targeted for high-perfor-

mance, low-voltage applications in leading-edge communi-

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS055 (v2.1 April 3, 2007

www.xilinx.com

1

Product Specification

1-800-255-7778

R

XC95288XL High Performance CPLD

application note XAPP114, “Understanding XC9500XL

CPLD Power.”

550

208 MHz

500

450

400

350

300

250

94 MHz

200

150

100

50

0

50

100

150

200

250

Clock Frequency (MHz)

DS055_01_121501

Figure 1: Typical I_CCvs. Frequency for XC95288XL

2

www.xilinx.com

1-800-255-7778

DS055 (v2.1 April 3, 2007

Product Specification

R

XC95288XL High Performance CPLD

3

JTAG

In-System Programming Controller

1

JTAG Port

Controller

54

Function

Block 1

18

I/O

Macrocells

1 to 18

I/O

Function

Block 2

Macrocells

1 to 18

I/O

Blocks

I/O

Function

Block 3

Macrocells

1 to 18

I/O

3

I/O/GCK

I/O/GSR

I/O/GTS

Function

Block 4

1

4

Macrocells

1 to 18

54

Function

Block 16

18

Macrocells

1 to 18

DS055_02_101300

Figure 2: XC95288XL Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

DS055 (v2.1 April 3, 2007

www.xilinx.com

3

Product Specification

1-800-255-7778

R

XC95288XL High Performance CPLD

(2)

Absolute Maximum Ratings

Symbol

Description

Value

–0.5 to 4.0

–0.5 to 5.5

–65 to +150

+150

Units

V

V_CC

V_IN

Supply voltage relative to GND

Input voltage relative to GND⁽¹⁾

Voltage applied to 3-state output⁽¹⁾

Storage temperature (ambient)⁽³⁾

Junction temperature

V

V_TS

T_STG

T_J

V

^oC

Notes:

1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the

device pins may undershoot to –2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the

forcing current being limited to 200 mA. External I/O voltage may not exceed V_CCINTby 4.0V.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions

is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free

packages, see XAPP427.

Recommended Operation Conditions

Symbol

Parameter

Supply voltage for internal logic

and input buffers

Min

3.0

2.3

0

Max

3.6

Units

V_CCINT

Commercial T_A= 0^oC to 70^oC

Industrial T_A= –40^oC to +85^oC

V

3.6

V_CCIO

Supply voltage for output drivers for 3.3V operation

Supply voltage for output drivers for 2.5V operation

Low-level input voltage

3.6

2.7

V_IL

V_IH

V_O

0.80

5.5

High-level input voltage

2.0

0

Output voltage

V_CCIO

Quality and Reliability Characteristics

Symbol

Parameter

Min

20

Max

Units

T_DR

Data Retention

-

Years

Cycles

Volts

N_PE

Program/Erase Cycles (Endurance)

Electrostatic Discharge (ESD)

10,000

2,000

V_ESD

DC Characteristic Over Recommended Operating Conditions

Symbol

Parameter

Test Conditions

I_OH= –4.0 mA

_OH= –500 μA

I_OL= 8.0 mA

_OL= 500 μA

V_CC= Max; V_IN= GND or V_CC

V_CC= Max; V_CCIO= Max;

Min

Max

Units

V

V_OH

Output high voltage for 3.3V outputs

Output high voltage for 2.5V outputs

Output low voltage for 3.3V outputs

Output low voltage for 2.5V outputs

Input leakage current

2.4

-

I

90% V_CCIO

-

V

V_OL

-

0.4

±10

V

I

V

I_IL

I_IH

μA

I/O high-Z leakage current

V_IN= GND or 3.6V

V

_CCMin < V_IN< 5.5V

-

±50

10

μA

pF

C_IN

I_CC

I/O capacitance

V_IN= GND; f = 1.0 MHz

Operating supply current

(low power mode, active)

V_IN= GND, No load; f = 1.0 MHz

85 (Typical)

mA

4

www.xilinx.com

DS055 (v2.1 April 3, 2007

1-800-255-7778

Product Specification

R

XC95288XL High Performance CPLD

AC Characteristics

XC95288XL-6

XC95288XL-7

XC95288XL-10

Symbol

Parameter

Min

Max

6.0

-

Min

Max

7.5

-

Min

Max

10.0

-

Units

ns

T_PD

T_SU

T_H

I/O to output valid

-

I/O setup time before GCK

I/O hold time after GCK

GCK to output valid

4.0

4.8

6.5

ns

0

-

0

-

0

-

ns

T_CO

-

3.8

208.3

-

4.5

125.0

-

5.8

100.0

-

ns

f_SYSTEMMultiple FB internal operating frequency

-

MHz

ns

T_PSU

T_PH

I/O setup time before p-term clock input

I/O hold time after p-term clock input

P-term clock output valid

1.0

1.6

2.1

2.6

-

3.2

-

4.4

-

ns

T_PCO

T_OE

-

6.8

4.5

8.4

10.8

11.8

-

7.7

5.0

9.5

12.0

12.6

-

10.2

7.0

11.0

14.5

15.3

-

ns

GTS to output valid

-

ns

T_OD

GTS to output disable

-

ns

T_POE

T_POD

T_AO

Product term OE to output enabled

Product term OE to output disabled

GSR to output valid

-

ns

-

ns

T_PAO

T_WLH

P-term S/R to output valid

-

ns

GCK pulse width (High or Low)

2.4

6.0

4.0

6.5

4.5

7.0

ns

T_APRPWAsynchronous preset/reset pulse width

(High or Low)

-

ns

T_PLH

P-term clock pulse width (High or Low)

6.0

-

6.5

-

7.0

-

ns

V

TEST

R

1

2

Output Type

V

R

C

L

CCIO

TEST

1

2

Device Output

3.3V

2.5V

320 Ω

250 Ω

360 Ω

660 Ω

35 pF

2.5V

C

L

R

DS058_03_081500

Figure 3: AC Load Circuit

DS055 (v2.1 April 3, 2007

www.xilinx.com

5

Product Specification

1-800-255-7778

R

XC95288XL High Performance CPLD

Internal Timing Parameters

XC95288XL-6

XC95288XL-7

XC95288XL-10

Symbol

Parameter

Min

Max

Min

Max

Min

Max

Units

Buffer Delays

T_IN

Input buffer delay

GCK buffer delay

-

2.2

1.2

2.2

4.5

2.4

0

-

2.3

1.5

3.1

5.0

2.5

0

-

3.5

1.8

4.5

7.0

3.0

0

ns

T_GCK

T_GSR

T_GTS

T_OUT

T_EN

GSR buffer delay

GTS buffer delay

Output buffer delay

Output buffer enable/disable

delay

Product Term Control Delays

T_PTCKProduct term clock delay

T_PTSRProduct term set/reset delay

-

2.0

1.0

6.2

-

2.4

1.4

7.2

-

2.7

1.8

7.5

ns

T_PTTS

Product term 3-state delay

Internal Register and Combinatorial Delays

T_PDI

T_SUI

T_HI

Combinatorial logic propagation delay

Register setup time

-

2.0

1.6

2.0

1.6

-

0.4

-

2.6

2.2

2.6

2.2

-

1.3

-

3.0

3.5

3.0

3.5

-

1.7

ns

-

Register hold time

T_ECSURegister clock enable setup time

T_ECHORegister clock enable hold time

-

T_COI

T_AOI

Register clock to output valid time

Register async. S/R to output delay

Register async. S/R recover before clock

Internal logic delay

0.2

6.2

0.5

6.4

1.0

7.0

-

T_RAI

6.0

-

7.5

-

10.0

-

T_LOGI

1.0

5.5

1.4

6.4

1.8

7.3

T_LOGILPInternal low power logic delay

-

Feedback Delays

T_F

Fast CONNECT II feedback delay

-

1.6

-

3.5

-

4.2

ns

Time Adders

T_PTA

Incremental product term allocator delay

(first incremental delay)

-

0.8

0.3

3.5

-

0.8

0.3

4.0

-

1.0

0.4

4.5

ns

T_PTA2

Incremental product term allocator delay

(subsequent incremental delay)

T_SLEWSlew-rate limited delay

6

www.xilinx.com

DS055 (v2.1 April 3, 2007

1-800-255-7778

Product Specification

R

XC95288XL High Performance CPLD

(2)

XC95288XL I/O Pins

Func-

tion Macro

Block cell

Func-

tion

Block

BScan

TQ144 PQ208 BG256 FG256 CS280 Order

Macro

cell

BScan

TQ144 PQ208 BG256 FG256 CS280 Order

1

2

–

28

29

–

L1

L2

–

H1

H5

–

K2

K3

–

861

858

855

852

849

846

843

840

837

834

831

828

825

822

819

816

813

810

807

804

801

798

795

792

789

786

783

780

777

774

771

768

765

762

759

756

3

4

1

2

–

28

–

38

39

–

L2

L5

–

753

750

747

744

741

738

735

732

729

P1

R1

–

N2

P1

–

1

3

–

3

1

4

–

4

–

1

5

20

21

–

30

31

–

L3

L4

–

J1

J5

–

K4

L1

–

5

–

40

41

–

P3

R2

–

M1

L4

–

P2

P3

–

1

6

–

1

7

–

1

8

22

–

32

–

M1

M2

M3

M4

N1

–

J2

J3

K1

J4

K2

–

L2

L3

L4

M1

M2

–

8

–

43

–

P4

R3

N1

L3

P4

R1

1

9

–

1

10

11

12

13

14

15

16

17

18

1

23

–

33

–

10

11

12

13

14

15

16

17

18

1

30⁽¹⁾44⁽¹⁾T2⁽¹⁾M2⁽¹⁾R3⁽¹⁾726

1

–

31

–

45

–

U1

T3

–

M4

P1

–

R2

R4

–

723

720

717

1

24

–

34

–

1

25

26

–

35

36

–

N2

N3

–

K5

L1

–

M3

M4

–

32⁽¹⁾46⁽¹⁾U2⁽¹⁾M3⁽¹⁾T1⁽¹⁾714

1

33

–

47

–

V1

–

N2

–

T2

–

711

708

705

702

699

1

27

–

37

–

N4

–

K3

–

N1

–

48

–

T4

–

N4

–

T3

–

1

–

2

–

2⁽¹⁾

–

2

9

15

16

–

G2

G1

–

D1

G4

–

G3

G2

–

2

3⁽¹⁾C2⁽¹⁾D3⁽¹⁾C2⁽¹⁾696

2

3

10

–

3

–

4

D2

–

D2

–

B1

–

693

690

2

4

–

3⁽¹⁾

–

2

5

11

12

–

17

18

–

H4

H3

–

E1

G3

–

G1

G4

–

5

5⁽¹⁾D3⁽¹⁾E3⁽¹⁾C1⁽¹⁾687

2

6

4

6

E4

–

C2

–

D4

–

684

681

2

7

–

5⁽¹⁾

–

2

8

13

–

19

–

H2

H1

J4

J3

J2

–

G2

F5

F1

G5

H2

–

H1

H3

H2

H4

J1

–

8

7⁽¹⁾C1⁽¹⁾D4⁽¹⁾D3⁽¹⁾678

2

9

–

8

D1

E3

E2

B1

E4

C1

D2

D1

E3

675

672

669

2

10

11

12

13

14

15

16

17

18

14

–

20

–

10

11

12

13

14

15

16

17

18

–

2

–

6⁽¹⁾

–

9⁽¹⁾

2

15

–

21

–

E1⁽¹⁾E5⁽¹⁾E2⁽¹⁾666

2

–

F3

F2

–

E2

F2

–

E4

F3

–

663

660

657

654

651

648

2

16

17

–

22

23

–

J1

K2

–

H4

G1

–

J2

J3

–

7

10

12

–

2

–

2

–

2

19

–

25

–

K1

–

H3

–

J4

–

14

–

G3

–

E6

–

F4

–

2

–

Notes:

1. Global control pin.

2. The pin-outs are the same for Pb-free versions of packages.

DS055 (v2.1 April 3, 2007

www.xilinx.com

7

Product Specification

1-800-255-7778

R

XC95288XL High Performance CPLD

(2)

XC95288XL I/O Pins (Continued)

Func-

tion Macro

Block cell

Func-

tion

Block

BScan

TQ144 PQ208 BG256 FG256 CS280 Order

Macro

cell

BScan

TQ144 PQ208 BG256 FG256 CS280 Order

5

1

2

–

34

–

49

50

–

U3

V2

–

R1

N3

–

U1

V1

–

645

642

639

636

633

630

627

7

8

1

2

–

62

63

–

W6

Y6

–

R3

M6

–

W5

U6

–

537

534

531

528

525

522

519

516

513

510

507

504

501

498

495

492

489

486

483

480

477

474

471

468

465

462

459

456

453

450

447

444

441

438

435

432

5

3

45

–

5

4

–

4

5

35

–

51

54

–

V3

Y2

–

P2

P4

–

U2

V3

–

5

46

–

64

66

–

V7

U8

–

T3

T4

–

V6

W6

–

5

6

5

7

–

7

–

5

8

38⁽¹⁾55⁽¹⁾W4⁽¹⁾P5⁽¹⁾W2⁽¹⁾624

8

–

67

–

W7

Y7

V8

W8

Y8

–

P7

T5

N7

R7

M7

–

U7

V7

W7

T7

W8

–

5

9

–

39

–

56

–

V4

U5

Y3

Y4

–

T2

N5

R4

M5

–

W3

T4

U4

V4

–

621

618

615

612

609

606

603

600

597

594

591

588

585

582

579

576

573

570

567

564

561

558

555

552

9

–

5

10

11

12

13

14

15

16

17

18

1

10

11

12

13

14

15

16

17

18

1

–

69

–

5

–

5

40

–

57

–

48

–

70

–

5

41

43

–

58

60

–

V5

V6

–

R5

R6

–

W4

V5

–

71

72

–

U9

V9

–

T6

N8

–

U8

V8

–

5

49

–

5

44

–

61

–

U7

–

N6

–

T5

–

73

–

W9

–

T7

–

T8

–

5

–

6

–

-

–

6

2

135

136

–

197

198

–

D7

C6

–

A5

D6

–

D7

A6

–

2

130

131

–

186

187

–

A9

B9

–

E11

A8

–

B10

C10

–

6

3

6

4

6

5

137

138

–

199

200

–

B5

A4

–

B5

C6

–

B6

C6

–

5

132

–

188

189

–

C9

D9

–

C8

B8

–

D10

A9

–

6

7

–

6

8

139

–

201

–

C5

B4

A3

D5

C4

–

A4

E7

A3

C5

A2

–

D6

A5

C5

B5

D5

–

8

133

–

191

–

A8

B8

C8

D8

A7

–

D8

A7

E9

B7

D7

–

B9

C9

D9

A8

B8

–

6

9

6

10

11

12

13

14

15

16

17

18

140

–

202

–

10

11

12

13

14

15

16

17

18

134

–

192

–

6

–

203

–

193

–

6

–

6

142

205

B2

B4

–

194

195

–

B7

B6

–

A6

B6

–

C8

B7

–

6

143⁽¹⁾206⁽¹⁾A2⁽¹⁾C4⁽¹⁾C4⁽¹⁾549

–

6

–

208

–

C3

–

B3

–

A3

–

546

543

540

–

6

–

196

–

A5

–

E8

–

C7

–

6

–

Notes:

1. Global control pin.

2. The pin-outs are the same for Pb-free versions of packages.

8

www.xilinx.com

DS055 (v2.1 April 3, 2007

1-800-255-7778

Product Specification

R

XC95288XL High Performance CPLD

(2)

XC95288XL I/O Pins (Continued)

Func-

tion Macro

Block cell

Func-

tion

Block

BScan

TQ144 PQ208 BG256 FG256 CS280 Order

Macro

cell

BScan

TQ144 PQ208 BG256 FG256 CS280 Order

9

1

2

–

50

51

–

74

75

–

R8

P8

–

U9

T9

–

429

426

423

420

11

12

1

2

–

87

88

–

321

Y11

W11

–

Y15

V14

–

P10 W13 318

9

3

60

–

T12

–

V13

–

315

312

309

306

303

9

4

9

5

52

53

–

76

77

–

V11

U11

–

T8

M8

–

W10 417

5

61

–

89

90

–

W15 N10 U13

9

6

V10

–

414

411

408

405

402

399

396

393

6

Y16

–

T13

–

T13

–

9

7

–

9

8

54

–

78

–

Y12

W12

V12

U12

Y13

–

T9

P9

R9

M9

T10

–

U10

W11

V11

U11

T11

–

8

–

91

–

U14

Y17

V16

Y18

V17

–

M11 W14 300

N11 T14 297

T14 W15 294

R12 V15 291

T15 W16 288

9

–

9

10

11

12

13

14

15

16

17

18

1

–

80

82

83

–

10

11

12

13

14

15

16

17

18

1

64

66

68

–

95

97

99

–

9

56

57

–

9

–

285

282

9

58

–

84

85

–

W13 M10 W12 390

69

–

100

101

–

Y19

V18

–

R14 U16

9

V13

–

R10

–

V12

–

387

384

381

378

375

372

369

366

363

360

357

354

351

348

345

342

339

336

333

330

327

324

N13 W17 279

276

9

–

9

59

–

86

–

W14

–

T11

–

T12

–

70

–

102

–

W19 R13 W18 273

9

–

270

267

264

261

258

255

252

249

246

243

240

237

234

231

228

225

222

219

216

10

Notes:

–

2

117

118

–

170

171

–

A14

C13

–

B11

D11

–

C14

B14

–

2

110

111

–

158

159

–

B18

C17

–

B13

B14

–

B19

B18

–

3

4

5

119

120

–

173

174

–

B13

A13

–

A11

D10

–

A14

C13

–

5

112

–

160

161

–

D16

A18

–

C13 B17

6

A15

–

A18

–

7

–

8

121

–

175

–

D12

C12

A12

B11

C11

–

B10

E12

F12

B9

C9

–

B13

A13

A12

C12

B12

–

8

113

–

162

–

A17

C16

A16

C15

D14

–

C12 A17

B12 D16

D13 C16

9

10

11

12

13

14

15

16

17

18

124

125

126

–

178

179

180

–

10

11

12

13

14

15

16

17

18

115

–

164

165

166

–

A14

E13

–

B16

A16

–

116

–

128

–

182

183

–

B10

C10

–

A9

D9

–

B11

C11

–

167

168

–

B15

A15

–

A13 C15

–

C11

–

B15

–

129

–

185

–

D10

–

E10

–

A10

–

169

–

C14

–

A12 D15

–

1. Global control pin.

2. The pin-outs are the same for Pb-free versions of packages.

DS055 (v2.1 April 3, 2007

www.xilinx.com

9

Product Specification

1-800-255-7778

R

XC95288XL High Performance CPLD

(2)

XC95288XL I/O Pins (Continued)

Func-

tion Macro

Block cell

Func-

tion

Block

BScan

TQ144 PQ208 BG256 FG256 CS280 Order

Macro

cell

BScan

TQ144 PQ208 BG256 FG256 CS280 Order

13

14

Notes:

1

2

–

71

–

213

210

207

204

201

198

195

192

189

186

183

180

177

174

171

168

165

162

159

156

153

150

147

144

141

138

135

132

129

126

123

120

117

114

111

108

15

16

1

2

–

79

80

–

105

102

99

96

93

90

87

84

81

78

75

72

69

66

63

60

57

54

51

48

45

42

39

36

33

30

27

24

21

18

15

12

9

103

106

–

Y20

V19

–

P13

P15

–

V17

U18

–

117

118

–

P19

P20

–

M12 P16

M16 P19

3

4

–

4

–

5

–

107

109

–

U19

T17

–

N14

R16

–

V19

U19

–

5

–

119

120

–

N17

N18

–

K14 N17

6

–

6

–

L16

–

N18

–

7

–

7

–

8

74

–

110

–

V20

U20

T18

T19

R18

–

N15

M15

M13

P16

N16

–

T16

T17

T18

T19

R18

–

8

81

–

121

–

N19

N20

M17

M18

M20

–

K13 N19

K15 N16

L12 M19

K16 M17

9

10

11

12

13

14

15

16

17

18

1

–

111

112

113

–

10

11

12

13

14

15

16

17

18

1

82

83

85

–

122

123

125

–

75

–

J14

–

M16

–

76

77

–

114

115

–

P17

R20

–

M14 R16

86

87

–

126

127

–

L19

L18

–

J15

J13

–

L19

L18

–

L15

–

R19

–

78

–

116

–

P18

–

L13

–

P17

–

88

–

128

–

L20

–

J16

–

L17

–

2

–

144

145

–

G19

F19

–

F15

E15

–

G19

G16

–

2

91

92

–

131

133

–

K19

K18

–

K12

J12

–

L16

K18

–

3

100

–

3

4

5

101

102

–

146

147

–

E20

G17

–

F13

D16

–

F19

F18

–

5

93

94

–

134

135

–

K17

J20

–

H15 K17

H14 K16

6

7

–

8

103

–

148

–

F18

E19

D20

E18

D19

–

F14

C16

E14

D15

G12

–

F17

F16

E19

E17

E18

–

8

95

–

136

–

J19

J18

J17

H20

H19

–

G16

H13

G15

H16

J19

J18

J17

J16

9

10

11

12

13

14

15

16

17

18

104

105

–

149

150

151

–

10

11

12

13

14

15

16

17

18

96

97

98

–

137

138

139

–

F16 H19

–

106

107

–

152

154

–

C20

D18

–

C15

D14

–

E16

D18

–

140

142

–

H18

H17

–

H12 H18

E16 H17

–

6

–

155

–

C18

–

B16

–

D17

–

143

–

G20 G14 H16

3

–

0

1. Global control pin.

2. The pin-outs are the same for Pb-free versions of packages.

10

www.xilinx.com

DS055 (v2.1 April 3, 2007

1-800-255-7778

Product Specification

R

XC95288XL High Performance CPLD

(1)

XC95288XL Global, JTAG and Power Pins

Pin Type

I/O/GCK1

I/O/GCK2

I/O/GCK3

I/O/GTS1

I/O/GTS2

I/O/GTS3

I/O/GTS4

I/O/GSR

TCK

TQ144

PQ208

44

46

55

7

BG256

FG256

M2

CS280

R3

30

T2

U2

32

M3

T1

38

W4

C1

P5

W2

D3

5

D4

6

9

E1

E5

E2

2

3

C2

D3

C2

3

5

D3

E3

C1

143

206

98

94

176

96

A2

C4

67

U16

W16

B12

W17

P12

R11

A10

N12

T15

U14

D13

U15

TDI

63

122

TDO

TMS

65

V_CCINT3.3V

8, 42, 84, 141

11, 59, 124, 153,

204

F1, P2, W5, Y9,

V10, U13, W18,

F4, F7, G6, H6, J6, E1, F2, N3, U5, W9,

K6, L7, F8, L8, F9, V9, U12, V16, R17,

T20, M19, F20, E17, L9, F10, L10, G11,

M18, G18, D19,

C18, A15, A11, D8,

A4

B17, B14, A10, C7,

B3, G4

H11, J11, K11

V_CCIO2.5V/3.3 V 1, 37, 55, 73, 109, 1, 26, 53, 65, 79, D4, D6, D11, D15, F3, K4, D5, F6, L6, C3, F1, K1, N4, V2

127

92, 105, 132, 157, D17, F4, F17, K4,

172, 181, 184 L17, R4, R17, U4, F11, L11, P11, D12,

P6, C7, N9, C10,

T6, T10, V14, V18,

P18, K19, G17,

C19, D14, D12, D11,

A7

U6, U10, U15, U17

G13, L14

GND

18, 29, 36, 47, 62, 2, 13, 24, 27, 42,

B1, K3, T1, Y5,

W10, Y10, Y14,

A1, A16, C14, T1, E5, F5, G5, H5, J5,

B2, B15, R2, C3, K5, L5, M5, N5, R5,

72, 89, 90, 99,

108, 114, 123,

144

52, 68, 81, 93,

104,1 08, 129, V15, U18, R19, K20, P3, G7, H7, J7, K7, R6, R7, R8, R9 R10,

130, 141, 156, G18, B16, D13, A11, G8, H8, J8, K8, G9, R11, R12, R13, R14,

163, 177, 190,

207

A6, J9, J10, J11,

J12, K9, K10, K11, H10, J10, K10, P14, M15, L15, K15, J15,

H9, J9, K9, G10,

R15, P15, N15,

K12, L9, L10, L11,

L12, M9, M10, M11,

M12

R15, T16

H15, G15, F15, E15,

E14, E13, E12, E11,

E10, E9, E8, E7, E6,

P5

No Connects

–

A1, A19, A20, B19,

B20, C19, W1, W2,

W3, W20, Y1

-

A1, B2, W1, U3,

W19, U17, A19,

C17, A2, B3

Notes:

1. The pin-outs are the same for Pb-free versions of packages.

DS055 (v2.1 April 3, 2007

www.xilinx.com

11

Product Specification

1-800-255-7778

R

XC95288XL High Performance CPLD

Device Part Marking and Ordering Combination Information

R

Device Type

Package

XC95xxxXL

TQ144

This line not

related to device

part number

Speed

7C

Operating Range

1

Sample package with part marking.

Speed

Device Ordering and

(pin-to-pin

delay)

Pkg.

No. of

Pins

Operating

Range⁽¹⁾

Part Marking Number

XC95288XL-6TQ144C

XC95288XL-6PQ208C

XC95288XL-6BG256C

XC95288XL-6FG256C

XC95288XL-6CS280C

XC95288XL-7TQ144C

XC95288XL-7PQ208C

XC95288XL-7BG256C

XC95288XL-7FG256C

XC95288XL-7CS280C

XC95288XL-7TQ144I

XC95288XL-7PQ208I

XC95288XL-7BG256I

XC95288XL-7FG256I

XC95288XL-7CS280I

XC95288XL-10TQ144C

XC95288XL-10PQ208C

XC95288XL-10BG256C

XC95288XL-10FG256C

XC95288XL-10CS280C

XC95288XL-10TQ144I

XC95288XL-10PQ208I

XC95288XL-10BG256I

XC95288XL-10FG256I

XC95288XL-10CS280I

XC95288XL-6TQG144C

Symbol

TQ144

PQ208

Package Type

6 ns

144-pin

208-pin

Thin Quad Flat Pack

Plastic Quad Flat Package

Plastic Ball Grid Array

C

I

6 ns

BG256 256-ball

FG256 256-ball

CS280 280-ball

6 ns

Plastic Fineline Ball Grid Array

Chipscale Package

6 ns

7.5 ns

10 ns

6 ns

TQ144

PQ208

144-pin

208-pin

Thin Quad Flat Pack

Plastic Quad Flat Package

Plastic Ball Grid Array

BG256 256-ball

FG256 256-ball

Plastic Fineline Ball Grid Array

Chipscale Package

CS280

TQ144

PQ208

280-pin

144-pin

208-pin

Thin Quad Flat Pack

Plastic Quad Flat Package

Plastic Ball Grid Array

I

BG256 256-ball

FG256 256-ball

I

Plastic Fineline Ball Grid Array

Chipscale Package

I

CS280

TQ144

PQ208

280-pin

144-pin

208-pin

I

Thin Quad Flat Pack

C

I

Plastic Quad Flat Package

Plastic Ball Grid Array

BG256 256-ball

FG256 256-ball

CS280 280-ball

Plastic Fineline Ball Grid Array

Chipscale Package

TQ144

PQ208

144-pin

208-pin

Thin Quad Flat Pack

Plastic Quad Flat Package

Plastic Ball Grid Array

I

BG256 256-ball

FG256 256-ball

CS280 280-ball

TQG144 144-pin

I

Plastic Fineline Ball Grid Array

Chipscale Package

I

Thin Quad Flat Pack; Pb-free

C

12

www.xilinx.com

1-800-255-7778

DS055 (v2.1 April 3, 2007

Product Specification

R

XC95288XL High Performance CPLD

Operating

Speed

(pin-to-pin

delay)

Device Ordering and

Part Marking Number

Pkg.

Symbol

No. of

Pins

Package Type

Range⁽¹⁾

XC95288XL-6PQG208C

XC95288XL-6BGG256C

XC95288XL-6FGG256C

XC95288XL-6CSG280C

XC95288XL-7TQG144C

XC95288XL-7PQG208C

XC95288XL-7BGG256C

XC95288XL-7FGG256C

XC95288XL-7CSG280C

XC95288XL-7TQG144I

XC95288XL-7PQG208I

XC95288XL-7BGG256I

XC95288XL-7FGG256I

XC95288XL-7CSG280I

XC95288XL-10TQG144C

XC95288XL-10PQG208C

XC95288XL-10BGG256C

XC95288XL-10FGG256C

XC95288XL-10CSG280C

XC95288XL-10TQG144I

XC95288XL-10PQG208I

XC95288XL-10BGG256I

XC95288XL-10FGG256I

XC95288XL-10CSG280I

Notes:

6 ns

PQG208 208-pin

BGG256 256-ball

FGG256 256-ball

CSG280 280-ball

TQG144 144-pin

PQG208 208-pin

BGG256 256-ball

FGG256 256-ball

CSG280 280-pin

TQG144 144-pin

PQG208 208-pin

BGG256 256-ball

FGG256 256-ball

CSG280 280-pin

TQG144 144-pin

PQG208 208-pin

BGG256 256-ball

FGG256 256-ball

CSG280 280-ball

TQG144 144-pin

PQG208 208-pin

BGG256 256-ball

FGG256 256-ball

CSG280 280-ball

Plastic Quad Flat Package; Pb-free

Plastic Ball Grid Array; Pb-free

Plastic Fineline Ball Grid Array; Pb-free

Chipscale Package; Pb-free

C

I

6 ns

7.5 ns

10 ns

Thin Quad Flat Pack; Pb-free

Plastic Quad Flat Package; Pb-free

Plastic Ball Grid Array; Pb-free

Plastic Fineline Ball Grid Array; Pb-free

Chipscale Package; Pb-free

Thin Quad Flat Pack; Pb-free

Plastic Quad Flat Package; Pb-free

Plastic Ball Grid Array; Pb-free

Plastic Fineline Ball Grid Array; Pb-free

Chipscale Package; Pb-free

I

Thin Quad Flat Pack; Pb-free

C

I

Plastic Quad Flat Package; Pb-free

Plastic Ball Grid Array; Pb-free

Plastic Fineline Ball Grid Array; Pb-free

Chipscale Package; Pb-free

Thin Quad Flat Pack; Pb-free

Plastic Quad Flat Package; Pb-free

Plastic Ball Grid Array; Pb-free

Plastic Fineline Ball Grid Array; Pb-free

Chipscale Package; Pb-free

I

1. C = Commercial: T_A= 0° to +70°C; I = Industrial: T_A= –40° to +85°C

Pb-

-4 TQ

G

144

C

XC95288XL

Free Example:

Standard Example: XC95288XL -4 TQ 144

C

Device

Speed Grade

Package Type

Speed Grade

Package Type

Number of Pins

Temperature Range

-Free

Pb

Number of Pins

Temperature Range

DS055 (v2.1 April 3, 2007

www.xilinx.com

13

Product Specification

1-800-255-7778

R

XC95288XL High Performance CPLD

Warranty Disclaimer

THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED

AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE

PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE

THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE

AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF

LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO

APPLICABLE LAWS AND REGULATIONS.

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