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产品型号XC9572XL-7TQ100I的概述

XC9572XL-7TQ100I概述 XC9572XL-7TQ100I是一款由赛灵思（Xilinx）公司推出的复杂可编程逻辑器件（CPLD），其设计旨在满足现代数字电路设计对高性能、低功耗和高集成度的需求。CPLD广泛应用于各种数字系统中，包括数据通信、消费电子、工业控制和汽车电子等领域。XC9572XL系列具有多种封装形式、不同的逻辑资源和丰富的设计灵活性，能够支持多种应用场景和设计要求。 XC9572XL系列的产品架构基于Xilinx的先进技术，提供了高达720个逻辑单元（LEs），支持多达96个输入/输出引脚。这些特性使得XC9572XL-7TQ100I成为一个在资源受限的情况下依然能够执行复杂逻辑运算的理想选择。芯片详细参数 XC9572XL-7TQ100I的关键技术指标和参数如下： - 逻辑单元数: 72个 - 引脚数: 100个 - 最大工作频率: 200 MHz - 供...

产品型号XC9572XL-7TQ100I的Datasheet PDF文件预览

XC9572XL High Performance

CPLD

DS057 (v1.1) August 28, 2000

Preliminary Product Specification

cations and computing systems. It is comprised of four

54V18 Function Blocks, providing 1,600 usable gates with

propagation delays of 5 ns. See Figure 2 for architecture

overview.

Features

•

5 ns pin-to-pin logic delays

System frequency up to 178 MHz

72 macrocells with 1,600 usable gates

Available in small footprint packages

Power Estimation

44-pin PLCC (34 user I/O pins)

44-pin VQFP (34 user I/O pins)

48-pin CSP (38 user I/O pins)

64-pin VQFP (52 user I/O pins)

100-pin TQFP (72 user I/O pins)

Power dissipation in CPLDs can vary substantially depend-

ing on the system frequency, design application and output

loading. To help reduce power dissipation, each macrocell

in a XC9500XL device may be configured for low-power

mode (from the default high-performance mode). In addi-

tion, unused product-terms and macrocells are automati-

cally deactivated by the software to further conserve power.

•

Optimized for high-performance 3.3V systems

Low power operation

5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V

signals

For a general estimate of I , the following equation may be

used:

3.3V or 2.5V output capability

Advanced 0.35 micron feature size CMOS

FastFLASH™ technology

(mA) = MC (0.5) + MC (0.3) + MC(0.0045 mA/MHz) f

HP LP

Where:

MC = Macrocells in high-performance (default) mode

Advanced system features

In-system programmable

MC = Macrocells in low-power mode

Superior pin-locking and routability with

FastCONNECT II™ switch matrix

Extra wide 54-input Function Blocks

Up to 90 product-terms per macrocell with

individual product-term allocation

Local clock inversion with three global and one

product-term clocks

Individual output enable per output pin

Input hysteresis on all user and boundary-scan pin

inputs

MC = Total number of macrocells used

f = Clock frequency (MHz)

This calculation is based on typical operating conditions

using a pattern of 16-bit up/down counters in each Function

Block with no output loading. The actual I

with the design application and should be verified during

normal system operation.

value varies

Figure 1 shows the above estimation in a graphical form.

100

Bus-hold circuitry on all user pin inputs

Full IEEE Standard 1149.1 boundary-scan (JTAG)

178 MHz

•

Fast concurrent programming

Slew rate control on individual outputs

Enhanced data security features

Excellent quality and reliability

104 MHz

Endurance exceeding 10,000 program/erase

cycles

20 year data retention

ESD protection exceeding 2,000V

•

Pin-compatible with 5V-core XC9572 device in the

44-pin PLCC package and the 100-pin TQFP package

Description

The XC9572XL is a 3.3V CPLD targeted for high-perfor-

mance, low-voltage applications in leading-edge communi-

100

150

200

Clock Frequency (MHz)

DS057_01_081500

Figure 1: Typical I vs. Frequency for XC9572XL

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS057 (v1.1) August 28, 2000

www.xilinx.com

Preliminary Product Specification

1-800-255-7778

XC9572XL High Performance CPLD

JTAG

In-System Programming Controller

JTAG Port

Controller

Function

Block 1

I/O

Macrocells

1 to 18

I/O

Function

Block 2

Macrocells

1 to 18

I/O

Blocks

I/O

Function

Block 3

Macrocells

1 to 18

I/O

I/O/GCK

I/O/GSR

I/O/GTS

Function

Block 4

Macrocells

1 to 18

DS057_02_082800

Figure 2: XC9572XL Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

www.xilinx.com

DS057 (v1.1) August 28, 2000

1-800-255-7778

Preliminary Product Specification

XC9572XL High Performance CPLD

Absolute Maximum Ratings

Symbol

Description

Value

–0.5 to 4.0

–0.5 to 5.5

–65 to +150

+260

Units

Supply voltage relative to GND

(1)

Input voltage relative to GND

(1)

Voltage applied to 3-state output

Storage temperature (ambient)

STG

Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)

Junction temperature

SOL

+150

Notes:

1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the

device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the

forcing current being limited to 200 mA.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions

is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Recommended Operation Conditions

Symbol

Parameter

Min

3.0

2.3

Max

3.6

Units

Supply voltage for internal logic

and input buffers

Commercial T = 0 C to 70 C

CCINT

Industrial T = –40 C to +85 C

3.6

Supply voltage for output drivers for 3.3V operation

Supply voltage for output drivers for 2.5V operation

Low-level input voltage

3.6

CCIO

2.7

0.80

5.5

High-level input voltage

2.0

Output voltage

CCIO

Quality and Reliability Characteristics

Symbol

Parameter

Min

Max

Units

Data Retention

Years

Cycles

Volts

Program/Erase Cycles (Endurance)

Electrostatic Discharge (ESD)

10,000

2,000

ESD

DC Characteristic Over Recommended Operating Conditions

Symbol

Parameter

Output high voltage for 3.3V outputs

Output high voltage for 2.5V outputs

Output low voltage for 3.3V outputs

Output low voltage for 2.5V outputs

Input leakage current

Test Conditions

Min

Max

Units

= –4.0 mA

= –500 µA

= 8.0 mA

= 500 µA

= Max

2.4

90% V

CCIO

0.4

±10

µA

= GND or V

= Max

I/O high-Z leakage current

I/O capacitance

±10

µA

= GND or V

= GND

f = 1.0 MHz

Operating supply current

(low power mode, active)

V = GND, No load

f = 1.0 MHz

20 (Typical)

DS057 (v1.1) August 28, 2000

Preliminary Product Specification

www.xilinx.com

1-800-255-7778

XC9572XL High Performance CPLD

AC Characteristics

XC9572XL-5

XC9572XL-7

XC9572XL-10

(1)

Symbol

Parameter

Min

Max

5.0

Min

Max

7.5

Min

Max

10.0

Units

I/O to output valid

I/O setup time before GCK

I/O hold time after GCK

3.7

4.8

6.5

0.0

GCK to output valid

3.5

178.6

4.5

125.0

5.8

100.0

Multiple FB internal operating frequency

I/O setup time before p-term clock input

I/O hold time after p-term clock input

P-term clock output valid

MHz

SYSTEM

1.7

1.6

2.1

PSU

2.0

3.2

4.4

5.5

4.0

7.0

10.0

10.5

7.7

5.0

9.5

12.0

12.6

10.2

7.0

11.0

14.5

15.3

PCO

GTS to output valid

GTS to output disable

Product term OE to output enabled

Product term OE to output disabled

GSR to output valid

POE

POD

P-term S/R to output valid

GCK pulse width (High or Low)

P-term clock pulse width (High or Low)

PAO

WLH

2.8

5.0

4.0

6.5

4.5

7.0

PLH

Advance

Preliminary

Notes:

1. Please contact Xilinx for up-to-date information on advance specifications.

TEST

Output Type

CCIO

TEST

Device Output

3.3V

2.5V

3.3V

2.5V

320 Ω

250 Ω

360 Ω

660 Ω

35 pF

DS058_03_081500

Figure 3: AC Load Circuit

www.xilinx.com

DS057 (v1.1) August 28, 2000

1-800-255-7778

Preliminary Product Specification

XC9572XL High Performance CPLD

Internal Timing Parameters

XC9572XL-5

XC9572XL-7

XC9572XL-10

(1)

Symbol

Parameter

Min

Max

Min

Max

Min

Max

Units

Buffer Delays

Input buffer delay

1.5

1.1

2.0

4.0

2.0

0.0

2.3

1.5

3.1

5.0

2.5

0.0

3.5

1.8

4.5

7.0

3.0

0.0

GCK buffer delay

GSR buffer delay

GTS buffer delay

Output buffer delay

Output buffer enable/disable

delay

GCK

GSR

GTS

OUT

Product Term Control Delays

Product term clock delay

Product term set/reset delay

Product term 3-state delay

1.6

1.0

5.5

2.4

1.4

7.2

2.7

1.8

7.5

PTCK

PTSR

PTTS

Internal Register and Combinatorial Delays

Combinatorial logic propagation delay

0.5

2.6

2.2

2.6

2.2

1.3

3.0

3.5

3.0

3.5

1.7

PDI

SUI

2.3

1.4

2.3

1.4

Internal logic delay

ECSU

ECHO

0.4

6.0

0.5

6.4

1.0

7.0

COI

AOI

5.0

7.5

10.0

RAI

1.0

5.0

1.4

6.4

1.8

7.3

LOGI

Internal low power logic delay

LOGILP

Feedback Delays

FastCONNECT II feedback delay

Time Adders

1.9

3.5

4.2

Incremental product term allocator delay

Slew-rate limited delay

0.7

3.0

0.8

4.0

1.0

4.5

PTA

SLEW

Advance

Preliminary

Notes:

1. Please contact Xilinx for up-to-date information on advance specifications.

DS057 (v1.1) August 28, 2000

www.xilinx.com

Preliminary Product Specification

1-800-255-7778

XC9572XL High Performance CPLD

XC9572XL I/O Pins

Func-

tion

Block

Func

-tion

Block

Macro-

cell

BScan

Macro-

cell

BScan

PC44 VQ44 CS48 VQ64 TQ100 Order

213

210

207

204

201

198

195

192

189

186

183

180

177

174

171

168

165

162

159

156

153

150

147

144

141

138

135

132

129

126

123

120

117

114

111

108

105

102

(1)

(2)

(1)

(3)

Notes:

1. Global control pin.

2. GTS1 for TQ100.

3. GTS1 for PC44, VQ44, CS48, and VQ64.

www.xilinx.com

1-800-255-7778

DS057 (v1.1) August 28, 2000

Preliminary Product Specification

XC9572XL High Performance CPLD

XC9572XL Global, JTAG and Power Pins

Pin Type

I/O/GCK1

I/O/GCK2

I/O/GCK3

I/O/GTS1

I/O/GTS2

I/O/GSR

TCK

PC44

VQ44

CS48

VQ64

TQ100

TDI

TDO

TMS

V_CCINT3.3V

V_CCIO2.5V/3.3V

GND

21, 41

15, 35

C1, F7

3, 37

5, 57, 98

26, 38, 51, 88

21, 31, 44, 62,

69, 75, 84, 100

2, 7, 19, 24, 34,

43, 46, 73, 80

26, 55

14, 21, 41, 54

10, 23, 31

4, 17, 25

A5, D1, F3

No Connects

DS057 (v1.1) August 28, 2000

Preliminary Product Specification

www.xilinx.com

1-800-255-7778

XC9572XL High Performance CPLD

Ordering Information

Example:

XC9572XL -7 TQ 100 C

Device Type

Temperature Range

Number of Pins

Package Type

Speed Grade

Device Ordering Options

Speed

Package

Temperature

T = 0°C to + 70°C

-10 10 ns pin-to-pin delay

-7 7.5 ns pin-to-pin delay

-5 5 ns pin-to-pin delay

PC44 44-pin Plastic Lead Chip Carrier (PLCC)

VQ44 44-pin Quad Flat Pack (VQFP)

CS48 48-pin Chip Scale Package

C = Commercial

I = Industrial

T = –40°C to + 85°C

VQ64 64-pin Quad Flat Pack (VQFP)

TQ100 100-pin Thin Quad Flat Pack (TQFP)

Component Availability

Pins

Plastic

PLCC

PC44

C, I

Plastic

VQFP

VQ44

C, I

Plastic

VQFP

VQ64

C, I

100

Plastic

TQFP

TQ100

C, I

Plastic

Type

Code

CSP

CS48

XC9572XL

-10

-7

C, I

-5

(C)

Notes:

1. C = Commercial (T = 0 C to +70 C); I = Industrial (T = –40 C to +85 C)

2. ( ) Parenthesis indicate future products. Please contact Xilinx for up-to-date information.

Revision History

The following table shows the revision history for this document.

Date

Version

1.0

Revision

09/28/98

08/28/00

Initial Xilinx release.

1.1

Added VQ44 package.

www.xilinx.com

DS057 (v1.1) August 28, 2000

1-800-255-7778

Preliminary Product Specification

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XC9572XL-7TQ100I产品参数

型号:	XC9572XL-7TQ100I
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Active
零件包装代码：	QFP
包装说明：	LFQFP, QFP100,.63SQ,20
针数：	100
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	12 weeks
风险等级：	5.12
其他特性：	72 MACROCELLS
最大时钟频率：	125 MHz
系统内可编程：	YES
JESD-30 代码：	S-PQFP-G100
JESD-609代码：	e0
JTAG BST：	YES
长度：	14 mm
湿度敏感等级：	3
专用输入次数：
I/O 线路数量：	72
宏单元数：	72
端子数量：	100
最高工作温度：	85 °C
最低工作温度：	-40 °C
组织：	0 DEDICATED INPUTS, 72 I/O
输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP
封装等效代码：	QFP100,.63SQ,20
封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	225
电源：	2.5/3.3,3.3 V
可编程逻辑类型：	FLASH PLD
传播延迟：	7.5 ns
认证状态：	Not Qualified
座面最大高度：	1.6 mm
子类别：	Programmable Logic Devices
最大供电电压：	3.6 V
最小供电电压：	3 V
标称供电电压：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	30
宽度：	14 mm
Base Number Matches：	1

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