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产品型号XRT7295ATIW的概述

XRT7295ATIW芯片概述 XRT7295ATIW是一款高性能的数字信号处理器(DSP)芯片，专门设计用于通信和信号处理领域。其内部架构经过优化，以满足现代通信系统对带宽、速度和灵活性的要求。该器件主要应用于调制解调器、基站、光纤通信等场景。 XRT7295ATIW的设计旨在实现高效的信号处理能力，同时保持低功耗特性。其整体架构结合了并行处理和流水线技术，使得在多种操作下能够保持较高的效率。这使得它特别适合需要高数据吞吐量的应用，如4G/5G基站的信号处理。 XRT7295ATIW的详细参数 XRT7295ATIW芯片的特性参数包括： - 工作电压：1.8V至3.3V - 工作频率：主频高达1GHz - 数据处理能力：支持高达1.5 Gbps的数据处理速度 - 功耗：典型功耗在1.5W左右，适合高集成度和低功耗的应用环境。 - 封装类型：LQFP封装，封装尺寸为14mm x 14m...

产品型号XRT7295ATIW的Datasheet PDF文件预览

XRT7295AT

DS3/Sonet STS-1

Integrated Line Receiver

December 2000-2

FEATURES

APPLICATIONS

D Fully Integrated Receive Interface for DS3 and

D Interface to DS-3 Networks

D Digital Cross-Connect Systems

D CSU/DSU Equipment

STS-1 Rate Signals

D Integrated Equalization (Optional) and Timing

Recovery

D PCM Test Equipment

D Loss-of-Signal and Loss-of-Lock Alarms

D Variable Input Sensitivity Control

D Fiber Optic Terminals

D 5V Power Supply

D Pin Compatible with XRT7295AE and XRT7295AC

D Companion Device to T7296 Transmitter

GENERAL DESCRIPTION

The XRT7295AT DS3/SONET STS-1 integrated line

receiver is a fully integrated receive interface that

terminates a bipolar DS3 (44.736Mbps) or Sonet STS-1

(51.84Mbps) signal transmitted over coaxial cable. (See

Figure 13).

settings, to adapt longer cables. High input sensitivity

allows for significant amounts of flat loss within the

system. Figure 1 shows the block diagram of the device.

The XRT7295AT device is manufactured using linear

CMOS technology. The XRT7295AT is available in a

20-pin plastic SOJ package for surface mounting.

The device also provides the functions of receive

equalization (optional), automatic-gain control (AGC),

clock-recovery and data retiming, loss-of-signal and

loss-of-frequency-lock detection. The digital system

interface is dual-rail, with received positive and negative

1s appearing as unipolar digital signals on separate

output leads. The on-chip equalizer is designed for cable

distances of 0 to 450ft. from the cross-connect frame to

the device. The receive input has a variable input

sensitivity control, providing three different sensitivity

Two versions of the chip are available, one is for either

DS3 or STS-1 operation (the XRT7295AT, this data

sheet), and the other is for E3 operation(the XRT7295AE,

refer to the XRT7295AE data sheet). Both versions are

pin compatible.

For either DS3 or STS-1, an input reference clock at

44.736MHz or 51.84MHz provides the frequency

reference for the device.

ORDERING INFORMATION

Operating

Part No.

Package

20 Lead 300 Mil JEDEC SOJ

Temperature Range

XRT7295ATIW

-40°C to + 85°C

Rev. 1.20

E2000

EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017

XRT7295AT

BLOCK DIAGRAM

LPF1 LPF2

GNDA V

GNDD V

GNDC

REQB

Loop

Filter

Gain &

Equalizer

Phase

Detector

Slicers

Attenuator

RCLK

VCO

RPDATA

RNDATA

Retimer

Peak

Detector

Digital

LOS

Detector

Frequency Phase

Aquisition Circuit

AGC

LOSTHR

Analog

LOS

RLOS

Analog

LOS

Equalizer

Tuning Ckt.

ICT

TMC1 TMC2

EXCLK RLOL

Figure 1. Block Diagram

Rev.1.20

XRT7295AT

PIN CONFIGURATION

GNDA

LOSTHR

REQB

ICT

RPDATA

RNDATA

RCLK

EXCLK

TMC1

LPF1

LPF2

TMC2

RLOS

RLOL

GNDD

GNDC

20 Lead SOJ (Jedec, 0.300”)

PIN DESCRIPTION

Pin #

Symbol

GNDA

R_IN

Type Description

Analog Ground.

Receive Input. Analog receive input. This pin is internally biased at about 1.5V in series

with 50 kΩ.

3,6

TMC1-TMC2

Test Mode Control 1 and 2. Internal test modes are enabled within the device by using

TMC1 and TMC2. Users must tie these pins to the ground plane.

4,5

LPF1-LPF2

RLOS

PLL Filter 1 and 2. An external capacitor (0.1µF ‵ 20%) is connected between these pins.

Receive Loss-of-signal. This pin is set high on loss of the data signal at the receive input.

(See Table 6)

RLOL

GNDD

Receive PLL Loss-of-lock. This pin is set high on loss of PLL frequency lock.

Digital Ground for PLL Clock. Ground lead for all circuitry running synchronously with

PLL clock.

GNDC

Digital Ground for EXCLK. Ground lead for all circuitry running synchronously with

EXCLK.

V_DD

5V Digital Supply (‵ 10%) for PLL Clock. Power for all circuitry running synchronously

with PLL clock.

V_DD

5V Digital Supply (‵ 10%) for EXCLK. Power for all circuitry running synchronously with

EXCLK.

EXCLK

External Reference Clock. A valid DS3 (44.736MHz ‵ 100ppm) or STS-1 (51.84MHz +

100ppm) clock must be provided at this input. The duty cycle of EXCLK, referenced to V_DD

/2 levels, must be within 40% - 60% with a minimum rise and fall time (10% to 90%) of 5ns.

RCLK

RNDATA

Receive Clock. Recovered clock signal to the terminal equipment.

Receive Negative Data. Negative pulse data output to the terminal equipment. (See

Figure 11.)

RPDATA

ICT

Receive Positive Data. Positive pulse data output to the terminal equipment. (See

Figure 11)

In-circuit Test Control (Active-low). If ICT is forced low, all digital output pins (RCLK,

RPDATA, RNDATA, RLOS, RLOL) are placed in a high-impedance state to allow for in-cir-

cuit testing. There is an internal pull-up on this pin.

REQB

Receive Equalization Bypass. A high on this pin bypasses the internal equalizer. A low

places the equalizer in the data path.

LOSTHR

Loss-of-signal Threshold Control. The voltage forced on this pin controls the input loss-

of-signal threshold. Three settings are provided by forcing GND, V_DD/2, or V_DD. This pin

must be set to the desired level upon power-up and should not be changed during opera-

tion.

V_DDA

5V Analog Supply (‵ 10%).

Rev.1.20

XRT7295AT

ELECTRICAL CHARACTERISTICS

Test Conditions: T = -40°C to +85°C, V = 5V + 10%

Typical Values are for V

= 5.0 V, 25°C, and Random Data. Maximum Values are for V = 5.5V all 1s Data.

Symbol

Electrical Characteristics

I_DDPower Supply Current

Parameter

Min.

Typ.

Max.

Unit

Condition

DS3

106

103

REQB=0

REQB=1

STS--1

111

REQB=0

REQB=1

108

Logic Interface Characteristics

Input Voltage

V_IL

V_IH

Low

GNDD

0.5

High

D-0.5

V_DDD

Output Voltage

Low

V_OL

V_OH

C_I

GNDD

D-0.5

0.4

-5.0mA

5.0mA

High

V_DDD

Input Capacitance

Load Capacitance

Input Leakage

µA

C_L

I_L

-10

-0.5 to V_DD+ 0.5V

(all input pins except 2, 3, 4, 5, 6,

17, 18, & 19)

500

100

-5

µA

0 V (pin 17)

V_DD(pin 2)

GNDD (pin 2)

-50

Specifications are subject to change without notice

ABSOLUTE MAXIMUM RATINGS

Power Supply . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.5V

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 700 mW

Storage Temperature . . . . . . . . . . . . -40°C to +125°C

Rev.1.20

XRT7295AT

System A

System B

0-450 ft.

Cross

Connect

XR-T7296

Transmitter

XRT7295AT

Receiver

Frame

DSX-3

or STSX-1

Type 728A

Coaxial Cable

Figure 2. Application Diagram

SYSTEM DESCRIPTION

Receive Path Configurations

In the receive signal path (see Figure 1), the internal

equalizer can be included by setting REQB = 0 or

bypassed by setting REQB = 1. The equalizer bypass

option allows easy interfacing of the XRT7295AT device

into systems already containing external equalizers.

Figure 3 illustrates the receive path options.

In Case 2 of Figure 3, external line build-out (LBO) and

equalizer networks precede the XRT7295AT device. In

this mode, the signal at R is already equalized, and the

on-chip filters should be bypassed by setting REQB=1.

In applications where the XRT7295AT device is used to

monitor DS3 transmitter outputs directly, the receive

equalizer should be bypassed.

Maximum input amplitude under all conditions is 850mV

pk.

In Case 1 of Figure 3, the signal from the DSX-3

cross-connect feeds directly into R . In this mode, the

user should set REQB = 0, engaging the equalizer in the

data path.

Rev.1.20

XRT7295AT

0-450 ft.

CASE 1:

REQB

0.01µF

LPF1

LPF2

0.1µF

XRT7295AT

Existing

Off-chip

Networks

CASE 2:

0-450 ft.

REQB

LPF1

LPF2

0.01µF

Fixed

Equalizer

225 ft.

LBO

0.1µF

XRT7295AT

Closed For

225-450 ft.

Of Cable

Figure 3. Receiver Configurations

Rev.1.20

XRT7295AT

DS3 SIGNAL REQUIREMENTS AT THE DSX

Pulse characteristics are specified at the DSX-3, which is

an interconnection and test point referred to as the

cross-connect (see Figure 2.) The cross-connect exists

at the point where the transmitted signal reaches the

distribution frame jack. Table 1 lists the signal

requirements. Currently, two isolated pulse template

requirements exist: the ACCUNET T45 pulse template

(see Table 2 and Figure 4)and the G.703 pulse template

(see Table 3 and Figure 5). Table 2 and Table 3 give the

associated boundary equations for the templates. The

XRT7295AT correctly decodes any transmitted signal

that meets one of these templates at the cross-connect.

Parameter

Specification

Line Rate

44.736 Mbps ¦20 ppm

Line Code

Test Load

Bipolar with three-0 substitution (B3ZS)

75 Ω ¦5%

Pulse Shape

An isolated pulse must fit the template in NO TAG or Figure 5.¹The pulse amplitude may be scaled by

a constant factor to fit the template. The pulse amplitude must be between 0.36vpk and 0.85vpk,

measured at the center of the pulse.

Power Levels

For and all 1s transmitted pattern, the power at 22.368 ‵ 0.002MHz must be -1.8 to +5.7dBm, and

the power at 44.736 ‵ 0.002MHz must be -21.8dBm to -14.3dBm.^{2, 3}

Notes

The pulse template proposed by G.703 standards is shown in Figure 5 and specified in Table 3. The proposed G.703 standards

further state that the voltage in a time slot containing a 0 must not exceed ‵ 5% of the peak pulse amplitude, except for the residue

of preceding pulses.

The power levels specified by the proposed G.703 standards are identical except that the power is to be measured in 3kHz bands.

The all 1s pattern must be a pure all 1s signal, without framing or other control bits.

Table 1. DSX-3 Interconnection Specification

Lower Curve

Upper Curve

Time

T ± -0.36

Equation

Time

T±-0.68

Equation

0.5 (1+sin {π/2}[1+T/0.18])

0.5 (1+sin {π/2} [1+T/0.34])

-0.36 ± T ± +0.28

0.28 ± T

-0.68 ± T± +0.36

0.36 ± T

0.11e^-3.42(T-0.3)

0.05 + 0.407e^{-1.84(T-0.36)}

Table 2. DSX-3 Pulse Template Boundaries for ACCUNET T45 Standards (See Figure 4.)

Rev.1.20

XRT7295AT

1.0

0.8

0.6

0.4

0.2

-1.0

-0.5

0.5

1.0

1.5

2.0

Time Slots - Normalized To Peak Location

Figure 4. DSX-3 Isolated Pulse Template for ACCUNET T45 Standards

Lower Curve

Upper Curve

Time

T± -0.36

Function

Time

Function

T ± -0.65

0.5 (1+sin {π/2} [1+T/0.18])

1.05 1-e^-4.6(T+0.65)

-0.36 ± T±+0.28

0.28 ± T

-0.65 ± T± 0

0 ± T ± 0.36

0.36 ± T

0.11e^-3.42(T-0.3)

0.5 (1+sin {π/2} [1+T/0.34])

0.05+0.407e^{-1.84(T-0.36)}

Table 3. DSX-3 Pulse Template Boundaries for G.703 Standards (See Figure 5)

1.0

0.8

0.6

0.4

0.2

-1.0

-0.5

0.5

1.0

1.5

2.0

Time Slots - Normalized To Peak Location

Figure 5. DSX-3 Isolated Pulse Template for G.703 Standards

Rev.1.20

XRT7295AT

STS-1 SIGNAL REQUIREMENTS AT THE STSX

Parameter

Line Rate

Specification

51.84 Mbps

For STS-1 operation, the cross-connect is referred at the

STSX-1. Table 4 lists the signal requirements at the

STSX-1. Instead of the DS3 isolated pulse template, an

eye diagram mask is specified for STS-1 operation

(TA-TSY-000253). The XRT7295AT correctly decodes

any transmitted signal that meets the mask shown in

Figure 6 at the STSX-1.

Line Code

Test Load

Bipolar with three-0 substitution (B3ZS)

75Ω‵ 5%

Power Levels

A wide-band power level measurement

at the STSX-1 interface using a low-pass

filter with a 3dB cutoff frequency of at

least 200MHz is within -2.7 dBm and 4.7

dBm.

Table 4. STSX-1 Interconnection Specification

1.0

0.8

0.6

0.4

0.2

-1.0

-0.5

0.5

1.0

1.5

2.0

Time Slots - Normalized To Peak Location

Figure 6. STSX-1 Isolated Pulse Template for Bellcore TA-TSY-000253

LINE TERMINATION AND INPUT CAPACITANCE

The distribution frame jack may introduce 0.6 ‵ 0.55 dB

of loss. This loss may be any combination of flat or

shaped (cable) loss.

The recommended receive termination is shown in

Figure 3 The 75 Ω resistor terminates the coaxial cable

with its characteristic impedance. The 0.01µF capacitor

The maximum cable distance between the point where

the transmitted signal exits the distribution frame jack and

the XRT7295AT device is 450 ft. (see Figure 2.) The

coaxial cable (Type 728A) used for specifying this

distance limitation has the loss and phase characteristics

shown in Figure 7 and Figure 8. Other cable types also

may be acceptable if distances are scaled to maintain

cable loss equivalent to Type 728A cable loss.

to R couples the signal into the receive input without

disturbing the internally generated DC bias level present

on R . The input capacitance at the R pin is 2.8pF

typical.

LOSS LIMITS FROM THE DSX-3 TO THE RECEIVE

INPUT

TIMING RECOVERY

External Loop Filter Capacitor

The signal at the cross-connect may travel through a

distribution frame, coaxial cable, connector, splitters, and

back planes before reaching the XRT7295AT device.

This section defines the maximum distribution frame and

cable loss from the cross-connect to the XRT7295AT

input.

Figure 3 shows the connection to an external 0.1µF

capacitor at the LPF1/LPF2 pins. This capacitor is part of

the PLL filter. A non-polarized, low-leakage capacitor

should be used. A ceramic capacitor with the value 0.1µF

‵

20% is acceptable.

Rev.1.20

XRT7295AT

OUTPUT JITTER

data pattern dependent jitter due to misequalization of the

input signal, all create jitter on RCLK. The magnitude of

this internally generated jitter is a function of the PLL

bandwidth, which in turn is a function of the input 1s

density. For higher 1s density, the amount of generated

jitter decreases. Generated jitter also depends on the

quality of the power supply bypassing networks used.

Figure 12 shows the suggested bypassing network, and

Table 5 lists the typical generated jitter performance.

The total jitter appearing on the RCLK output during

normal operation consists of two components. First,

some jitter appears on RCLK because of jitter on the

incoming signal. (The next section discusses the jitter

transfer characteristic, which describes the relationship

between input and output jitter.) Second, noise sources

within the XRT7295AT device and noise sources that are

coupled into the device through the power supplies and

100

1.0

1.0 2.0

5.0 10

50 100

2.0

5.0 10 20

50 100

Frequency (MHz)

Figure 7. Loss Characteristic of 728A

Coaxial Cable (450 ft.)

Figure 8. Phase Characteristic of 728A

Coaxial Cable (450 ft.)

JITTER TRANSFER CHARACTERISTIC

Parameter

Generated Jitter¹

All 1s pattern

Typ

Max

Unit

The jitter transfer characteristic indicates the fraction of

input jitter that reaches the RCLK output as a function of

input jitter frequency. Table 5 shows Important jitter

transfer characteristic parameters. Figure 9 also shows a

typical characteristic, with the operating conditions as

described in Table 5. Although existing standards do not

specify jitter transfer characteristic requirements, the

XRT7295AT information is provided here to assist in

evaluation of the device.

1.0

1.5

ns peak-to-peak

Repetitive “100”

pattern

Jitter Transfer

Characteristic²

Peaking

f 3dB

0.05

205

kHz

Notes

¹Repetitive input data pattern at nominal DSX-3 level with V_DD

= 5V T_A= 25°C.

²Repetitive “100 ” input at nominal DSX-3 level with V_DD= 5V,

T_A= 25°C.

Table 5. Generated Jitter and Jitter Transfer

Characteristics

Rev.1.20

XRT7295AT

JITTER ACCOMMODATION

LOSS-OF-LOCK DETECTION

Under all allowable operating conditions, the jitter

accommodation of the XRT7295AT device exceeds all

As stated above, the PLL acquisitionaid circuitry monitors

the PLL clock frequency relative to the EXCLK frequency.

The RLOL alarm is activated if the difference between the

PLL clock and the EXCLK frequency exceeds

approximately ‵ 0.5%.

system

(BER<1E ). The typical (V

requirements

for

error-free

= 5V, T = 25°C, DSX-3

operation

-9

nominal signal level) jitter accommodation for the

XRT7295AT is shown in Figure 10.

This will not occur until at least 250 bit periods after loss of

input data.

FALSE-LOCK IMMUNITY

False-lock is defined as the condition where a PLL

recovered clock obtains stable phase-lock at a frequency

not equal to the incoming data rate. The XRT7295AT

device uses

combination frequency/phase-lock

PEAK = 0.05dB

architecture to prevent false-lock. An on-chip frequency

comparatorcontinuously compares the EXCLKreference

to the PLL clock. If the frequency difference between the

EXCLK and PLL clock exceeds approximately ‵ 0.5%,

correction circuitry forces re-acquisition of the proper

frequency and phase.

-1

-2

f3dB = 205kHz

-3

-4

-5

ACQUISITION TIME

100

500 1K

5K 10K

50K100K 500K

If a valid input signal is assumed to be already present at

R , the maximum time between the application of device

Frequency (Hz)

power and error-free operation is 20ms. If power has

already been applied, the interval between the application

of valid data (or the action of valid data following a loss of

signal) and error-free operation is 4ms.

Figure 9. Typical PLL Jitter Transfer

Characteristic

TR-TSY-000499

Category 2

XRT7295AT Typical

Jitter

Frequency

(Hz)

Jitter

Amplitude

(U.I.)

TR-TSY-000499

Category 1

XRT7295AT Typical

G.824

10k

60k

300k

0.5

0.4

PUB 54014

1.0

0.1

100

10K

100K

1000K

Sinewave Jitter Frequency (Hz)

Figure 10. Input Jitter Tolerance at DSX-3 Level

Rev.1.20

XRT7295AT

A high RLOL output indicates that the acquisition circuit is

working to bring the PLL into proper frequency lock.

RLOL remains high until frequency lock has occurred;

however, the minimum RLOL pulse width is 32 clock

cycles.

To allow for varying levels of noise and crosstalk in

different applications, three loss-of-signal threshold

settings are available using the LOSTHR pin. Setting

LOSTHR = V

provides the lowest loss-of-signal

threshold; LOSTHR = V /2 (can be produced using two

50 kΩ ‵ 10% resistors as a voltage divider between

PHASE HITS

D and GNDD) provides an intermediate threshold;

and LOSTHR = GND provides the highest threshold. The

LOSTHR pin must be set to its desired value at power-up

and must not be changed during operation.

In response to a phase hit in the input data, the

XRT7295AT returns to error free operation in less than

2ms. During the requisition time, RLOS may temporarily

be indicated.

DIGITAL DETECTION

LOSS-OF-SIGNAL DETECTION

In addition to the signal amplitude monitoring of the

analog LOS detector, the digital LOS detector monitors

the recovered data 1s density. The RLOS alarm goes

high if 160 ‵ 32 or more consecutive 0s occur in the

receive data stream. The alarm goes low when at least

ten 1s occur in a string of 32 consecutive bits. This

hysteresis prevents RLOS chattering and guarantees a

minimum RLOS pulse width of 32 clock cycles. Note,

however, that RLOS chatter can still occur. When

REQB=1, input signal levels above the analog RLOS

thresholdcan still be low enoughto result in a highbit error

rate. The resultant data stream (containing) errors can

temporarily activate the digital LOS detector, and RLOS

chatter can occur. Therefore, RLOS should not be used

as a bit error rate monitor.

Figure 1 shows that analog and digital methods of

loss-of-signal (LOS) detection are combined to create the

RLOS alarm output. RLOS is set if either the analog or

digital detection circuitry indicates LOS has occurred.

ANALOG DETECTION

The analog LOS detector monitors the peak input signal

amplitude. RLOS makes a high-to-low transition (input

signal regained) when the input signal amplitude exceeds

the loss-of signal threshold defined in Table 6. The RLOS

low-to-high transition (input signal loss) occurs at a level

typically 1.0 dB below the high-to-low transition level. The

hysteresis prevents RLOS chattering. Once set, the

RLOS alarm remains high for at least 32 clock cycles,

allowing for system detection of a LOS condition without

the use of an external latch.

RLOS chatter can also occur when RLOL is activated

(high).

Rev.1.20

XRT7295AT

Data

Rate

Min.

Max.

REQB

LOSTHR

Threshold

220

145

Unit

DS3

mV pk

V_DD/2

V_DD

175

115

V_DD/2

V_DD

STS-1

275

185

115

V_DD/2

V_DD

220

145

V_DD/2

V_DD

Notes

- Lower threshold is 1.5 dB below upper threshold.

- The RLOS alarm is an indication of the absence of an input signal, not a bit error rate indication (independent of the RLOS state). The

device will attempt to recover correct timing data. The RLOS low-to-high transition typically occurs 1dB below the high to low transi-

tion.

Table 6. Analog Loss-of-Signal Thresholds

RECOVERED CLOCK AND DATA TIMING

IN-CIRCUIT TEST CAPABILITY

When pulled low, the ICT pin forces all digital output

buffers (RCLK, RPDATA, RNDATA, RLOS, RLOL pins) to

be placed in a high output impedance state. This feature

allows in-circuit testing to be done on neighboring devices

without concern for XRT7295AT device buffer damage.

An internal pull-up device (nominally 50kΩ) is provided on

this pin therefore, users can leave this pin unconnected

for normal operation. Test equipment can pull ICT low

during in-circuit testing without damaging the device.

This is the only pin for which internal pull-up/pull-down is

provided.

Table 7 and Figure 11 summarize the timing relationships

between the logic signals RCLK, RPDATA, and RNDATA.

The duty cycle is referenced to V /2 threshold level.

RPDATA and RNDATA change on the rising edge of

RCLK and are valid during the falling edge of RCLK. A

positive pulse at R creates a high level on RPDATA and

a low level on RNDATA. A negative pulse at the input

creates a high level on RNDATA and a low level on

RPDATA, and a received zero produces low levels on

both RPDATA and RNDATA.

Rev.1.20

XRT7295AT

TIMING CHARACTERISTICS

Test Conditions: All Timing Characteristics are Measrured with 10pF Loading, -40°C ± T ± +85°C, V

5V ‵ 10%

Symbol

tRCH1RCH2

tRCL2RCL1

tRCHRDV

Parameter

Min

Typ

Max

Unit

Clock Rise Time (10% - 90%)

Clock Fall Time (10% - 90%)

Receive Propagation Delay¹

Clock Duty Cycle

0.6

3.7

Table 7. System Interface Timing Characteristics

tRCHRDV

tRCH1RCH2

tRCL2RCL1

RCLK

(RC)

tRDVRCL

RPDATA

RNDATA

(RD)

tRCLRDX

Figure 11. Timing Diagram for System Interface

BOARD LAYOUT CONSIDERATIONS

Power Supply Bypassing

input pin. Any noise coupled into the XRT7295AT input

directly degrades the signal-to-noise ratio of the input

signal and may degrade sensitivity.

PLL Filter Capacitor

Figure 12 illustrates the recommended power supply

bypassing network. A 0.1µF capacitor bypasses the

The PLL filter capacitor between pins LPF1 and LPF2

must be placedas closeto the chip as possible. The LPF1

and LPF2 pins are adjacent, allowing for short lead

lengths with no crossovers to the external capacitor.

Noise-coupling into the LPF1 and LPF2 pins may

degrade PLL performance.

digital supplies. The analog supply V A is bypassed by

using a 0.1µF capacitor and a shield bead that removes

significant amounts of high-frequency noise generatedby

the system and by the device logic. Good quality,

high-frequency (low lead inductance) capacitors should

be used. Finally, it is most important that all ground

connections be made to a low-impedance ground plane.

Handling Precautions

Receive Input

Although protection circuitry has been designed into this

device, proper precautions should be taken to avoid

exposure to electrostatic discharge (ESD) during

handling and mounting.

The connections to the receive input pin, R , must be

carefully considered. Noise-coupling must be minimized

along the path from the signal entering the board to the

Rev.1.20

XRT7295AT

COMPLIANCE SPECIFICATIONS

0.1µF

D Compliance with AT&T Publication 54014, “ACCU-

NET R T45 Service Description and Interface Spec-

ifications,” June 1987.

GNDA

Sensitive Node

D Compliance with ANSI Standard T1.102-1989,

Shield Bead

XRT7295AT

“Digital Hierarchy - Electrical Interfaces, ” 1989.

D Compliance with Compatibility Bulletin 119,

“Interconnection Specification for Digital

Cross-Connects,” October 1979.

GNDD

GNDC

0.1µF

+5V

D Compliance with CCITT Recommendations G.703

and G.824, 1988.

Notes

D Compliance with TR-TSY-000499, “Transport Sys-

tems Generic Requirements (TSGR): Common Re-

quirements,” December 1988.

Recommended shield beads are the Fair-Rite

2643000101 or the Fair-Rite 2743019446 (surface

mount).

D Compliance with TA-TSY-000253, “Synchronous

Optical Network (SONET) Transport System Gener-

ic Criteria,” February 1990.

Figure 12. Recommended Power Supply

Bypassing Network

Rev.1.20

XRT7295AT

OUTPUTS

RECEIVER

MONITOR

SW DIP-4

RLOS

RLOL

R22

22K

R21

22K

XRT7296

6 4

XRT7295AT

2 4

INPUT

SIGNAL

LLOOP

RLOOP

T3/E3

TAOS

TXLEV

ICT

LOSTHR

REQB

ICT/

RCLK

RNDATA

RPDATA

LLOOP

RLOL

RLOS

RLOOP

DS3,STS-1/E3/

TAOS

R10

RCLK

ICT/

RNDATA

RPDATA

TXLEV

ENCODIS

DECODIS

0.01µF

ENCODIS

DECODIS

R1 50

EXTERNAL

CLOCK

TMC1

TMC2

GND

SW DIP-8

RCLKO

RPOS

RNEG

RNRZ

RCLKO

RPOS

EXCLK

LPF1

TCLK

RECEIVER

OUTPUTS

TCLK

GNDA

GNDC

RNEG

RNRZ

0.1µF

GNDD

TNDATA

TPDATA

TNDATA

TPDATA

LPF2

TTIP

TRING

BT1

TRING

FERRITE BEAD

TTIP

R15

R16

270

PE65966

0.1µF

MRING

0.1µF

MTIP

GNDD

GNDA

TRANSFORMER # PULSE ENGINEERING

PE 65966

DMO

BPV

DMO

BPV

PE 65967 IN SURFACE MOUNT

22µF

TRANSMITER

MONITOR

OUTPUTS

0.1µF

BT2

0.1µF

FERRITE BEAD

FERRITE BEAD # FAIR RITE 2643000101

0.1µF

22µF

Figure 13. Typical Application Schematic

Rev.1.20

XRT7295AT

20 LEAD SMALL OUTLINE J LEAD

(300 MIL JEDEC SOJ)

Rev. 1.00

Seating

Plane

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

MAX

0.145

0.025

0.120

0.014

0.008

0.496

0.292

0.262

0.200

---

3.60

0.64

3.05

0.36

0.20

12.60

7.42

6.65

5.08

---

0.140

0.020

0.013

0.512

0.300

0.272

3.56

0.51

0.30

13.00

7.62

6.91

0.050 BSC

1.27 BSC

0.335

0.030

0.347

0.040

8.51

0.76

8.81

1.02

Note: The control dimension is the inch column

Rev.1.20

XRT7295AT

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-

prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-

scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are

free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary

depending upon a user’s specific application. While the information in this publication has been carefully checked;

no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or

malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly

affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation

receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the

user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-

stances.

Datasheete December 2000

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

Rev.1.20

XRT7295ATIW相关文章

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XRT7295ATIW产品参数

型号:	XRT7295ATIW
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	SOJ
包装说明：	SOJ, SOJ20,.34
针数：	20
Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01
风险等级：	5.64
运营商类型：	STS-1/OC-1
运营商类型（2）：	T-3(DS3)
数据速率：	51840 Mbps
JESD-30 代码：	R-PDSO-J20
JESD-609代码：	e0
长度：	12.8 mm
功能数量：	1
端子数量：	20
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOJ
封装等效代码：	SOJ20,.34
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V
认证状态：	Not Qualified
座面最大高度：	5.08 mm
子类别：	Digital Transmission Interfaces
最大压摆率：	0.111 mA
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
电信集成电路类型：	PCM TRANSCEIVER
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	J BEND
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.52 mm
Base Number Matches：	1

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