YMF715E现货热卖使用介绍供应商报价哪里找芯片批发报价-中国IC网-芯三七

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YMF715E

OPL3-SA3

Preliminary

OPL3 Single-chip Audio System 3

■ OUTLINE

YMF715E-S (OPL3-SA3) is a single audio chip that integrates OPL3 and its DAC, 16bit Sigma-delta

CODEC, MPU401 MIDI interface, joystick port, and a 3D enhanced controller including all the analog

components which is suitable for multi-media application. This LSI is fully compliant with Plug and Play

ISA 1.0a, and supports all the necessary features, i.e. 16bit address decode, more IRQs and DMAs in

compliance with PC’96. This LSI also supports the expandability, i.e. Zoomed Video, Modem and CD-

ROM interface in a Plug and Play manner, and power management (power down, power save, partial

power down, and suspend/resume) that is indispensable with power-conscious application.

■ FEATURES

● Built-in OPL3 (FM-synthesizer)

● Supports Sound Blaster Game compatibility

● Supports Windows Sound System compatibility

● Supports Plug & Play ISA 1.0a compatibility

● Full Duplex operation

● Built-in MPU401 Compatible MIDI I/O port

● Built-in Joystick port

● Built-in the 3D enhanced controller including all the analog components

● Supports multi-purpose pin function

(Support 16-bit address decode, DAC interface for OPL4-ML/ML2, Zoomed Video port, EEPROM

interface, MODEM interface, IDE CD-ROM interface)

● Hardware and software master volume control

● Supports monaural input

● 24 mA TTL bus drive capability

● Supports Power Management(power down, power save, partial power down, and suspend/resume)

● +5V/ +3.3V power supply for digital, 5V power supply for analog.

● 100 pin SQFP package (YMF715E-S)

ꢀꢀThe contents of this catalog are target specifications and are subject to change

ꢀꢀ without prior notice. When using this device, please recheck the specifications.

CORPORATION

YAMAHA

May 21, 1997

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■ PIN CONFIGURATION

YMF715E-S

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

ADFLTR

DVSS

SEL0

SEL1

SEL2

MP0

MP1

MP2

MP3

MP4

1

2

3

4

5

6

7

8

AVSS

AVDD

GP0

GP1

GP2

GP3

GP4

GP5

GP6

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

GP7

MP5

MP6

MP7

MP8

DVSS

RESET

/IOW

/IOR

DVDD

AEN

A11

MP9

DVDD

/VOLUP

/VOLDW

A0

A1

A2

X33O

X33I

X24O

X24I

A10

A9

IRQ3

IRQ5

IRQ7

IRQ9

IRQ10

IRQ11

ꢀꢀꢀꢀ100 pin SQFP Top View

May 21, 1997

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■ PIN DESCRIPTION

ISA bus interface: 36 pins

name

pins

8

I/O

type

TTL

Size

function

D7-0

I/O

I

24mA Data Bus

A11-0

12

1

TTL

-

Address Bus

AEN

I

TTL

Address Bus Enable

Write Enable

Read Enable

Reset

Schmitt

TTL

/IOW

1

I

/IOR

1

I

RESET

IRQ3,5,7,9,10,11

DRQ0, 1, 3

/DACK0, 1, 3

1

I

6

T

I

12mA Interrupt request

12mA DMA Request

3

TTL

3

TTL

-

DMA Acknowledge

Analog Input & Output : 24 pins

name

pins

1

I/O

O

I

type

size

-

function

OUTL

-

Left mixed analog output

Right mixed analog output

Voltage reference input

Voltage reference output

Left AUX1 input

OUTR

-

VREFI

VREFO

AUX1L

AUX1R

AUX2L

AUX2R

LINEL

LINER

MIC

-

O

I

-

I

-

Right AUX1 input

Left AUX2 input

I

-

I

-

Right AUX2 input

Left LINE input

I

-

I

-

Right LINE input

I

-

MIC input

MIN

I

-

Monaural input

TRECL

TRECR

SBFLTL

SBFLTR

SYNSHL

SYNSHR

ADFLTL

ADFLTR

VOCOL

VOCOR

VOCIL

VOCIR

-

Left Treble capacitor

Right Treble capacitor

Left SBDAC filter

Right SBDAC filter

Left SYNDAC sample / hold capacitor

Right SYNDAC sample / hold capacitor

Left input filter

-

Right input filter

O

I

-

Left voice output

-

Right voice output

Left voice input

-

I

-

Right voice input

May 21, 1997

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Multi-purpose pins : 13 pins

name

pins

3

I/O

I+

type

CMOS

TTL

size

-

function

SEL2-0

MP9-0

Refer to “Multi-purpose pins” section

Refer to “multi-purpose pins” section

10

I+/O

2mA

Others : 27 pins

name

pins

4

I/O

IA

I+

O

I+

I

type

-

size

function

GP3-0

GP7-4

RXD

-

Game Port

4

-

Game Port

Schmitt

TTL

Schmitt

CMOS

-

1

-

MIDI Data Receive

MIDI Data Transfer

Hardware Volume (Up)

Hardware Volume (Down)

33.8688 MHz

TXD

1

4mA

/VOLUP

/VOLDW

X33I

1

-

1

-

1

-

X33O

1

O

I

2mA

33.8688 MHz

X24I

1

-

24.576 MHz

X24O

1

O

-

2mA

24.576 MHz

AVDD

DVDD

AVSS

2

-

Analog Power Supply (put on +5.0V)

Digital Power Supply (put on +5.0 V or +3.3V)

Analog GND

3

-

2

-

DVSS

4

-

Digital GND

Total : 100 pins

Note :

I+:

Input Pin with Pull up Resistor

T: TTL-tri-state output pin

Schmitt: TTL-Schmitt input pin

May 21, 1997

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■ BLOCK DIAGRAM

May 21, 1997

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■ FUNCTION OVERVIEW

1. Multi-purpose pin

ꢀ1-1. Multi-purpose function

OPL3-SA3 can support the various functions listed below by programming SEL2-0 pins.

A. 16-bit address decode

B. EEPROM interface

C. Zoomed video port

D. CPU and DAC interface for OPL4-ML/ML2

E. MODEM interface

F. IDE CD-ROM interface

Following table shows what combinations of the above functions are available for each SEL2-0 pins.

SEL

0

16bit Dec. EEPROM

ZV port

OPL4-ML/ML2

-

MODEM

CDROM

-

Remark

Test mode

S/C,C/C(add-in)

S/C (add-in)

Note PC

-

○

(*1)

(*2)

(*3)

1

○

2

-

○

(*4)

3

-

○

4

-

○

(*3)

5

Note PC

6

-

reserved

○

7

M/B, Note PC

Where,

S/C : Sound Card

C/C : Combo Card (Sound and Modem)

M/B : Desktop Mother Board

SEL=0 SEL=1 SEL=2 SEL=3 SEL=4 SEL=5 SEL=6 SEL=7

SEL0 pin

SEL1 pin

SEL2 pin

0

1

0

1

0

1

0

1

0

1

0

1

Notice

*1 : External PAL is needed.

*2 : External wavetable synthesizer (ex.OPL4-ML/ML2) is mixed as analog signal using external

DAC.

*3 : Clock module (ex.MK1420) is used to generate the clock for OPL4-ML/ML2 and it will be

mixed analog signal by having an additional DAC.

*4 : External TTLs (ex.LS138) is needed.

See section 1-2 and 1-3 for implementation detail.

May 21, 1997

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ꢀ1-2. Pin description

SEL=0

SEL=1

/MCS

MIRQ

SEL=2

/MCS

MIRQ

SEL=3

/EXTEN

/SYNCS

SEL=4

/EXTEN

/SYNCS

SEL=5

/MCS

MIRQ

A12

SEL=6

SEL=7

/EXTEN

/SYNCS

A12

MP0

MP1

MP2

MP3

MP4

MP5

MP6

MP7

MP8

MP9

-

ROMCLK ROMCLK ROMCLK BCLK_ZV

ROMCS

ROMDI

ROMDO

/CDCS0

/CDCS1

CDIRQ

CLKO

ROMCS

ROMDI

ROMDO

A12

ROMCS

ROMDI

ROMDO

LRCK_ZV

SIN_ZV

/XRST

A13

A14

A15

BCLK_ML BCLK_ML BCLK_ZV

LRCK_ML LRCK_ML LRCK_ZV

BCLK_ML

LRCK_ML

SIN_ML

CLKO

A13

A14

SIN_ML

CLKO

SIN_ML

CLKO

SIN_ZV

/XRST

A15

ꢀꢀNote : do not select SEL=0 and SEL=6.

ꢀꢀꢀꢀ SEL=0 ; TEST mode

SEL=6 ; reserved

Mutil-purpose pins:

name

I/O function

/MCS

O

I+

O

Chip select output for MODEM chip (COM)

Interrupt request input for MODEM (COM)

Serial data clock output for external EEPROM

Chip select output for external EEPROM

Serial data input for external EEPROM

Serial data output for external EEPROM

Chip select output for IDE CD-ROM (/CS1FX)

Chip select output for IDE CD-ROM (/CS3FX)

Interrupt request input for IDE CD-ROM

Address bus for ISA-bus

MIRQ

ROMCLK

ROMCS

ROMDI

ROMDO

/CDCS0

/CDCS1

CDIRQ

O

I+

O

I+

I

A12 - 15

/EXTEN

/SYNCS

BCLK_ML

LRCK_ML

SIN_ML

CLKO

I+

O

Enable OPL4-ML/ML2 interface

Chip select output for OPL4-ML/ML2

Bit clock input for OPL4-ML/ML2

I+

O

L/R clock input for OPL4-ML/ML2

Serial data input for OPL4-ML/ML2

Master clock output (33.8688MHz)

BCLK_ZV

LRCK_ZV

SIN_ZV

/XRST

I+

O

Bit clock input for Zoomed Video port (I²S)

L/R clock input for Zoomed Video port (I²S)

Serial data input for Zoomed Video port (I²S)

Inverted RESET output

May 21, 1997

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ꢀ1-3. System Block Diagram

ꢀꢀ(1) SEL=1 (Sound Card and Combo Card Add-in)

SD15-8

/ENH

SA2-0

SA15-12

/RESET

AEN

/ENL

RESETDRV

SD7-0

MP0

/MCS

MIRQ

MODEM I/F

}

RESET

/IOW,/IOR

A11-0

MP1

/IOW,/IOR

SA11-0

YMF715E-S

(OPL3-SA3)

D7-0

SD7-0

AUX2L

AUX2R

EEPROM

CLKO

BCO

LRO

DO2

YAC516

RESET

OPL4-ML/ML2

ꢀ 1. External PAL(16V8 etc.)

(i) connect the signal AEN* generated by decoding SA15-12 and AEN to the AEN of OPL3-

SA3.

(ii) generate the /G(enable) signal for Data Bus Buffer (LS245) by decoding the /CDCS1-0 and

SA2-0.

(iii) generate the /RESET signal from RESETDRV.

May 21, 1997

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ꢀ 2. Master Clock

Both 33.8688MHz and 24.576MHz are used or 14.31818MHz and clock module

(ex.MK1420 by Micro Clock) are used.

ꢀ 3. OPL4-ML/ML2

The external DAC (YAC516) is necessary for wavetable upgrade.

ꢀ(2) SEL=2 (Sound Card and Combo Card for Add-in)

RESET

/IOW,/IOR

AEN

MP0

MP1

/MCS

MIRQ

RESETDRV

/IOW,/IOR

AEN

MODEM I/F

}

MP9-6

A11-0

D7-0

SA15-12

SA11-0

YMF715E-S

(OPL3-SA3)

SD7-0

AUX2L

AUX2R

X24I

X33I

EEPROM

CLKO

BCO

LRO

DO2

RESET

XI

YAC516

OPL4-ML/ML2

MK1420

14.31818MHz

ꢀ 1. OPL4-ML/ML2

The external DAC (YAC516) and the clock module (ex.MK1420 by Micro Clock) are

necessary for wavetable upgrade.

ꢀ 2. MK1420

The MK1420 is the clock module that generates all clocks necessary for this chipset . It is by

Micro Clock and its package is SOP8.

May 21, 1997

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ꢀ(3) SEL=3 (Sound Card for Add-in)

SA15-12

AEN*

AEN

RESET

RESETDRV

BCLK_ML

LRCK_ML

SIN_ML

/IOW,/IOR

A11-0

MP6

MP7

MP8

/IOW,/IOR

SA11-0

YMF715E-S

(OPL3-SA3)

D7-0

SD7-0

EEPROM

RESET

/IOW

/IOR

A2-0

D7-0

DO2

LRO

BCO

/IOW,/IOR

SA2-0

OPL4-

ML/ML2

SD7-0

DBDIR

ꢀ 1. 16bit Address Decode

The signal AEN* generated by decoding SA15-12 and AEN needs to be connected to the

AEN of OPL3-SA3.

May 21, 1997

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ꢀ(4) SEL=4 (for Notebook PC)

SA15-12

AEN*

BCLK_ZV

AEN

MP2

MP3

MP4

MP5

MP6

MP7

MP8

AEN

LRCK_ZV

SIN_ZV

ZV Port

}

RESET

/IOW,/IOR

A11-0

RESETDRV

/IOW,/IOR

SA11-0

/XRST

Peripheral

Equipment

YMF715E-S

(OPL3-SA3)

BCLK_ML

LRCK_ML

SIN_ML

D7-0

SD7-0

RESET

/IOW

/IOR

A2-0

D7-0

DO2

LRO

BCO

/IOW,/IOR

SA2-0

OPL4-

ML/ML2

SD7-0

DBDIR

ꢀ 1. 16bit Address Decode

The signal AEN* generated by decoding SA15-12 and AEN needs to be connected to the

AEN of OPL3-SA3.

ꢀ 2. ZV Port and OPL4-ML/ML2 I/F

ZV port is supported by using the internal DAC of OPL3-SA3 that is originally dedicated for

the use of internal OPL3.

(i) either OPL4-ML/ML2 or ZV port is active at a time and simultaneous use is not

possible.

(ii) which function the internal DAC is used for is determined by the SA3 Control

register, index 02h, VZE bit.

May 21, 1997

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ꢀ(5) SEL=5 (for Notebook PC)

RESET

/IOW,/IOR

AEN

MP0

MP1

/MCS

MIRQ

RESETDRV

/IOW,/IOR

AEN

MODEM I/F

ZV Port

}

BCLK_ZV

MP6

LRCK_ZV

SIN_ZV

/XRST

MP5-2

A11-0

D7-0

MP7

SA15-12

SA11-0

YMF715E-S

(OPL3-SA3)

MP8

Peripheral

Equipment

MP9

SD7-0

X24I

AUX2L

AUX2R

X33I

RESET

XI

CLKO

BCO

LRO

DO2

YAC516

OPL4-ML/ML2

MK1420

14.31818MHz

ꢀ 1. Internal DAC

The internal OPL3 and the ZV Port shares the internal DAC, which is very similar to the case

mentioned the previous section.

(i) either internal OPL3 or ZV port is active at a time and simultaneous use is not

possible.

(ii) which function the internal DAC is used for is determined by the SA3 control

register, index 02h, VZE bit.

ꢀ 2. OPL4-ML/ML2

The external DAC (YAC516) and the clock module (ex.MK1420 by Micro Clock) are

necessary for wave table upgrade.

May 21, 1997

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(6) SEL=7 (for Notebook PC, Desktop PC)

RESET

RESETDRV

/IOW,/IOR

AEN

BCLK_ML

LRCK_ML

SIN_ML

MP5-2

A11-0

D7-0

MP6

MP7

MP8

SA15-12

SA11-0

SD7-0

YMF715E-S

(OPL3-SA3)

RESET

/IOW

/IOR

A2-0

D7-0

DO2

LRO

BCO

/IOW,/IOR

SA2-0

OPL4-

ML/ML2

SD7-0

DBDIR

May 21, 1997

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ꢀ2. ISA Interface

OPL3-SA3 supports ISA Plug and Play (PnP) that frees the users from configuring the I/O address,

IRQ and DMA channel. Those system resources are set automatically by the system. However even

when used in Non PnP system, the configuration can be changed with software.

ꢀ2-1. PnP Auto-Configuration mode

OPL3-SA3 has the following I/O port to support the Plug and Play ISA.

Address port:

279h

Write Data Port:

A79h

Relocatable Read Data Port:

203h - 03FFh

The following four Logical Devices are supported by OPL3-SA3.

Logical Device No. 0

Sound Blaster compatible Playback system

16-bit CODEC

(SB Base)

(WSS Base)

(MPU Base)

(AdLib Base)

(CTRL Base)

MPU401

OPL3

OPL3-SA3 control register

Logical Device No. 1

Joy Stick

Logical Device No. 2 (Optional)

MODEM (COM port)

Logical Device No. 3 (Optional)

IDE CD-ROM interface

May 21, 1997

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ꢀ2-2. PnP ISA Configuration Register

OPL3-SA3 has the following Registers defined in the PnP ISA software.

0x00

Card Control

0x22

0x30

LDN=0, SA3 Sound System

0x75

LDN=1, Joy Stick

LDN=2, MODEM

LDN=3, CDROM

Listed below is the register map of card control register and logical device registers. For the detailed

description of each register, please refer to the Plug and Play ISA Specification 1.0a

Card Control Registers

Index

R/W

D7

D6

D5

D4

D3

D2

D1

D0

00h

01h

W

R

Set RD_DATA

Serial Isolation

02h

03h

04h

05h

06h

07h

20h

21h

W

Config Control

Wake [CSN]

R

Resource Data

R

Status

R/W

W

Card Select Number

Logical Device Number

Resource Data Write

W

IKD

RDWE

ꢀRDWE : Resource Data Write Enable

Setting “1” to this bit means the host can download the resources data to EEPROM and

internal SRAM via 20h.

ꢀIKD : Initiation Key Disable

Setting “1” to this bit means OPL3-SA3 should not detect the initiation key in the Wait for

Key state.

May 21, 1997

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Logical Device Number = 0 : SA3 Sound System

30h

60h

61h

62h

63h

64h

65h

66h

67h

68h

69h

70h

71h

72h

73h

74h

75h

R/W

R

Activate

I/O port base address[15..8], Descriptor 0 (SB base)

I/O port base address[7..0], Descriptor 0 (SB base)

I/O port base address[15..8], Descriptor 1 (WSS base)

I/O port base address[7..0], Descriptor 1 (WSS base)

I/O port base address[15..8], Descriptor 2 (AdLib base)

I/O port base address[7..0], Descriptor 2 (AdLib base)

I/O port base address[15..8], Descriptor 3 (MPU base)

I/O port base address[7..0], Descriptor 3 (MPU base)

I/O port base address[15..8], Descriptor 4 (CTRL base)

I/O port base address[7..0], Descriptor 4 (CTRL base)

Interrupt request level select 0 (for IRQ-A)

Interrupt request type select 0 (for IRQ-A)

R/W

R

Interrupt request level select 1 (for IRQ-B)

Interrupt request type select 1 (for IRQ-B)

R/W

DMA channel select 0 (for DMA-A)

DMA channel select 1 (for DMA-B)

Logical Device Number = 1 : Joystick

30h

60h

61h

R/W

Activate

I/O port base address[15..8]

I/O port base address[7..0]

Logical Device Number = 2 : MODEM (Optional)

30h

60h

61h

70h

71h

R/W

R

Activate

I/O port base address[15..8]

I/O port base address[7..0]

Interrupt request level select

Interrupt request type select

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Logical Device Number = 3 : CD-ROM (Optional)

30h

60h

61h

62h

63h

70h

71h

R/W

R

Activate

I/O port base address [15..8], Descriptor 0 (/CDCS0)

I/O port base address [7..0], Descriptor 0 (/CDCS0)

I/O port base address [15..8], Descriptor 1 (/CDCS1)

I/O port base address [7..0], Descriptor 1 (/CDCS1)

Interrupt request level select

Interrupt request type select

ꢀ2-3. Recommended Resource Data

The recommended resource data is the followings.

(1) LDN=0:SA3 Sound System

ꢀ

I/O (SB base): 16bit address decode

Index

Best

Acceptable1

Acceptable2

Acceptable3

I/O

220h

16

240h

16

220-280h

16

<-

Length

Alignment

-

16

<-

I/O (WSS base): 16bit address decode

Index

Best

Acceptable1

Acceptable2

Acceptable3

I/O

530h

8

E80h

8

530-F48h

8

<-

Length

Alignment

-

8

<-

I/O (AdLib base): 16bit address decode

Index

Best

Acceptable1

Acceptable2

Acceptable3

I/O

388h

8

<-

388-3F8h

8

<-

Length

Alignment

-

8

<-

I/O (MPU base): 16bit address decode

Index

Best

Acceptable1

Acceptable2

Acceptable3

I/O

330h

2

300h

2

300-334h

2

<-

Length

Alignment

-

2

<-

I/O (CTRL base): 16bit address decode

Index

Best

Acceptable1

Acceptable2

Acceptable3

I/O

370h

2

100-FFEh

2

<-

Length

Alignment

-

2

<-

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

IRQ-A: high-active, edge-sense

Index

IRQ

Best

10

Acceptable1

7,9,10,11

Acceptable2

5,7,9,10,11

Acceptable3

<-

IRQ-B: high-active, edge-sense

Index

IRQ

Best

5

Acceptable1

5,7

Acceptable2

5,7,9,10,11

Acceptable3

<-

DMA-A: 8bit, count by byte, type-A, B, F

Index

DMA

Best

0

Acceptable1

0,1,3

Acceptable2

0,1,3

Acceptable3

<-

DMA-B: 8bit, count by byte, type-A, B, F

Index

DMA

Best

1

Acceptable1

0,1,3

Acceptable2

0,1,3

Acceptable3

<-

(2) LDN=1:Joystick

ꢀ

I/O (Game Port): 16bit address decode

Index

Best

Acceptable1

Acceptable2

Acceptable3

I/O

201h

1

202h

1

203h

1

204-20Fh

1

Length

Alignment

-

1

(3) LDN=2:MODEM

ꢀ

I/O (/MCS): 16bit address decode

Index

Best

Acceptable1

Acceptable2

Acceptable3

I/O

2F8h

8

100-FF8h

8

<-

Length

Alignment

-

8

-

IRQ: high-active, edge-sense

Index

IRQ

Best

3

Acceptable1

<-

Acceptable2

<-

Acceptable3

<-

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

(4) LDN=3:CD-ROM

ꢀ

I/O (/CDCS0): 16bit address decode

Index

Best

Acceptable1

Acceptable2

Acceptable3

I/O

1E8h

8

100-1F8h

8

<-

Length

Alignment

-

8

<-

I/O (/CDCS1): 16bit address decode

Index

Best

Acceptable1

Acceptable2

Acceptable3

I/O

3EEh

1

306-3F6h

1

<-

Length

Alignment

-

8

<-

IRQ: high-active, edge-sense

Index

IRQ

Best

11

Acceptable1

3,5,7,9,10,11

Acceptable2

<-

Acceptable3

<-

ꢀ2-4. Manual Configuration Mode

When OPL3-SA3 is in the Wait for Key state, it can be changed to the Manual Configuration mode

by sending the following YAMAHA key to Address_Port. The Manual Configuration mode is used

for downloading the resource data to EEPROM and internal SRAM, setting up the OPL3-SA3

without PnP protocol.

YAMAHA Key:

B1h, D8h, 6Ch, 36h, 9Bh, 4Dh, A6h, D3h,

69h, B4h, 5Ah, ADh, D6h, EBh, 75h, BAh,

DDh, EEh, F7h, 7Bh, 3Dh, 9Eh, CFh, 67h,

33h, 19h, 8Ch, 46h, A3h, 51h, A8h, 54h

In the Manual Configuration mode, PnP registers can be accessed by the host without PnP protocol.

Right after OPL3-SA3 is switched to the Manual Configuration mode, set “81h” in CSN register

automatically to put OPL3-SA3 in ‘Sleep’ State. And when “81h” is written to Wake [CSN], it

becomes possible to access to Configuration register of each logical device from the host.

To return from the Manual Configuration mode to PnP auto-configuration mode, the Wait for Key

command should be sent.

Note :

The Manual Configuration mode can not be used in the system with more than one OPL3-SA3’s card

installed in the ISA slot.

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

3. Download Resource data

When OPL3-SA3 is in the Configuration state, the host can download the resources data to EEPROM

and internal SRAM via 20h: Resource Data Write. To switch OPL3-SA3 into configuration mode,

there are two methods.

First method is to use the normal PnP protocol. After CSN was assigned for all ISA cards by PnP soft-

ware, get CSN from CM (configuration manager) and write the CSN to Wake [CSN], then OPL3-SA3

switches into configuration state.

Second method is to use the YAMAHA Key sequence which is described in the Manual Configuration

mode section. After OPL3-SA3 detects YAMAHA key, OPL3-SA3 switches into the Sleep state.

Writing “81h” to Wake [CSN] register changes OPL3-SA3 into Configuration state.

After OPL3-SA3 switches into the Configuration state, download the Resource data to EEPROM and

internal SRAM by using following sequence.

1. Write “01h”(RDWE bit = “1”) to 21h: Resource Data Write Enable register to reset

internal address counter and to enable downloading the data.

2. Write Resource data to 20h: Resource Data Write register until downloading data is

completed.

3. Write “00h” to 21h: Resource Data Write Enable register to disable downloading .

4. External EEPROM

The resource data information of OPL3-SA3 used for PnP auto configuration is stored in external

EEPROM. And either 256 x 16-bit EEPROM or 128 x 16-bit EEPROM, such as 93C55, 93C56,

93C65, 93C66 should be used.

5. Hardware Volume Control

5-1. Hardware Volume up/down/mute Control

Two digital input pins; /VOLUP and /VOLDW can control the master volume of OPL3-SA3.

When /VOLUP is low level, register value of master volume is decremented(-1). When the value

reaches to “00h”(max.0dB), the input signal will not be effective.

When /VOLDW is low level, register value of master volume is incremented(+1). When the value

reaches to “0Fh”(min.-30dB), the input signal will not be effective.

When both of the /VOLUP and /VOLDW are low level simultaneously, volume is muted. When either

/VOLUP or /VOLDW is low level, the previous value becomes effective, and volume is no mute.

5-2. Hardware Volume Interrupt

If configured VEN(Hardware Volume Enable)=1, SA3 Control Register, index 0Ah, D7 bit, when one

of the hardware volume control pins /VOLUP or /VOLDW is asserted or when both are asserted to

request mute, interrupt will be posted in the interrupt channel specified in SA3 Control Register, index

17h, IRQ-A MV or IRQ-B MV bit.

Note that when the muting is in effect, the subsequent mute requests which does not change any

register contents will generate interrrupts. The ignored UP/DOWN requests (UP requests with 0dB

Volume attn., DOWN requests with -30dB) will not generate interrupts.

This bit is cleared upon host’s reading the Master Volume Lch register, SA3 Control Register, index

07h.

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

6. DAC interface

OPL3-SA3 supports two types of DAC interface format. One is the conventional DAC interface format

(very common for the consumer audio product) for OPL4-ML/ML2. Another is the I²S format for

Zoomed Video port. These two types of the formats are shown in the following Fig.6-1, 2.

BCLK

SIN

1

0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

Left Channel

Right Channel

LRCK

Fig.6-1 Conventional DAC Interface Format forOPL4-ML/ML2

BCLK

SIN

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

Left Channel

Right Channel

LRCK

Fig.6-2 I²S Format for Zoomed Video Port

7. 3D Enhanced Control

OPL3-SA3 integrates the 3D enhanced controller including all the analog components in conventional

systems. Wide, bass, and treble controls are available via SA3 control register, index 14h, 15h, 16h.

One of the four 3D Enhancement modes can be selected according to the frequency response of the

speaker. These are controlled by SA3 control register, index 02h D5, D4 bit (YMODE1-0).

YMODE1 YMODE0 3D Enhancement mode

Target speaker

Standard speaker

Small speaker

Speaker size

5 ~ 12cm

3cm

0

1

0

1

0

1

Desktop mode

Notebook PC mode (1)

Notebook PC mode (2)

Hi-Fi mode

Smaller speaker

Hi-Fi speaker

1.5cm

16 ~ 38cm

Following diagram(Fig.7-1) shows the 3D enhanced controller sub-system.

MIC,LINER,

AUX1R,AUX2R,

MIN,SBR,WSS_PBR

Yamaha

Rch

3D Enhanced

Controller

(analog components)

to Hardware

Volume Control

}

Lch

MIC,LINEL,

AUX1L,AUX2L,

MIN,SBL,WSS_PBL

Fig.7-1 3D Enhanced Control Block Diagram

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

ꢀ8. Power Management

Following 4 functionalities are provided for APM(Advanced Power Management) compliance.

(1) Partial Power Down Mode

(2) Power Save Mode

(3) Global Power Down Mode

(4) Suspend/Resume Mode

1bit D/A

WSS-Recording

SCF

1bit A/D

WSS-Playback

SCF

FM

DAC

FM(OPL3)

SB

DAC

Sound Blaster

Clock-

out

MPU

401

Joy-

Stick

Clock

Generator

：Global Power Down

：Power Save 1,2

：Partial Power Down (digital) : 8 digital blocks can be disabled independently.

：Partial Power Down (analog) : 5 analog blocks can be disabled independently.

Fig.8-1 PowerManagement

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

ꢀ8-1. Partial Power Down Mode

Functional blocks comprising OPL3-SA3 which are shown in Fig.8-1, are designed so they can be

disabled independent of each other. SA3 control register, index 12h and 13h, implements these

controls (see section 9-1-5).

ꢀꢀ,ꢀꢀ blocks in the above diagram show those that can be disabled/enabled. Note, however,

the OPL3-SA3 dissipates more power with all these blocks “partial power down”ed than that can be

achieved in “power save mode 2”.

In this mode, master volume is not muted, so all analog input sources and enabled digital sources (i.e.

FM, SB, WSS etc.) can be heard.

Note :

AUX2 inputs are exceptions in this regard since setting FM-DAC at index 13h of SA3 Control

Register inhibits the inputs altogether.

ꢀ8-2. Power Save Mode

SA3 control register, index 01h, PSV and PDX bits, implement these controls.

Clock generator can be controlled under either two options.

(i) Power Save Mode 1 (Clock Generator Control : Disabled (stop)) (PSV=PDX=1)

It is necessary to take some time before clock oscillation to stabilize. Power dissipation of digital

portion becomes about 100uA(typ.), and that of analog portion becomes about 5mA(typ.).

(ii) Power Save Mode 2 (Clock Generator Control : Enabled (crystals keep on oscillating))

(PSV=1, PDX=0)

Leaving power save mode gets the OPL3-SA3 back into function instantly. Power dissipation of

digital portion becomes about 10mA(typ.), and that of analog portion becomes about 5mA(typ.).

In these power save modes, the OUTL/R pins will keep the VREF voltage. During these modes,

master volume is automatically muted, so all audio sources can not heard. After resuming from these

modes, master volume is still muted.

ꢀ8-3. Global Power Down Mode (PDN=PDX=1)

This mode is to minimize power dissipation by stopping all the function of OPL3-SA3. It is

necessary to take some time before clock oscillation to stabilize. Total dissipation becomes about

10uA(typ.).

VREF voltage slowly decays to ground on transition into this mode, and quickly returns to VREF on

transition from this mode. During this mode, master volume is automatically muted, so all audio

sources can not heard. After resuming from this mode, master volume is still muted.

ꢀ

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

8-4. Suspend/Resume Mode

There is no “read only” or “hidden state” registers in OPL3-SA3. This means you can always read

and save these values before power off and can set those values back in registers after reset or power

on to achieve the suspend/resume capability.

Correspondence to APM

APM

ON

OPL3-SA3

ON

WIN(Driver)

BIOS

○

×

APM Enabled

APM Standby

APM Suspend

OFF

Partial Power Down

Power Save(Down)

OFF

○

OFF

Note : Analog Power OFF Feature

OPL3-SA3 has the special feature that the Analog power supplies can be removed from OPL3-SA3. This

feature is independent of digital portion.

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

^ꢀꢀ9. Register description

ꢀ9-1. SA Sound System

ꢀ9-1-1. OPL3

Listed below are the OPL3-L register for AdLib compatibility.

AdLib base

(R)

Status Register port

Address port for Register Array 0

Data port

AdLib base

(W)

AdLib base + 1

AdLib base + 2

AdLib base + 3

(R/W)

(W)

Address port for Register Array 1

Data port

(R/W)

Wavetable upgrade (OPL4-ML/ML2) is available by setting /EXTEN (SEL=3, 4, 7) to “L”. And,

additional I/O ports listed below can also be accessed. In case of SB mode, AdLib base + 2, 3 is write

only registers.

AdLib base + 4

AdLib base + 5

AdLib base + 6

AdLib base + 7

(R)

Status port for Wavetable Register

Address port for Wavetable Register

Data port Wavetable Register

(W)

(R/W)

(R)

Command port for MIDI processor

Status port for MIDI processor

Control port for MIDI processor

(W)

OPL3 Status Register (RO):

Index

xxh

D7

D6

D5

D4

-

D3

-

D2

D1

-

D0

IRQ

FT1

FT2

BUSY

OPL3 Data Register Array 0 (R/W):

Index

D7

D6

D5

D4

D3

D2

D1

D0

00 - 01h

02h

LSI TEST

TIMER 1

TIMER 2

03h

04h

RST

-

MT1

NTS

VIB

MT2

-

ST2

-

ST1

-

08h

20 - 35h

40 - 55h

60 - 75h

80 - 95h

A0 - A8h

B0 - B8h

BDh

AM

EGT

KSR

MULT

KSL

TL

AR

SL

DR

RR

F-NUM (L)

-

KON

RHY

CHR

-

BLOCK

SD

F-NUM (H)

DAM

DVB

BD

CHL

-

TOM

FB

TC

HH

C0 - C8h

E0 - F5h

*

-

*

-

CNT

-

WS

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

OPL3 Data Register Array 1 (R/W)

Index

D7

D6

D5

D4

D3

D2

D1

*

D0

00 - 01h

04h

LSI TEST

CONNECTION SEL

NEW3

MULT

-

05h

-

NEW

20 - 35h

40 - 55h

60 - 75h

80 - 95h

A0 - A8h

B0 - B8h

C0 - C8h

E0 - F5h

AM

VIB

EGT

KSR

KSL

TL

AR

SL

DR

RR

F-NUM (L)

-

*

-

*

-

KON

CHR

-

BLOCK

F-NUM (H)

CHL

-

FB

CNT

-

WS

The bit remarked * indicates that these can be read and written but not effective.

Note :

The wait time of 960ns(min.) is needed before access to OPL3 registers.

ꢀ9-1-2. Sound Blaster Pro compatibility

The followings are the I/Os for Sound Blaster Pro compatibility.

SB base

(R)

OPL3 Status port

SB base

(W)

(R/W)

(W)

(R/W)

(W)

(R/W)

(W)

(R)

OPL3 Address port for Register Array 0

OPL3 Data register

SB base + 1h

SB base + 2h

SB base + 3h

SB base + 4h

SB base + 5h

SB base + 6h

SB base + 8h

SB base + 9h

SB base + Ah

SB base + Ch

SB base + Eh

OPL3 Address port for Register Array 1

OPL3 Data port

SB Mixer Address port

SB Mixer Data port

DSP Reset port

OPL3 Status port

(W)

(R/W)

(R)

OPL3 Address port for Register Array 0

OPL3 Data port

DSP Read Data port

(R)

DSP Write-buffer status port

DSP Write Command/Data port

DSP Read-buffer status port

(W)

(R)

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

ꢀ9-1-2-1. DSP Command

Listed below are the supported commands of DSP defined Sound Blaster Pro compatibility.

CMD Support Function

10h

14h

16h

17h

1Ch

1Fh

20h

24h

2Ch

30h

31h

34h

35h

36h

37h

38h

40h

48h

74h

75h

76h

77h

7Dh

7Fh

80h

90h

91h

98h

99h

A0h

A8h

D0h

D1h

D3h

D4h

D8h

DAh

E1h

o

8bit direct mode digitized sound I/O output

8bit single-cycle DMA mode digitized sound output

8bit to 2bit ADPCM single-cycle DMA mode digitized sound output

8bit to 2bit ADPCM single-cycle DMA mode digitized sound output with ref. byte

8bit auto-init DMA mode digitized sound output

8bit to 2bit ADPCM auto-init DMA mode digitized sound output with ref. byte

8bit direct mode single byte digitized sound input

8bit single-cycle DMA mode digitized sound input

8bit auto-init DMA mode digitized sound input

Polling mode MIDI input

*1

o

*1

o

Interrupt mode MIDI input

o

UART polling mode MIDI I/O

o

UART interrupt mode MIDI I/O

o(*2)

o

UART polling mode MIDI I/O with time stamping

UART interrupt mode MIDI I/O with time stamping

MIDI output

o

Set digitized sound transfer Time Constant

Set DSP block transfer size

o

8bit to 4bit ADPCM single-cycle DMA mode digitized sound output

8bit to 4bit ADPCM single-cycle DMA mode digitized sound output with ref. byte

8bit to 3bit ADPCM single-cycle DAM mode digitized sound output

8bit to 3bit ADPCM single-cycle DMA mode digitized sound output with ref. byte

8bit to 4bit ADPCM auto-init DMA mode digitized sound output with ref. byte

8bit to 3bit ADPCM auto-init DMA mode digitized sound output with ref. byte

Pause DAC for a duration

o

*1

o

*1

o

8bit high-speed auto-init DMA mode digitized sound output

8bit high-speed single-cycle DMA mode digitized sound output

8bit high-speed auto-init DMA mode digitized sound input

8bit high-speed single-cycle DMA mode digitized sound input

Set input mode to mono

o

*1

o

Set input mode to stereo

Pause 8bit DMA mode digitized sound I/O

*1

o

Turn on speaker

Turn off speaker

Continue 8bit DMA mode digitized sound I/O

Get speaker status

*1

o

Exit 8bit auto-init DMA mode digitized sound I/O

Get DSP version number

o

Note :

*1) These commands are performed in state-machine, but they are not effective.

*2) MIDI data can not be received.

Additional undocumented commands are included.

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

ꢀ9-1-2-2. Sound Blaster Pro compatibility Mixer

The table below is the register map of mixer of Sound Blaster Pro compatibility.

Index

00h

D7

D6

D5

D4

D3

D2

D1

D0

Reset Mixer

-

04h

Voice Vol. Lch

-

Voice Vol. Rch

0Ah

-

MIC Vol.

-

Input

Filter

Low Pass

Filter

0Ch

0Eh

-

Input Source

Output

Filter

Stereo

SW

-

22h

26h

28h

2Eh

Master Vol. Lch

MIDI Vol. Lch

CD Vol. Lch

-

Master Vol. R

MIDI Vol. Rch

CD Vol. Rch

Line Vol. Rch

-

Line Vol. Lch

The bit remarked

indicates that these can be read and written but not effective.

The actual value written to the Master Vol., MIDI Vol., CD Vol. and Line Vol. is based on the table

shown below. And when read, actual value cannot be read and written value to each register is read

instead.

Voice Vol. (04h), CD Vol. (28h), Line Vol. (2Eh)

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

mute

-7.5dB

-3.0dB

0dB

mute

-3.0dB

0dB

mute

-28.5dB -22.5dB -16.5dB -10.5dB

0dB

-22.5dB -16.5dB -10.5dB

-7.5dB

-3.0dB

0dB

-16.5dB -10.5dB

-7.5dB

-3.0dB

0dB

-10.5dB

-7.5dB

-3.0dB

0dB

-7.5dB

-3.0dB

0dB

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

MIDI Vol. (26h)

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

mute

-24.0dB -18.0dB -12.0dB

-6.0dB

-3.0dB

+1.5dB

+4.5dB

-3.0dB

+1.5dB

+4.5dB

+1.5dB

+4.5dB

-18.0dB -12.0dB

-6.0dB

-3.0dB

+1.5dB

+4.5dB

-12.0dB

-6.0dB

-3.0dB

+1.5dB

+4.5dB

-6.0dB

-3.0dB

+1.5dB

+4.5dB

Mixer register

SB Mixer

WSS Mixer

MIDI Vol.

CD Vol.

→

AUX2 Vol.

AUX1 Vol.

Line Vol.

→

Line Vol.

default

SB Mixer

Master Vol.

MIDI Vol.

Voice Vol.

CD Vol.

=

(99h)

= +4.5dB (99h)

=

0dB (99h)

mute (11h)

Line Vol.

WSS Mixer

AUX2 Vol.

AUX1 Vol.

Voice Vol.

Line Vol.

= +4.5dB (05h)

=

mute (88h)

mute (80h)

mute (88h)

=

Mono Vol.

mute(MIN, MOUT) (C0h)

SA3 CTRL

Master Vol.

MIC Vol.

= -14dB (07h)

mute (88h)

=

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

ꢀ9-1-3. WSS compatible 16-bit CODEC

The followings are the I/Os for Window Sound System compatibility.

WSS base

(R)

WSS Configuration Register port

WSS Status Register port

WSS base + 3h

WSS base + 4h

WSS base + 5h

WSS base + 6h

WSS base + 7h

(R)

(R/W)

WSS CODEC Index address port

WSS CODEC Index data port

WSS CODEC Status port

WSS CODEC PIO Data port

WSS Configuration Register (RO):

port

+0h

D7

“0”

D6

“0”

D5

D4

D3

D2

D1

D0

IRQ

DMA

This register is used to indicate what resources is assigned and it is read only register.

IRQ:

“0”:

“1”:

“2”:

“3”:

“4”:

No interrupt channel is available

IRQ7 is available

IRQ9 is available

IRQ10 is available

IRQ11 is available

“5”-”7”: reserved.

DMA:

“0”:

“1”:

“2”:

“3”:

No DMA channel is available

DMA0

DMA1

DMA3

“4”-“7”: reserved

Notice)

In the case that CODEC is in Dual DMA mode, only playback DMA channels are valid

and recording DMA channels are ignored.

WSS Status Register (RO):

port D7 D6

+03h SBHC “0”

D5

D4

D3

D2

D1

D0

“04h”

WSS CODEC Direct Registers (R/W):

port

D7

D6

D5

D3

D2

D1

D0

+4h

+5h

INIT

MCE

TRD

Index Address

P/R

Index Data

+6h

+7h

CU/L

CL/R

CRDY

SER

PU/L

PRDY

INT

PIO Data

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

WSS CODEC Indirect Registers (R/W):

Index

D7

D6

D5

D4

D3

D2

D1

D0

00h

01h

LSS1

RSS1

LSS0

RSS0

LMGE

RMGE

-

LIG3

RIG3

LIG2

RIG2

LIG1

RIG1

LIG0

RIG0

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

LX1M

RX1M

LX2M

RX2M

LOM

ROM

FM1

CPIO

XTL1*

COR

MID

LBA5

PUB7

PLB7

OLB

-

LX1G4

LX1G3

LX1G2

LX1G1

LX1G0

-

RX1G4 RX1G3 RX1G2 RX1G1 RX1G0

LX2G4 LX2G3 LX2G2 LX2G1 LX2G0

RX2G4 RX2G3 RX2G2 RX2G1 RX2G0

-

LOA5

LOA4

LOA3

ROA3

CFS2

ACAL

-

LOA2

ROA2

CFS1

SDC

-

LOA1

ROA1

CFS0

CEN

IEN

“0”

LOA0

ROA0

CSL

PEN

-

ROA5

ROA4

FM0

PPIO

XTL0*

PUR

MODE

LBA4

PUB6

PLB6

TE

C/L

S/M

-

DRS

-

ACI

“0”

-

ID3

LBA1

PUB3

PLB3

-

ID2

LBA0

PUB2

PLB2

-

ID1

-

ID0

LBA3

LBA2

PUB4

PLB4

PMCE

-

LBE

PUB0

PLB0

DACZ

HPF*

LLG0

RLG0

TL0

TU0

-

PUB5

PUB1

PLB1

-

PLB5

CMCE

-

LLM

RLM

TL7

TU7

-

LLG4

RLG4

TL4

TU4

-

LLG3

RLG3

TL3

TU3

-

LLG2

RLG2

TL2

TU2

-

LLG1

RLG1

TL1

TU1

-

TL6

TU6

-

TL5

TU5

-

TI

CI

PI

CU

CO

PO

PU

V2

V1

V0

-

CID2

MIA2

-

CID1

MIA1

-

CID0

MIA0

-

MIM

-

MIA3

-

FMT1

-

FMT0

-

C/L

-

S/M

-

CUB7

CLB7

CUB6

CLB6

CUB5

CLB5

CUB4

CLB4

CUB3

CLB3

CUB2

CLB2

CUB1

CLB1

CUB0

CLB0

The bit remarked * indicates that these can be read and written but not effective.

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Mixer default:

02h:AUX1L = 88h (mute)

03h:AUX1R = 88h (mute)

04h:AUX2L = 05h (+4.5dB)

05h:AUX2R = 05h (+4.5dB)

06h:DACL = 80h (mute)

07h:DACR = 80h (mute)

12h:LineL = 88h (mute)

13h:LineR = 88h (mute)

1Ah:MonoIn = C0h (mute)

ꢀ9-1-4. MPU401

The followings are the I/Os for MPU401 compatibility.

MPU base

(R/W)

(R)

MIDI Data port

MPU base +1

MPU base + 1

Status Register port

Command Register port

(W)

ꢀ9-1-5. OPL3-SA3 control register

This register is used to control the additional functions (ex. power management, wide stereo).

CTRL base

(R/W)

Index port

Data port

CTRL base +1

Power Management (R/W):

Index

01h

D7

“0”

D6

“0”

D5

D4

“0”

D3

“0”

D2

D1

D0

ADOWN

PSV

PDN

PDX

ADOWN (Analog Down)... Analog power supplies can be removed from OPL3-SA3, if

ADOWN=“1”.

Set this bit to “0”, before analog power is supplied again.

PSV (power save)...

Setting this bit to “1” makes OPL3-SA3 in power save mode

that is categorized into two types.

Power save mode 1

where PSV=PDX=”1”, clock oscillation is disabled and power

dissipation of digital portion becomes about 100uA(typ.), and that of

analog portion becomes about 5mA(typ.).

Power save mode 2

where PSV=”1” and PDX=0, clock oscillation is active. However

power dissipation of digital portion becomes about 10mA(typ.), and

that of analog portion becomes about 5mA(typ.).

PDN (Power down)...

Setting this bit to “1” makes in power down mode.

PDX (Oscillation stop)... Setting this bit to “1” makes the clock oscillation halt.

default : 00h

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Notice)

1) Set D7, D6, D4 and D3 bits to “0”.

2) In the power save modes 1, 2, the OUTL/R pins will keep the VREF voltage. In the power down

mode, VREF voltage slowly decays to ground on transition into this mode, and quickly returns to

VREF on transition from this mode. During these modes (power save/down), master volume is

automatically muted, so all audio sources cannot be heard. After resuming these modes, master

volume is still muted.

3) The Joystick portion must be re-initialized by writing any value to the Joystick port after resuming

from the power down/save mode.

System control (R/W):

Index

02h

D7

D6

-

D5

D4

D3

-

D2

D1

D0

SBHE

YMODE1 YMODE0

IDSEL1 IDSEL0

VZE

SBHE...

When AT-bus is used, set to “0” and set to “1” in case of XT-bus.

3D Enhancement mode according to the application can be selected

by these two bits as follows.

YMODE1-0...

YMODE1

YMODE0

3D Enhancement mode

Desktop mode

0

1

0

1

0

1

Notebook PC mode (1)

Notebook PC mode (2)

Hi-Fi mode

IDSEL1, IDSEL0... These two bits specify the DSP version of Sound Blaster compatible

portion.

The different return value of DSP command E1h (Get DSP version

number) of Sound Blaster Pro is got by these bits in.

1st byte

2nd byte

IDSEL1

IDSEL0

(major ver) (minor ver)

0

1

0

1

0

1

03h

02h

01h

00h

01h

05h

00h

VZE...

I²S audio format can be fed to BCLK_ZV, LRCK_ZV, SIN_ZV pins

of OPL3-SA3 by setting this bit to “1” regardless of the /EXTEN,

when Zoomed Video port is in use.

default : 00h

Notice)

Input signals, BCLK_ZV and LRCK_ZV pins which appear on SEL=4 or 5 mode, should be

oscillated, when VZE=1.

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Interrupt Channel configuration (R/W):

Index

D7

D6

D5

D4

D3

D2

D1

D0

IRQ-B

MPU

IRQ-A

MPU

OPL3

SB

WSS

OPL3

SB

WSS

There are four devices (WSS (Windows Sound System CODEC), SB (Sound Blaster

compatible portion), OPL3, MPU (MPU401)) that can be an interrupt source. This

register specifies what interrupt source is routed to two physical interrupt (IRQA and

IRQB) of OPL3-SA3. The device written to ”1” is assigned to the corresponding interrupt.

And by writing all “1” to upper or lower half byte, it is possible to share all interrupt

sources to a single physical interrupt line.

default : 69h

IRQ-A: WSS + OPL3

IRQ-B: SB + MPU401

Notice)

Do not assign a device to both IRQA and IRQB.

Interrupt (IRQ-A) status (RO):

Index

04h

D7

-

D6

D5

D4

D3

SB

D2

TI

D1

CI

D0

PI

MV

OPL3

MPU

This register is the status register that indicates which is the interrupt source of IRQA.

When an interrupt occurs, the corresponding bit becomes “1” and its flag (except MV bit)

is cleared when the interrupt routine is completed. This register is not cleared by writing

to this register.

MV...

Hardware Volume Interrupt Flag : If configured VEN=1(index 0Ah, D7

bit), the interrupt occurs when either /VOLUP or /VOLDW is low level or

when both are low level to request mute. The interrupt will be posted in

the IRQ-A channel, if IRQ-A MV=1 (index 17h, D4 bit).

Note that when the muting is in effect, the subsequent mute requests which

does not change any register contents will generate interrrupts. The

ignored UP/DOWN requests (UP requests with 0dB Volume attn.,

DOWN requests with -30dB) will not generate interrupts.

This bit is cleared upon host's reading the Master Volume Lch register at

index 07h.

OPL3...

Internal FM-synthesizer Timer Flag : Note that this flag will become

undefined for the configurations (SEL=3,4,7) using external synthesizer

(i.e. OPL4-ML/ML2).

MPU...

SB...

TI...

MPU401 Interrupt Flag

Sound Blaster compatible Playback Interrupt Flag

Timer Flag of CODEC

CI...

Recording Flag of CODEC

PI...

Playback Flag of CODEC

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Interrupt (IRQ-B) status (RO):

Index

05h

D7

-

D6

D5

D4

D3

SB

D2

TI

D1

CI

D0

PI

MV

OPL3

MPU

This register is the status register that indicates which is the interrupt source of IRQB.

When an interrupt occurs, the corresponding bit becomes “1” and its flag (except MV bit)

is cleared when the interrupt routine is completed. This register is not cleared by writing

to this register.

MV...

Hardware Volume Interrupt Flag : If configured VEN=1(index 0Ah, D7

bit), the interrupt occurs when either /VOLUP or /VOLDW is low level or

when both are low level to request mute. The interrupt will be posted in

the IRQ-B channel, if IRQ-B MV=1 (index 17h, D5 bit).

Note that when the muting is in effect, the subsequent mute requests which

does not change any register contents will generate interrrupts. The

ignored UP/DOWN requests (UP requests with 0dB Volume attn.,

DOWN requests with -30dB) will not generate interrupts.

This bit is cleared upon host's reading the Master Volume Lch register at

index 07h.

OPL3...

Internal FM-synthesizer Timer Flag : Note that this flag will become

undefined for the configurations (SEL=3,4,7) using external synthesizer

(i.e. OPL4-ML/ML2).

MPU...

SB...

TI...

MPU401 Interrupt Flag

Sound Blaster compatible Playback Interrupt Flag

Timer Flag of CODEC

CI...

Recording Flag of CODEC

PI...

Playback Flag of CODEC

DMA configuration (R/W):

Index

D7

D6

D5

D4

D3

-

D2

SB

D1

D0

DMA-B

WSS-R WSS-P

DMA-A

WSS-R WSS-P

-

SB

There are three devices (WSS-P (Windows Sound System CODEC playback), WSS-R

(Windows Sound System CODEC recording) , SB(Sound Blaster compatible playback))

that may use a DMA channel. However 2 DMA channels (DMAA and DMAB) are

available at maximum, this register specifies which device is routed to the physical DMA

channels. And the device written to ”1” is assigned to the corresponding DMA channel.

default : 61h

DMA-A: WSS-P

DMA-B: WSS-R + SB

Notice)

Do not assign a device to both DMA-A and DMA-B.

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Master Volume Lch (R/W):

Index

07h

D7

D6

-

D5

-

D4

-

D3

D2

D1

D0

MVLM

MVL3

MVL2

MVL1

MVL0

This register specifies the master volume of left channel.

MVLM...

Setting to “1” to this bit makes Master Volume Left Channel muted.

These bits determine the attenuation level of Master Volume Left

Channel by -2dB step. When all bits are set to “0”, volume is maximum

(0dB) and when all bits are set to “1”, volume is minimum (-30dB).

MVL3-0...

default : 07h (-14dB)

Notice)

During the power on reset and power down/save mode, master volume is automatically

muted, so all audio sources can not be heard. In resuming from power down/save mode, it is

still muted.

Master Volume Rch (R/W):

Index

08h

D7

D6

-

D5

-

D4

-

D3

D2

D1

D0

MVRM

MVR3

MVR2

MVR1

MVR0

This register specifies the master volume of right channel.

MVRM...

Setting to “1” to this bit makes Master Volume Right Channel muted.

These bits determine the attenuation level of Master Volume Right

Channel by -2dB step. When all bits are set to “0”, volume is maximum

(0dB) and when all bits are set to “1”, volume is minimum (-30dB).

MVR3-0...

default : 07h (-14dB)

Notice)

During the power on reset and power down/save mode, master volume is automatically

muted, so all audio sources can not be heard. In resuming from power down/save mode, it is

still muted.

MIC Volume (R/W):

Index D7

09h MICM

D6

-

D5

-

D4

D3

D2

D1

D0

MCV4

MCV3

MCV2

MCV1

MCV0

This register specifies the master volume of MIC.

MICM...

Setting to “1” to this bit makes Mic Volume muted.

MCV4-0...

These bits determine the gain level of Mic volume by -1.5dB step. When

all bits are set to “0”, volume is maximum(+12dB) and when all bits are

set to “1”, volume is minimum (-34.5dB).

default : 88h

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Miscellaneous:

Index

0Ah

D7

D6

-

D5

-

D4

D3

D2

D1

D0

VEN

MCSW

MODE

VER2

VER1

VER0

VEN...

This bit enables the hardware volume control. Default is VEN=“1”.

MCSW...

This bit determines whether Rch of Mic input or loopback of monaural

output is connected to A/D. This will be useful to support the echo

cancellation. When “0” is set to this bit, Rch of Mic input is selected.

This bit indicates the SB or WSS mode. If MODE=0, it is the SB mode.

This bit is read only.

MODE...

VER2-0...

These bits indicate the version of OPL3-SA3 and read only (VER2=“1”,

VER1=“0”, VER0=“0”).

default : 84h

WSS DMA Base counter (R/W):

Index

D7

D6

D5

D4

D3

D2

D1

D0

0Bh

0Ch

Playback Base Counter (Low)

Playback Base Counter (High)

0Dh

0Eh

Recording Base Counter (Low)

Recording Base Counter (High)

These registers are to load the value to WSS DMA base counter and read out the present

value. Initial value is FFh.

In case of loading the value, both high and low bytes are loaded to internal DMA counter

when the high byte is written. The value set to this register is “(the number of transfer

byte) -1” that is same as WSS CODEC indirect register 0Eh, 0Fh, 1Eh and 1Fh.

When read these registers, the present value of DMA base counter is read out.

These registers are used mainly to support the suspend/resume feature that is very

important for Notebook PC application.

WSS Interrupt Scan out/in (R/W):

Index

0Fh

D7

-

D6

-

D5

-

D4

-

D3

-

D2

D1

D0

STI

SCI

SPI

Use the bits in this register to set WSS interrupt-flags(WSS CODEC indirect Register, index

18h, D6-D4 bits).

STI...

“1” in this bit means TI=“1” and corresponding IRQ active.

“1” in this bit means CI=“1” and corresponding IRQ active.

“1” in this bit means PI=“1” and corresponding IRQ active.

SCI...

SPI...

default : 00h

Notice)

To make IRQ active, it is necessary to set “1” to WSS CODEC indirect register index 0Ah

IEN bit.

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Sound Blaster compatibility Internal State Scan out/in (R/W):

Index

10h

D7

D6

-

D5

-

D4

-

D3

SS

D2

D1

SE

D0

SBPDA

SM

SBPDR

SBPDA...

Sound Blaster Power Down Acknowledgment: “1” in SBPDA acknowledges

that OPL3-SA3 is ready for scanning internal state data in/out or for power

down operation. This flag is read-only.

SS...

Scan Select : Set “1” in this bit when reading or writing internal state.

Set “0” for normal operation.

SM...

Scan Mode : Setting “1” in this bit means the internal state’s are read(out).

Set “0” for write(in).

SE...

Scan Enable : “1” to “0” transition in this bit clocks the shifting internal state

scan data out 1-bit at a time.

SBPDR...

Sound Blaster Power Down Request : “1” in this bit inhibits further DMA

requests and have the internal state begin shutdown procedure. “1” in

SBPDA signals the shutdown procedure completion.

default : 00h

Sound Blaster compatibility Internal State Scan Data (R/W):

Index

11h

D7

D6

D5

D4

D3

D2

D1

D0

SCAN DATA

SCAN DATA... Data port for internal state scan data in/out.

default : 00h

Notice)

The Sound Blaster compatibility internal state scan out/in sequence are shown in the

following Fig.9-1.

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

i) Scan Out

ii) Scan In

: not ready for scanning

internal state data

: not ready for scanning

internal state data

SBPDA=0

: inhibit further DMA,

internal state shutdown

: inhibit further DMA,

internal state shutdown

SBPDR=1

SBPDA=1

SBPDR=1

SBPDA=1

: ready for scanning

internal state data

: ready for scanning

internal state data

: internal state read out

: reading internal state

: internal state write in

: writing internal state

SM=1

SS=1

SM=0

SS=1

: internal state

scan data in

: shifting internal state

SE=1→0

Scan Data (Write)

scan data out 1-bit at a time

: shifting internal state

SE=1→0

scan data in 1-bit at a time

8 times

N times

: internal state

N times

Scan Data (Read)

scan data out

Suspend Prepareration

SM=0

SS=0

SBPDR=0

Resume Completion

N=29 byte (Total Scan Data=228 bit (28 byte×8+4bit))

Fig. 9-1 Sound Blaster compatibility Internal State Scan out/in Sequence

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Digital Block Partial Power Down (R/W):

Index

12h

D7

D6

D5

D4

D3

D2

D1

SB

D0

JOY

MPU

MCLKO

FM

WSS_R WSS_P

PnP

This register specifies the partial power management of the digital portion. This function is

to spare power dissipation in unneeded blocks.

JOY...

Setting this bit to “1” makes the Joystick portion in power down mode. Note

that the Joystick portion must be re-initialized by writing any value to the

Joystick port after resuming from the Joystick portion power down mode.

Setting this bit to “1” makes the MPU401 portion in power down mode.

when set to “1”, Master Clock(33.8688MHz) is disable, which appears on

the pin MP9(SEL=1,3,4,7).

MPU...

MCLKO

when set to “0”, normal operation is active.

FM...

Setting this bit to “1” makes the internal FM(OPL3) portion in power down

mode.

WSS_R...

WSS_P...

SB...

Setting this bit to “1” makes the WSS recording portion in power down

mode.

Setting this bit to “1” makes the WSS playback portion and the digital

loopback portion in power down mode.

Setting this bit to “1” makes the Sound Blaster compatible portion in power

down mode.

PnP...

Setting this bit to “1” makes the PnP portion in power down mode.

default : 00h

Analog Block Partial Power Down (R/W):

Index

13h

D7

-

D6

-

D5

-

D4

D3

D2

D1

D0

FMDAC

A/D

D/A

SBDAC

WIDE

This register specifies the partial power management of the analog portion. The respective

outputs of the blocks which are to be disabled should be muted beforehand.

FMDAC...

Setting this bit to “1” makes the FMDAC portion for the internal FM(OPL3)

or external synthesizer(OPL4-ML/ML2) or ZV port etc. in power down

mode. AUX2 should be muted via register before setting the FMDAC

portion to power down.

A/D...

D/A...

Setting this bit to “1” makes the A/D portion for the WSS recording in

power down mode.

Setting this bit to “1” makes the D/A portion for the WSS playback in power

down mode. WSS CODEC indirect register, index 06h and 07h, LOM and

ROM bits must be “1”, before doing this.

SBDAC...

WIDE...

Setting this bit to “1” makes the SBDAC portion in power down mode. SB

master volume should be muted via register before setting the SBDAC

portion to power down.

Setting this bit to “1” makes the Wide Stereo(3D Enhanced Control) portion

in power down mode. The 3D Enhanced parameter registers at index 14, 15,

and 16h must be 00h, when doing this.

default : 00h

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Notice)

In the partial power down mode, master volume is not muted, so all analog input sources and

enabled digital sources (i.e. FM, SB, WSS etc.) can be heard. Note that AUX2 inputs are

exceptions in this regard since setting FMDAC bit inhibits the inputs altogether.

3D Enhanced control(WIDE) (R/W):

Index

14h

D7

-

D6

D5

D4

D3

-

D2

D1

D0

WIDER2 WIDER1 WIDER0

WIDEL2 WIDEL1 WIDEL0

This register specifies the wide level of the 3D enhanced control.

WIDER2-0...

WIDEL2-0...

default:00h

These bits determine the wide level of 3D enhanced control on Right

Channel by 8 step (if WIDER2-0=0, 0%, and WIDER2-0=7, 100%).

These bits determine the wide level of 3D enhanced control on Left

Channel by 8 step (if WIDEL2-0=0, 0%, and WIDEL2-0=7, 100%).

3D Enhanced control(BASS) (R/W):

Index

15h

D7

-

D6

D5

D4

D3

-

D2

D1

D0

BASSR2 BASSR1 BASSR0

BASSL2 BASSL1 BASSL0

This register specifies the bass level of the 3D enhanced control.

BASSR2-0...

BASSL2-0...

default : 00h

These bits determine the bass level of 3D enhanced control on Right

Channel by 1.5dB step(Max. 10.5dB).

These bits determine the bass level of 3D enhanced control on Left

Channel by 1.5dB step(Max. 10.5dB).

3D Enhanced control(TREBLE) (R/W):

Index

16h

D7

-

D6

D5

D4

D3

-

D2

D1

D0

TRER2 TRER1 TRER0

TREL2

TREL1

TREL0

This register specifies the treble level of the 3D enhanced control.

TRER2-0...

TREL2-0...

default : 00h

Notice)

These bits determine the treble level of 3D enhanced control on Right

Channel by 1.5dB step(Max. 10.5dB).

These bits determine the treble level of 3D enhanced control on Left

Channel by 1.5dB step(Max. 10.5dB).

The 3D Enhanced control parameter registers at index 14h, 15h and 16h must be 00h, when

doing the Wide Stereo portion in power down mode (setting SA3 control register, index 13h,

WIDE bit to “1”).

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Hardware Volume Interrupt Channel Configuration (R/W):

Index

17h

D7

-

D6

-

D5

D4

D3

-

D2

*

D1

*

D0

*

IRQ-B MV IRQ-A MV

The Hardware Volume can source interrupt. This register indicates which interrupt

channel will be used. If IRQ-A MV=“1”, assigned to IRQ-A.

default : 00h

Notice)

Writing to the other bit positions is invalid, though the bits remarked * (D2-D0) will

retain written values. D3, D6 and D7 will always returns “0” when read.

Multi-purpose Select Pin Status (RO):

Index

18h

D7

”1”

D6

D5

D4

D3

-

D2

-

D1

-

D0

“0”

SEL2

SEL1

SEL0

This is a status register that indicates the state of multi-purpose pin.

SEL2-0...

The state of SEL2-0 pins is reflected to these bits. The multi-purpose

function of YMF715E (OPL3-SA3) can be confirmed by reading the bits.

These bits are read only.

default : (1xxx0000)_b

ꢀ9-2. Joystick

port

D7

D6

D5

D4

D3

D2

D1

D0

xxh

JBB2

JBB1

JAB2

JAB1

JBCY

JBCX

JACY

JACX

JACX... Joystick A, Coordinate X

JACY... Joystick A, Coordinate Y

JBCX... Joystick B, Coordinate X

JBCY... Joystick B, Coordinate Y

JAB1... Joystick A, Button 1

JAB2... Joystick A, Button 2

JBB1... Joystick B, Button 1

JBB2... Joystick B, Button 2

Notice)

The Joystick portion must be re-initialized by writing any value to the Joystick port after resuming

from the power down/save or the Joystick portion power down mode.

ꢀ9-3. MODEM

The following pins are for MODEM interface with PnP supported.

/MCS... chip select (eight consecutive byte I/O)

MIRQ... interrupt signal

And MIN is the analog input to mix the telephone line.

MIN...

analog input

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

ꢀ9-4. CD-ROM

The following pins are for IDE CD-ROM interface with PnP supported.

/CDCS0...chip select for CD-ROM

/CDCS1...chip select for CD-ROM

CDIRQ... interrupt signal

Other signals needed for CD-ROM must be generated by the external PALs, which is described in

section 1-3.

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

■ Electrical Characteristics

ꢀAbsolute Maximum Ratings

Item

Power Supply Voltage (Analog/Digital)

Input Voltage

Symbol

V_DD

Minimum

V_SS-0.5

V_SS-0.3

-20

Maximum

V_SS+7.0

V_DD+0.5

V_DD+0.3

20

Unit

V

V_IN

V

Output Voltage

V_OUT

I_IN

V

Input Current

mA

℃

Storage Temperature

T_STG

-50

125

ꢀNote : V_DD=DV_DD=AV_DD, V_SS=DV_SS=AV_SS=0[V]

ꢀRecommended Operating Conditions

Item

(Analog)

Symbol

AV_DD

DV_DD

AV_DD

DV_DD

T_OP

Min.

4.75

3.00

0

Typ.

5.00

3.30

25

Max.

5.25

3.60

70

Unit

V

Power Supply 1

5.0V Spec.

(Digital)

(Analog)

(Digital)

V

Power Supply 2

3.3V Spec.

V

℃

Operating Ambient Temperature

ꢀNote : DV_SS=AV_SS=0[V]

ꢀDC Characteristics 1 (DV_DD= 5.0±0.25[V])

Item

Symbol

Condition

Min.

2.0

Typ.

Max. Unit

V

TTL-Input Pins

V_IH1

V_IL1

Except

High Level Input Voltage 1

Low Level Input Voltage 1

CMOS-Input Pins

schmitt inputs

0.8

V

V_IH2

V_IL2

V_t-

V_t+

V_h1

V_h2

I_L

0.7DV_DD

V

High Level Input Voltage 2

Low Level Input Voltage 2

Schmitt Vt- (H to L)

Schmitt Vt+ (L to H)

Schmitt Hysteresis

0.2DV_DD

1.5

0.8

1.3

0.3

0.1

-10

V

2.1

V

*1

V

*2

V

Input Leakage Current

Input Capacitance

V_IN=DV_SS, DV_DD

10

^μA

pF

k ^Ω

C_I

R_U1

R_U2

R_U3

RXD

20

30

50

100

200

400

Pull up Register

GP7 ~ 4

Otherwise

100

200

TTL-Output Pins

V_OH1

V_OL1

I_OHL1

I_OHL2

I_OHL3

I_OHL4

2.4

V

High Level Output Voltage 1

Low Level Output Voltage 1

TTL Output Current

*3

0.4(0.5)

V

D7 ~ 0 pins *3

16(24)

mA

IRQn, DRQn pins *3 8(12)

TXD pin

4

2

MP9 ~ 0 pins

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Item

Symbol

Condition

I_OH=2mA

Min.

0.8DV_DD

-10

Typ.

Max. Unit

V

CMOS Output pins

V_OH2

V_OL2

O_L

High Level Output Voltage 2

Low Level Output Voltage 2

Output Leakage Current

Output Capacitance

I_OL=2mA

0.4

10

V

^μA

pF

Hi_Z:V_IN=DV_SS, DV_DD

C_O

ꢀNote : DV_SS=AV_SS=0[V], T_OP=0~70℃, AV_DD=5.0[V]

*1 : Applicable to schmitt input pins without /VOLUP, /VOLDW.

*2 : Applicable to /VOLUP and /VOLDW pins.

*3 : When V_OL1=max. 0.5V, the value into the brackets is specified at I_{OHL1, 2}

.

ꢀDC Characteristics 2 (DV_DD= 3.3±0.30[V])

Item

Symbol

Condition

Min.

2.0

Typ.

Max. Unit

V

TTL-Input Pins

V_IH1

V_IL1

Except

High Level Input Voltage 1

Low Level Input Voltage 1

CMOS-Input Pins

schmitt inputs

0.8

V

V_IH2

V_IL2

V_t-

V_t+

V_h

0.7DV_DD

V

High Level Input Voltage 2

Low Level Input Voltage 2

Schmitt Vt- (H to L)

Schmitt Vt+ (L to H)

Schmitt Hysteresis

Input Leakage Current

Input Capacitance

0.2DV_DD

1.5

0.8

1.3

V

2.2 *

V

0.3 *

-10

V

I_L

V_IN=DV_SS, DV_DD

10

^μA

pF

k ^Ω

C_I

R_U1

R_U2

R_U3

RXD

20

30

50

100

200

400

Pull up Register

GP7 ~ 4

Otherwise

100

200

TTL-Output Pins

V_OH1

V_OL1

I_OHL1

I_OHL2

I_OHL3

I_OHL4

2.4

V

High Level Output Voltage 1

Low Level Output Voltage 1

TTL Output Current

0.4

V

D7 ~ 0 pins

2 *

2

mA

IRQn, DRQn pins

TXD pin

MP9 ~ 0 pins

CMOS Output pins

V_OH2

V_OL2

O_L

I_OH=2mA

0.8DV_DD

-10

V

High Level Output Voltage 2

Low Level Output Voltage 2

Output Leakage Current

Output Capacitance

I_OL=2mA

0.4

10

Hi_Z:V_IN=DV_SS, DV_DD

^μA

pF

C_O

ꢀNote : DV_SS=AV_SS=0[V], T_OP=0~70℃, AV_DD=5.0[V]

The specifications marked “*” are different from the value at DV_DD= 5.0±0.25[V].

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

AC Characteristics

CPU Interface & DMA BUS Cycle :Fig.1,2,3,4,5,6,7,8

Item

Symbol

t_AKS

t_AKH

t_AS

Min.

50

Typ.

Max. Unit

/DACK inactive to /IOW, /IOR falling edge

/DACK active from /IOW, /IOR rising edge

Address set up to /IOW, /IOR active

Address hold to /IOW, /IOR inactive

/IOW Write Pulse Width

ns

10

40

t_AH

10

t_WW

t_WDS

t_WDH

t_RW

90

Write Data set up to /IOW active

Write Data hold to /IOW inactive

/IOR Read Pulse Width

20

10

90

Read Data access time

t_ACC

t_RDH

t_DGH

t_SF

80

20

ns

Read Data hold from /IOR inactive

DRQ hold from /IOW, /IOR falling edge

/DACK set up to /IOW, /IOR falling edge

/DACK hold to /IOW, /IOR rising edge

Time between rising edge of /IOW, /IOR to next

falling edge of /IOW, /IOR

0

25

t_HR

t_NX

100

ns

Valid Address from /SYNCS or /MCS or /CDCS1-0

/SYNCS or /MCS or /CDCS1-0 hold to Valid Address

RESET Pulse Width

t_EX1

t_EX2

t_RST

70(90) * ns

^μs

90

ꢀNote : DV_SS=AV_SS=0[V], T_OP=0~70℃, DV_DD=5.0±0.25[V] or 3.3±0.30[V], AV_DD=5.0[V]

*... The value into the brackets is specified at DV_DD=3.3±0.30[V].

Serial Audio (Zoomed Video) Interface Input :Fig.9

Item

BCLK Cycle

Symbol

f_BCK

Condition

Min.

32fs

40

Typ.

48fs

50

Max. Unit

64fs

60

kHz

%

BCLK Duty

D_BCLK

t_LRH

BCLK↑/LRCK

BCLK↑/SIN

LRCK Hold Time

SIN Set up Time

SIN Hold Time

CLKO Frequency

CLKO Duty

-120

20

120

ns

t_DS

ns

t_DH

20

ns

f_CLKO33

D_CLKO33

33.8688

50

MHz

%

f₃₃=50%

40

60

ꢀNote : DV_SS=AV_SS=0[V], T_OP=0~70℃, DV_DD=5.0±0.25[V] or 3.3±0.30[V], AV_DD=5.0[V]

Duty Search Point is 1/2 DV_DD

.

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Miscellaneous

Item

Symbol

f₃₃

Condition

Min.

40

Typ.

Max. Unit

MHz

Master Clock Frequency

(X’tal 33) Duty

Master Clock Frequency

(X’tal 24) Duty

Power Consumption 1

(Normal)

*

33.8688

D_f33

f₂₄

50

24.5760

50

60

%

MHz

%

D_f24

P_OP1

40

60

50

60

35

DV_DD=5.0±0.25[V]

AV_DD=5.0±0.25[V]

DV_DD=3.3±0.30[V]

DV_DD=5.0±0.25[V]

AV_DD=5.0±0.25[V]

DV_DD=3.3±0.30[V]

DV_DD=5.0±0.25[V]

AV_DD=5.0±0.25[V]

DV_DD=3.3±0.30[V]

DV_DD=5.0±0.25[V]

AV_DD=5.0±0.25[V]

DV_DD=3.3±0.30[V]

DV_DD=5.0±0.25[V]

AV_DD=5.0±0.25[V]

DV_DD=3.3±0.30[V]

40

mA

^μA

mA

^μA

mA

^μA

50

P_OP2

25

Power Consumption 2

(Power Save 1)

100

5

80

Power Consumption 3

(Power Save 2)

10

5

7

Power Consumption 4

(Partial Power Down)

20

15

10

Power Consumption 5

(Power Down)

10

40

10

30

0

10

Note : DV_SS=AV_SS=0[V], T_OP=0~70℃

Duty Search Point is 1/2 DV_DD

.

*... DV_DD= 5.0±0.25[V] or 3.3V±0.30[V], AV_DD= 5.0±0.25[V]

Power Save1 : SA3 Control Register, index 01h, PSV=PDX=1

Power Save2 : SA3 Control Register, index 01h, PSV=1, PDX=0

Partial power down : SA3 Control Register, index 12h=FFh, index 13h=1Fh

Power Down : SA3 Control Register, index 01h, PDN=PDX=1

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

I/O Write Cycle

t_AKS

t_AKH

/DACK3,1,0

t_AS

t_AH

(A15-12)

A11-0

Valid

t_WW

/IOW

D7-0

t_WDS

t_WDH

Fig.1

I/O Read Cycle

t_AKS

t_AKH

/DACK3,1,0

t_AS

t_AH

(A15-12)

A11-0

Valid

t_RW

/IOR

D7-0

t_ACC

t_RDH

Valid

Fig.2

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

8bit Mono & ADPCM DMA Write Cycle

t_DGH

DRQ3,1,0

/DACK3,1,0

t_SF

t_WW

t_HR

/IOW

D7-0

t_WDS

t_WDH

Fig.3

8bit Mono & ADPCM DMA Read Cycle

t_DGH

DRQ3,1,0

/DACK3,1,0

t_SF

t_RW

t_HR

/IOR

t_ACC

t_RDH

D7-0

Valid

Fig.4

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

8bit Stereo or16bit Mono DMA Cycle

DRQ3,1,0

/DACK3,1,0

t_NX

/IOW,/IOR

Left/Low

Byte

Right/High

Byte

D7-0

Fig.5

16bit Stereo DMA Cycle

DRQ3,1,0

/DACK3,1,0

/IOW,/IOR

t_NX

Left/Low

Byte

Left/High

Byte

Right/Low

Byte

Right/High

Byte

D7-0

Fig.6

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

External Interface (External Synthesizer, CD ROM, Modem)

(A15-12)

Valid

A11-0

t_EX1

t_EX2

/SYNCS

or

/CDCS1,0

or

/MCS

Fig.7

Reset Pulse Width

t_RST

RESET

Fig.8

Serial Audio Interface

1/f_BCK

BCLK

t_DH

t_DS

SIN

t_LRH

LRCK

Fig.9

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Analog Characteristics

Analog Input Characteristics

Item

Full Scale V_Input

Condition

Min.

Typ.

Max. Unit

･ LINE/AUX1,2/MIN/MIC

･ MIC

2.5

0.25

16

2.8

3.1

Vpp

bit

+20dB

0.28

0.31

ADC Resolution

Recording Path (ADC)

Signal to Noise ratio

･ LINE/AUX1,2/MIN/MIC

･ MIC

78

75

82

80

dB

%

+20dB

Distortion

0.05

Interchannel Isolation

L/R Channel Separation

Gain Mismatch

70

dB

from Spec.

･ 0 ~ -20dB

-0.5

-1.0

-3.0

20

0.5

1.0

0.5

100

15

dB

k ^Ω

pF

･ -21dB or less

Frequency Response

Input Resistance

Input Capacitance

20 to 15kHz

Note : DV_SS=AV_SS=0[V], T_OP=25℃, DV_DD=AV_DD=5.0[V], fs=44.1kHz

Analog Output Characteristics

Item

Full Scale Line Output

･ OLB=1

Condition

Min.

Typ.

Max. Unit

2.4

1.7

16

2.8

2.0

3.1

2.2

Vpp

bit

･ OLB=0

DAC Resolution (WSS_DAC)

Frequency Response (WSS_DAC)

Mix_path Total

20 to 17.64 kHz

-1.0

0.5

dB

Signal to Noise ratio

･ from Input (LINE, AUX1)

･ from Input (AUX2, MIC)

･ from Input (MIC)

･ from WSS_DAC

Distortion

85

82

75

78

90

87

80

82

dB

+20dB

･ from Input

0.003

0.01

0.05

0.02

0.05

%

･ from Input (MIC)

･ from WSS_DAC

Interchannel Isolation

L/R Channel Separation

Gain Mismatch

%

70

dB

from Spec.

･ 0 ~ -20dB

-0.5

-1.0

0.5

1.0

-80

2.7

dB

V

･ -21dB or less

Mute Attenuation

VREFO Voltage output

2.3

2.5

Note : DV_SS=AV_SS=0[V], T_OP=25℃, DV_DD=AV_DD=5.0[V], fs=44.1kHz

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

■ External Dimensions

Note : The LSIs for surface mount need especial consideration on storage and soldering conditions.

For detailed information, please contact your nearest agent of yamaha.

May 21, 1997

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YMF715Eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

IMPORTANT NOTICE

1. Yamaha reserves the right to make changes to its Products and to this document without

notice. The information contained in this document has been carefully checked and is believed

to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no

commitment to update or to keep current the information contained in this document.

2. These Yamaha Products are designed only for commercial and normal industrial

applications, and are not suitable for other uses, such as medical life support equipment,

nuclear facilities, critical care equipment or any other application the failure of which could lead

to death, personal injury or environmental or property damage. Use of the Products in any such

application is at the customer's sole risk and expense.

3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL OR SPECIAL

DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR IMPROPER USE

OR OPERATION OF THE PRODUCTS.

4. YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS ARE

SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANYTHIRD

PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF NON-

INFRINGEMENT WITH RESPECT TO THE PRODUCTS. YAMAHA SPECIFICALLY

EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING FROM

OR RELATED TO THE PRODUCTS' INFRINGEMENT OF ANY THIRD PARTY'S

INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT, COPYRIGHT,

TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY.

5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE

CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA ASSUMES

NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR OTHER

PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE EXAMPLES

DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH RESPECT TO THE

PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR USE AND TITLE.

Note) The specifications of this product are subject to improvement change without prior notice.

YAMAHA CORPORATION

Address inquires to :

AGENCY

Semi-conductor Sales Department

Head Office

203, MatsunokiJima, Toyooka-mura.

■

Iwata-gun, Shizuoka-ken, 438-01

Tel. 0539-62-4918 Fax. 0539-62-5054

2-17-11, Takanawa, Minato-ku, Tokyo, 108

Tel. 03-5488-5431 Fax. 03-5488-5088

3-12-9, Minami Senba, Chuo-ku, Osaka City,

Osaka, 542 Shinsaibashi Plaza Bldg. 4F

Tel. 06-252-7980 Fax. 06-252-5615

YAMAHA System Technology.

Tokyo Office

Osaka Office

■

U.S.A. Office

■

100 Century Center Court, San Jose, CA 95112

Tel. 408-467-2300 Fax. 408-437-8791

May 21, 1997

-54-

型号:	YMF715E-S
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	YAMAHA CORP
零件包装代码：	QFP
包装说明：	LFQFP,
针数：	100
Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01
风险等级：	5.84
Is Samacsys：	N
其他特性：	IT ALSO REQUIRES 3.3V OR 5V DIGITAL SUPPLY
商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	S-PQFP-G100
长度：	14 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	100
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP
封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	225
认证状态：	Not Qualified
座面最大高度：	1.7 mm
最大供电电压 (Vsup)：	5.25 V
最小供电电压 (Vsup)：	4.75 V
表面贴装：	YES
温度等级：	COMMERCIAL
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm
Base Number Matches：	1

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