YMF753-S各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

YMF753

AC’97 Revision2.2 Audio CODEC

with Digital Audio I/F

OVERVIEW

YMF753 is an AC’97 Audio CODEC LSI, which is fully compliant with the industry standard “Audio

CODEC ’97” component specification (Revision 2.2).

Different from former AC’97, YMF753 supports new features like SPDIF OUT and Zoomed Video Port.

Without using a digital controller, these new features can be enhanced in the AC’97 sound system that has an

ICH controller built-in chipset.

Low power consumption is supported not only in the normal mode but can be controlled in the power-down

mode.

FEATURES

• AC’97 Revision 2.2 Compliant

• Exceeds PC99 / PC2001 Analog Performance Requirement

(Mobile PC Audio Performance Compliant when analog low power supply is used.)

• Analog Inputs :

- 4 Stereo Inputs: LINE, CD, VIDEO, AUX

- 2 Monaural Inputs: Speakerphone and PC BEEP Inputs

- 2 Independent Microphone Inputs

• PC BEEP can directly output to Line Out

• Internal +20dB amplifier circuitry for microphone

• Analog Outputs : Stereo LINE Output, True LINE Level and Monaural Output

• Supports Zoomed Video Port

• Supports Consumer IEC958 Output Port (SPDIF OUT)

• SPDIF Output for AC’97 Revision 1.0 Compliant

• Different audio data from AC-Link can be output to SPDIF and Line Out

• Supports 3D Enhancement (Wide Stereo), and Bass / Treble control

• Multiple CODEC Capability

• Programmable Power Down Mode

• Supports EAPD (External Amplifier Power Down)

• Power Supplies : Analog 4.3V to 5.0V, Digital 3.3V or 5.0V

• 48-Pin SQFP Package (YMF753-S)

CORPORATION

YAMAHA

YMF753 CATALOG

Decembe 3, 1998

CATALOG No.:LSI-4MF753A2

March 6, 2001

YMF753

PIN CONFIGURATION

DVdd1

XTL_IN

1

2

36

35

34

33

32

31

30

29

28

27

26

25

LINE_OUT_R

LINE_OUT_L

CAP6

XTL_OUT

DVss1

3

4

CAP5

SDATA_OUT

BIT_CLK

DVss2

5

CAP4

6

CAP3

7

CAP2

SDATA_IN

DVdd2

8

CAP1

9

Vrefout

Vref

SYNC

10

11

12

RESET#

PC_BEEP

AVss1

AVdd1

48-Pin SQFP Top View

2

March 6, 2001

YMF753

PIN DESCRIPTION

No.

1

Name

I/O

-

Function

Digital power supply (Typ. +3.3V / +5.0V)

Connect to the digital ground with 0.1mF and 47mF capacitors.

Connect this pin to DVdd2.

DVdd1

2

3

4

5

XTL_IN

XTL_OUT

DVss1

I

O

-

24.576MHz Clock Input

24.576MHz Clock Output

Digital ground. Connect this pin to DVss2.

AC’97 Serial Input Stream

SDATA_OUT

I

AC’97 Bit Clock

6

BIT_CLK

I/O

As an output pin at the primary codec where CODEC ID=00.

As an input pin at the secondary codec where CODEC ID=01,10,11.

Digital ground. Connect this pin to DVss1.

AC’97 Serial Output Stream

7

8

DVss2

-

SDATA_IN

O

Digital power supply (Typ. +3.3V / +5.0V)

Connect to the digital ground with 0.1mF and 47mF capacitors.

Connect this pin to DVdd1.

9

DVdd2

-

10

11

12

13

14

15

16

17

18

SYNC

RESET#

PC_BEEP

PHONE

AUX_L

I

SYNC Input (Fixed at 48kHz)

I

Hardware Reset

AI

PC Speaker Beep

Telephony Input

AUX Input Left Channel

AUX_R

AUX Input Right Channel

VIDEO_L

VIDEO_R

CD_L

Video Audio Input Left Channel

Video Audio Input Right Channel

CD Audio Input Left Channel

CD Audio Analog Ground

19

CD_GND

AI

Connect this pin to CD Ground or Analog Ground.

CD Audio Input Right Channel

20

21

22

23

24

CD_R

MIC1

AI

Microphone Input 1

MIC2

Microphone Input 2

LINE_IN_L

LINE_IN_R

Line Input Left Channel

Line Input Right Channel

Analog Power Supply (Typ. +4.3V to +5.0V)

Connect to the analog ground with 0.1mF and 47mF capacitors.

Connect this pin to AVdd2.

25

AVdd1

-

26

27

AVss1

Vref

-

Analog ground. Connect this pin to AVss2.

Analog Reference Voltage

AO

Connect to the analog ground with 0.1mF and 22mF capacitors.

Analog Reference Voltage Output

Connect to the analog ground with 0.1mF and 22mF capacitors when

it is used to the external circuit.

28

Vrefout

AO

3

March 6, 2001

YMF753

No.

Name

I/O

Function

29

30

31

32

33

34

35

36

37

CAP1

CAP2

A

Connect to the analog ground with a 2200pF capacitor.

Connect to the analog ground with a 0.015mF capacitor.

Connect to the analog ground with a 0.01mF capacitor.

Connect to the analog ground with a 2200pF capacitor.

Connect to the analog ground with a 0.015mF capacitor.

Connect to the analog ground with a 0.01mF capacitor.

Line Output Left Channel

CAP3

A

CAP4

A

CAP5

A

CAP6

A

LINE_OUT_L

LINE_OUT_R

MONO_OUT

AO

Line Output Right Channel

Monaural Output

Analog power supply (Typ. +4.3V to +5.0V)

Connect to the analog ground with 0.1mF and 47mF capacitors.

Connect this pin to AVdd1.

38

AVdd2

-

39

40

41

42

LNLVL_OUT_L

MSEL

AO

True LINE Level Output Left Channel

I

AO

-

Mode Select, which changes the pin function of No.43 – 46, 48.

True LINE Level Output Right Channel

LNLVL_OUT_R

AVss2

Analog ground. Connect to AVss1.

The function is selected at 62h TX-7 bit.

47

EAPD (DIT)

O

TX-7=“0”, External Amplifier Power Down

TX-7=“1”, Digital Audio Interface Output (48kHz)

1. MSEL= “High” (Connect to analog power supply.)

No.

Name

I/O

Function

Zoomed Video Port L/R clock

43

44

45

46

48

ZV_LR

ZV_SIN

Reserved

EXT24M

ZV_BCK

I-

-

Zoomed Video Port serial data

Do not connect externally.

24.576MHz clock output

O

I-

Zoomed Video Port bit clock

2. MSEL= “Low” (Connect to analog ground.)

No.

Name

I/O

Function

43

44

45

46

48

DIT

O

-

Digital Audio Interface Output (48kHz)

Do not connect externally.

CODEC ID

Reserved

CODEC ID0#

CODEC ID1#

DIT

I+

O

CODEC ID

Digital Audio Interface Output (48kHz)

Note) AI: Analog Input Pin, AO: Analog Output Pin, I+: Input Pin with a Pull-up resistor,

I-: Input Pin with a Pull-down resistor

4

March 6, 2001

YMF753

BLOCK DIAGRAM

MS

VREF

0dB/

+20dB

MIC1

MIC2

Record R

16step

LINE_IN_R

LINE_IN_L

CD_R

CD_GND

CD_L

A/D

CD Right

CD Left

Record L

16step

RESET#

BUF

SYNC

LPBK

AC’97

VIDEO_R

VIDEO_L

AUX_R

AUX_L

PHONE

PCM L

32step

BIT_CLK

digital

PCM R

32step

SDATA_OUT

I/F

ZV L

32step

SDATA_IN

ZV R

32step

UDS

DIT

TX-7

PHONE

32step

EAPD (DIT)

AUX

32step

ID0#

Reserved / ID0#

EXT24M / ID1#

ZV_LR / DIT

VIDEO

32step

ID1#

DIT

CD

32step

ZV_LR

ZV_SIN

ZV_BCK

LINE

32step

ZV

Port

ZV_SIN

/ Reserved

Monaural

32step

MIC

32step

MONO_OUT

PC_BEEP

EXT24M

ZV_BCK / DIT

MSEL

MIX

PC Beep

16step

RESET#

Left

Master L

32step

LINE_OUT_L

LINE_OUT_R

3D

tone

XTL_IN

Master R

32step

Right

LNLVL_OUT_L

LNLVL_OUT_R

POP

XTL_OUT

5

March 6, 2001

YMF753

MIXER REGISTERS

NAME

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

“0” “0” “0” “0” “0” “0” “0” “0” “0” “1” “0” “0” “0” “0” “0” “0” 0040h

00h

02h

04h

Reset

Master vol.

LNLVL vol.

Mute

-

ML5-0

-

MR5-0

8000h

0000h

8000h

0707h

0000h

8008h

8808h

0000h

8000h

0000h

-

06h Master vol. Mono Mute

-

MM5-0

-

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

Master tone

PC_BEEP vol.

Phone vol.

Mic vol.

-

BA2-0

-

TR2-0

Mute

-

PV3-0

-

GN4-0

-

20dB

GN4-0

GR4-0

Line in vol.

CD vol.

-

GL4-0

-

Video vol.

-

Aux vol.

-

PCM out vol.

Record Select

Record Gain

-

SL2-0

-

SR2-0

GR3-0

Mute

-

GL3-0

20h General Purpose POP

3D

-

MIX MS LPBK

-

22h

26h

3D Control

-

WD3-1

-

Power Down

PR5 PR4 PR3 PR2 PR1 PR0

REF ANL DAC ADC 000xh

EAPD

28h Extended Audio ID ID1 ID0

-

REV1-0

-

xxx4h

0400h

AMAP LDAC SDAC CDAC

SPDIF

2Ah Ext Audio Stat/Ctrl

3Ah DIT Control 1

62h Vendor Function

-

SPSA1-0

SPCV

-

V

-

SPSR1-0 GL CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE

PRO 2000h

COPY AUD#

*

-

*

GL4-0

-

*

TX-7

*

0224h

x808h

0040h

0C00h

EXEN

64h

66h

ZV vol.

Mute

ZEN ZAC

-

TX-3

-

GR4-0

MSEL

DIT Control 2

-

*

-

*

-

*

-

*

-

TX-8 DMU UDS

3AWE

68h 3D Mode Select

WM1-0

-

7Ch

7Eh

Vendor ID 1

Vendor ID 2

“0” “1” “0” “1” “1” “0” “0” “1” “0” “1” “0” “0” “1” “1” “0” “1” 594Dh

“0” “1” “0” “0” “1” “0” “0” “0” “0” “0” “0” “0” “0” “0” “1” “1” 4803h

Note) The * bits of 62h and 66h should not be changed from the default value.

Do not access to 5Ah and 60h because they are LSI test registers.

00h : Reset (Read/Write reset, Default: 0040h)

D15 D14 D13 D12 D11 D10

“0” “0” “0” “0” “0” “0”

D9

“0”

D8

“0”

D7

“0”

D6

“1”

D5

“0”

D4

“0”

D3

“0”

D2

“0”

D1

“0”

D0

“0”

When any value is written to this register, all registers except for the lower 4 bits of 26h:Power Down are reset

to the default value.

6

March 6, 2001

YMF753

02h : Master Volume (Read/Write, Default: 8000h)

D15 D14 D13 D12 D11 D10

Mute ML5-0

D9

D8

D7

-

D6

-

D5

D4

D3

D2

D1

D0

-

MR5-0

Mute..............Setting this bit to “1” mutes both left and right channels of the line output.

ML5-0...........These bits determine the volume level of the line output left channel by 1.5dB step. The volume

range is from 0dB to -46.5dB. When all bits are set to “0”, volume is maximum (0dB) and when

they are set to “011111b”, volume is minimum (-46.5dB). And when ML5 bit is set to “1”, the

volume level is minimum (-46.5dB), then their status become “011111b”.

MR5-0...........These bits determine the volume level of the line output right channel by 1.5dB step.

Setting to them is the same as the upper ML5-0 bits.

04h : LNLVL Volume (Read/Write, Default: 0000h)

D15 D14 D13 D12 D11 D10

D9

-

D8

-

D7

-

D6

-

D5

-

D4

-

D3

-

D2

-

D1

-

D0

-

Though the register can be written any value, it does not function.

0000h is always read out.

06h : Master Volume Mono (Read/Write, Default: 8000h)

D15 D14 D13 D12 D11 D10

Mute

D9

-

D8

-

D7

-

D6

-

D5

D4

D3

D2

D1

D0

-

MM5-0

Mute..............Setting this bit to “1” mutes the monaural output.

MM5-0..........These bits determine the volume level of the monaural output by 1.5dB step. The volume range

is from 0dB to -46.5dB. When all bits are set to “0”, volume is maximum (0dB) and when they

are set to “011111b”, volume is minimum (-46.5dB). And when MM5 bit is set to “1”, the

volume level is minimum (-46.5dB), then their status become “011111b”

08h : Master Tone (Read/Write, Default: 0707h)

D15 D14 D13 D12 D11 D10

D9

D8

D7

-

D6

-

D5

-

D4

-

D3

-

D2

D1

D0

-

BA2-0

TR2-0

BA2-0 ...........These bits determine the bass level by 1.5dB step. The tone range is from 0dB to +10.5dB.

When all bits are set to “0”, tone is maximum (+10.5dB) and when all bits are set to “1”, tone is

minimum (0dB)

TR2-0............These bits determine the treble level by 1.5dB step. Setting to them is the same as the upper

BA2-0.

7

March 6, 2001

YMF753

0Ah : PC_BEEP Volume (Read/Write, Default: 0000h)

D15 D14 D13 D12 D11 D10

Mute

D9

-

D8

-

D7

-

D6

-

D5

-

D4

D3

D2

D1

D0

-

PV3-0

Mute..............Setting this bit to “1” mutes the PC_BEEP.

PV3-0............These bits determine the volume level of the PC_BEEP by 3.0dB step. The volume range is from

0dB to -45dB. When all bits are set to “0”, volume is maximum (0dB) and when all bits are set

to “1”, volume is minimum (-45dB).

0Ch : Phone Volume (Read/Write, Default: 8008h)

D15 D14 D13 D12 D11 D10

Mute

D9

-

D8

-

D7

-

D6

-

D5

-

D4

D3

D2

D1

D0

-

GN4-0

Mute..............Setting this bit to “1” mutes the Phone.

GN4-0...........These bits determine the volume level of the Phone by 1.5dB step. The volume range is from

+12dB to -34.5dB. When all bits are set to “0”, volume is maximum (+12dB) and when all bits

are set to “1”, volume is minimum (-34.5dB).

0Eh : Mic Volume (Read/Write, Default: 8008h)

D15 D14 D13 D12 D11 D10

Mute

D9

-

D8

-

D7

-

D6

D5

-

D4

D3

D2

D1

D0

-

20dB

GN4-0

Mute..............Setting this bit to “1” mutes the Microphone.

20dB .............Setting this bit to “1” increases +20dB for the microphone volume, which is set to GN4-0 bits.

GN4-0...........These bits determine the volume level of the microphone by 1.5dB step. The volume range is

from +12dB to -34.5dB. When all bits are set to “0”, volume is maximum (+12dB) and when all

bits are set to “1”, volume is minimum (-34.5dB).

10h : Line in Volume (Read/Write, Default: 8808h)

12h : CD Volume (Read/Write, Default: 8808h)

14h : Video Volume (Read/Write, Default: 8808h)

16h : Aux Volume (Read/Write, Default: 8808h)

18h : PCM out Volume (Read/Write, Default: 8808h)

D15 D14 D13 D12 D11 D10

Mute GL4-0

D9

D8

D7

-

D6

-

D5

-

D4

D3

D2

D1

D0

-

GR4-0

Mute..............Setting this bit to “1” mutes both left and right channels of the each source.

GL4-0 ...........These bits determine the volume level of the left channel by 1.5dB step. The volume range is

from +12dB to -34.5dB. When all bits are set to “0”, volume is maximum (+12dB) and when all

bits are set to “1”, volume is minimum (-34.5dB).

GR4-0 ...........These bits determine the volume level of the right channel by 1.5dB step.

Setting to them is the same as the upper GL4-0 bits.

8

March 6, 2001

YMF753

1Ah : Record Select (Read/Write, Default: 0000h)

D15 D14 D13 D12 D11 D10

D9

D8

D7

-

D6

-

D5

-

D4

-

D3

-

D2

D1

D0

-

SL2-0

SR2-0

SL2-0 ............These bits select the left channel source for A/D converter.

SR2-0............These bits select the right channel source for A/D converter.

SL2 SL1 SL0

Left Source

Mic

SR2 SR1 SR0

Right Source

Mic

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

CD L-ch

CD R-ch

Video L-ch

Aux L-ch

Video R-ch

Aux R-ch

Line in L-ch

Stereo Mix L-ch

Mono Mix

Phone

Line in R-ch

Stereo Mix R-ch

Mono Mix

Phone

1Ch : Record Gain (Read/Write, Default: 8000h)

D15 D14 D13 D12 D11 D10

D9

D8

D7

-

D6

-

D5

D4

D3

D2

D1

D0

Mute GL3-0

-

GR3-0

Mute..............Setting this bit to “1” mutes the source which is selected at 1Ah:Record Select.

GL3-0 ...........These bits determine the volume level, which is selected at 1Ah:Record Select SL2-0 bits, by

1.5dB step. The volume range is from 0dB to +22.5dB. When all bits are set to “0”, volume is

minimum (0dB) and when all bits are set to “1”, volume is maximum (+22.5dB).

GR3-0 ...........These bits determine the volume level, which is selected at 1Ah:Record Select SR2-0 bits, by

1.5dB step. Setting to them is the same as the upper GL3-0 bits.

9

March 6, 2001

YMF753

20h : General Purpose (Read/Write, Default: 0000h)

D15 D14 D13 D12 D11 D10

POP 3D

D9

D8

D7

D6

-

D5

-

D4

-

D3

-

D2

-

D1

-

D0

-

MIX

MS LPBK

POP...............This bit selects whether PCM (DAC) output is gone through the 3D and Tone (Bass / Treble) or

not.

“0” : PCM (DAC) output is gone through the 3D and Tone.

“1” : PCM (DAC) output is bypassed the 3D and Tone.

3D.................This bit selects whether 3D enhancement is used or not.

“0” : Off

“1” : On

MIX ..............This bit selects the output to MONO_OUT(No.37).

“0” : All mixing sources are output to MONO_OUT.

“1” : The microphone input is output to MONO_OUT.

MS ................This bit selects either MIC1 or MIC2 for the microphone input.

“0” : MIC1 (No.21)

“1” : MIC2 (No.22)

LPBK............This bit selects data to the D/A converter.

“0” : Data from the AC-Link

“1” : Loopback from A/D converted data

22h : 3D Control (Read/Write, Default: 0000h)

D15 D14 D13 D12 D11 D10

WD3-1

D9

D8

-

D7

-

D6

-

D5

-

D4

-

D3

-

D2

-

D1

-

D0

-

WD3-1..........These bits determine the wide level of 3D enhancement (wide stereo). The wide range is from

0% to 100%. When all bits are set to “0”, wide level is 0% and when all bits are set to “1”, wide

level is 100%.

10

March 6, 2001

YMF753

26h : Power Down (Read/Write, Default: 000xh)

D15 D14 D13 D12 D11 D10

D9

D8

D7

-

D6

-

D5

-

D4

-

D3

D2

D1

D0

EAPD PR5 PR4 PR3 PR2 PR1 PR0

-

REF ANL DAC ADC

EAPD............This bit controls the state of EAPD (No.47) pin.

“0” : Low

“1” : High

PR5 ...............This bit controls the power state of the clock oscillation circuit.

“0” : Normal

“1” : Power down

PR4 ...............This bit controls the power state of the AC-Link.

“0” : Normal

“1” : Power down

PR3 ...............This bit controls the power state of the analog mixer.

“0” : Normal

“1” : Power down (Vref off)

PR2 ...............This bit controls the power state of the analog mixer.

“0” : Normal

“1” : Power down (Vref still on)

PR1 ...............This bit controls the power state of the D/A converter.

“0” : Normal

“1” : Power down

PR0 ...............This bit controls the power state of the A/D converter.

“0” : Normal

“1” : Power down

REF...............This bit is Read Only, and indicates the state of Vref.

“0” : Ground level

“1” : Reference voltage

ANL..............This bit is Read Only, and indicates the state of the analog mixer.

“0” : The analog mixer does not work.

“1” : The analog mixer works normally.

DAC..............This bit is Read Only, and indicates the state of the D/A converter.

“0” : The D/A converter does not work.

“1” : The D/A converter works normally.

ADC..............This bit is Read Only, and indicates the state of the A/D converter.

“0” : The A/D converter does not work.

“1” : The A/D converter works normally.

Note) When YMF753 is the Secondary CODEC, and both PR5 and PR4 are set to “1”, these bits are not

cleared by Warm Reset.

11

March 6, 2001

YMF753

28h : Extended Audio ID (Read Only, Default: xxx4h)

D15 D14 D13 D12 D11 D10

ID1 ID0 REV1-0

D9

D8

D7

D6

D5

-

D4

-

D3

-

D2

D1

-

D0

-

AMAP LDAC SDAC CDAC

SPDIF

ID1,ID0.........These bits indicate CODEC ID. The states are determined by setting both No.46 and 45 pins.

When MSEL is high, they are fixed to “Primary ID00”.

ID1# (No.46)

ID0# (No.45)

CODEC ID

Configuration

Pin Status

Logic Value

Pin Status

Logic Value

OPEN (“H”)

GND (“L”)

“0”

“1”

OPEN (“H”)

GND (“L”)

OPEN (“H”)

GND (“L”)

“0”

“1”

“0”

“1”

Primary ID00

Secondary ID01

Secondary ID10

Secondary ID11

REV1-0.........These bits are hardwired to “01b”, which indicates AC’97 Revision 2.2 Compliant.

AMAP...........This bit is hardwired to “1”. It indicates that the PCM DAC uses data of the standard slot into

twelve slots, as the following table.

CODEC

ID

Slot Number

PCM Left DAC

PCM Right DAC

00

01

10

11

Slot 3

Slot 7

Slot 6

Slot 4

Slot 8

Slot 9

Original definition (master)

Original definition (docking)

Left / Right surround channels

Center / LFE channels

LDAC ...........When PCM DAC uses the LFE channel, this bit is set to “1”.

SDAC ...........When PCM DAC uses the surround channels, this bit is set to “1”.

CDAC...........When PCM DAC uses the center channel, this bit is set to “1”.

SPDIF ...........This bit is hardwired to “1”, which indicates that SPDIF output is compliant with AC’97

Revision 2.2.

2Ah : Ext Audio Stat/Ctrl (Read/Write, Default: 0400h)

D15 D14 D13 D12 D11 D10

SPCV

D9

-

D8

-

D7

-

D6

-

D5

D4

D3

-

D2

D1

-

D0

-

SPSA1-0

SPDIF

SPCV............This bit is hardwired to “1”, which indicates that SPDIF output configuration is valid.

SPSA1-0 .......These bits select DIT output slot.

SPSA1

SPSA0

L-ch Slot Number

R-ch Slot Number

0

1

0

1

0

1

Slot 3

Slot 7

Slot 6

Slot 10

Slot 4

Slot 8

Slot 9

Slot 11

SPDIF ...........This bit selects whether the SPDIF signal is output from DIT or not.

“0” : DIT is power down state, and outputs low level.

“1” : SPDIF signal is output from DIT.

12

March 6, 2001

YMF753

3Ah : DIT Control 1 (Read/Write, Default: 2000h)

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

V

-

SPSR1-0 GL CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY AUD# PRO

V...................This bit determines V-bit (Validity flag) output from DIT.

“0” : The Validity flag is “0” (Valid).

“1” : The Validity flag is “1” (Invalid).

SPSR1-0 .......These bits determine sampling frequency of channel status output from DIT. These bits are

hardwired to “10b”, because SPDIF output of YMF753 is fixed to 48kHz.

GL.................This bit determines bit15: L-bit (Generation status) of channel status output from DIT. The

sense of Generation status is different by Category Code.

CC6-0 ...........These bits determine bit14-8: Category Code of channel status output from DIT.

PRE...............This bit determines bit3: Pre-emphasis of channel status output from DIT.

“0” : without Pre-emphasis

“1” : with Pre-emphasis of 50/15µs

COPY ...........This bit determines bit2: Copy protection of channel status output from DIT.

“0” : Copyright

“1” : No Copyright

AUD# ...........This bit determines bit1 of channel status output from DIT. If AC-3 or DTS is output, set to “1”.

“0” : PCM format

“1” : Non-PCM format

PRO ..............This bit determines bit0 of channel status output from DIT. It should be set to “0” as Consumer

use.

62h : Vendor Function (Read/Write, Default: 0224h)

D15 D14 D13 D12 D11 D10

D9

*

D8

*

D7

*

D6

*

D5

*

D4

*

D3

D2

D1

*

D0

*

TX-7 EXEN

TX-7 .............This bit selects the pin function of No.47.

“0” : EAPD

“1” : DIT

EXEN ...........This bit selects whether EXT24M pin outputs clock or not.

“0” : EXT24M is power down state, and outputs low level.

“1” : EXT24M outputs the clock.

The bits except TX-7 and EXEN should not be changed from the default value.

13

March 6, 2001

YMF753

64h : ZV Port Volume (Read/Write, Default: 8808h or C808h)

D15 D14 D13 D12 D11 D10

Mute MSEL GL4-0

D9

D8

D7

D6

D5

-

D4

D3

D2

D1

D0

-

ZEN ZAC

GR4-0

Mute..............Setting this bit to “1” mutes both left and right channels of the ZV port.

MSEL ...........This bit is read only, and indicates the status of No.40 MSEL pin.

“0” : Low

“1” : High

GL4-0 ...........These bits determine the volume level of the ZV port left channel by 1.5dB step. The volume

range is from +12dB to -34.5dB. When all bits are set to “0”, volume is maximum (+12dB) and

when all bits are set to “1”, volume is minimum (-34.5dB).

ZEN ..............This bit selects whether ZV port is used or not.

“0” : ZV port is power down state, and can not be used.

“1” : ZV port can be used.

ZAC ..............This bit is read only, and indicates whether the bit clock (ZV_BCK) is input to ZV port or not.

“0” : The bit clock (ZV_BCK) is not input.

“1” : ZV port is active because the bit clock (ZV_BCK) is input.

GR4-0 ...........These bits determine the volume level of the ZV port right channel by 1.5dB step.

Setting to them is the same as the upper GL4-0 bits.

66h : DIT Control 2 (Read/Write, Default: 0040h)

D15 D14 D13 D12 D11 D10

D9

-

D8

*

D7

*

D6

*

D5

D4

*

D3

D2

D1

D0

-

TX-3

TX-8 DMU UDS 3AWE

TX-3 .............SPDIF signal is output from No.43 DIT, if this bit is set to “1” at MSEL= “Low”.

TX-8 .............SPDIF signal is output from No.48 DIT, if this bit is set to “1” at MSEL= “Low”.

DMU.............Setting this bit to “1” mutes audio data output from DIT.

UDS..............This bit selects the data output from DIT.

“0” : Data from the AC-Link

“1” : Data from A/D converter

3AWE...........This bit selects whether 3Ah register can be written or not.

“0” : 3Ah register is Read Only.

“1” : 3Ah register is Read / Write.

D8, D7, D6 and D4 should not be changed from the default value.

14

March 6, 2001

YMF753

68h : 3D Mode Select (Read/Write, Default: 0C00h)

D15 D14 D13 D12 D11 D10

WM1-0

D9

-

D8

-

D7

-

D6

-

D5

-

D4

-

D3

-

D2

-

D1

-

D0

-

WM1-0 .........These bits select the mode of 3D / Bass / Treble according to the frequency response of the

speaker.

WM1

WM0

3D Mode

Target Speaker

–

Speaker Size

–

0

1

0

1

0

1

Do not select.

DeskTop

Standard Speaker 5 – 12 cm

Notebook PC 1

Notebook PC 2

Small Speaker

3 cm

Smaller Speaker

1.5 cm

7Ch : Vendor ID 1 (Read Only, Default: 594Dh)

D15 D14 D13 D12 D11 D10

“0” “1” “0” “1” “1” “0”

D9

“0”

D8

“1”

D7

“0”

D6

“1”

D5

“0”

D4

“0”

D3

D2

“1”

D1

“0”

D0

“1”

7Eh : Vendor ID 2 (Read Only, Default: 4803h)

D15 D14 D13 D12 D11 D10

“0” “1” “0” “0” “1” “0”

D9

“0”

D8

“0”

D7

“0”

D6

“0”

D5

“0”

D4

“0”

D3

“0”

D2

“0”

D1

“1”

D0

“1”

7Ch and upper 8 bits of 7Eh indicate Yamaha vendor ID, which is “YMH”. “Y” is 59h, “M” is 4Dh, and “H”

is 48h with ASCII code.

Lower 8 bits of 7Eh is YMF753 revision ID (03h).

15

March 6, 2001

YMF753

SYSTEM CONNECTION DIAGRAM

Mono Out

L-ch LNLVL Out

R-ch LNLVL Out

L-ch LINE Out

R-ch LINE Out

PC Beep

PC_BEEP

Phone

PHONE

AUX_L

Vref

L-ch AUX

R-ch AUX

L-ch Video

R-ch Video

L-ch CD

AUX_R

VIDEO_L

VIDEO_R

CD_L

Vrefout

MSEL

AVdd1,2

AVss1,2

+5.0V

+3.3V

CD Ground

R-ch CD

CD_GND

CD_R

YMF753-S

MIC

MIC1

L-ch Line IN

R-ch Line IN

LINE_IN_L

LINE_IN_R

MIC2

DVdd1,2

DVss1,2

XTL_OUT

XTL_IN

ZV BCK

ZV SIN

ZV LR

SDATA IN

SDATA OUT

BIT CLK

SYNC

EAPD / DIT

DGND AGND

RESET#

1) Power and Ground

To get the most out of analog performance, it is necessary to split the ground into analog and digital blocks.

Analog ground and digital ground earth at one point closed to the initial ground supply of the board. The

layout of the ground pattern should be designed as large as possible and the impudence should be reduced to

prevent from receiving ambient noise. In addition, use 0.1µF and 47µF capacitors to connect between the

analog voltage pin and the analog ground as well as between the digital supply pin and the digital ground.

2) Reference Voltage

As the reference voltage determines all analog signals’ reference levels of YMF753, noise generated from

the reference voltage could affect the YMF753’s analog performance. To stabilize the YMF753’s reference

voltage, insert a 0.1µF ceramic capacitor in parallel with a 22µF capacitor between Vref pin and the ground.

The 0.1µF ceramic capacitor should be designed as close to the Vref pin as possible

3) Master Clock

To suppress the master clock from affecting its surroundings, it is recommended to keep the master clock

guarded on the ground so the noise can be reduced.

4) Unused Analog Input / Output pins

For the unused analog input pins, short them through a 0.1µF ceramic capacitor to the analog ground. For

the unused analog output pins, they should be left opened.

16

March 6, 2001

YMF753

5) Recommended Analog Voltage Circuit

YMF753 is presumed that it is made to work in the analog power supply formed from +5.0±0.25V power

supply, because the range of analog operating voltage is being made +4.0V to +5.25V. The recommended

circuit to form the analog power supply from +5V power supply is shown in below.

+5.0V

470 W

+4.3V

100 µF

0.1 µF

To YMF753’s AVdd1,2

0.1 µF

17

March 6, 2001

YMF753

ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Parameter

Analog Supply Voltage

Symbol

Min.

Max.

Unit

AV_DD

DV_DD

V_INA

V_IND

T_OP

-0.3

-0.5

0

7.0

V

Digital Supply Voltage

Analog Input Voltage

Digital Input Voltage

Ambient Temperature

Storage Temperature

Note) DV_SS= AV_SS= 0V

AV_DD+ 0.5

DV_DD+ 0.5

70

V

°C

T_STG

-50

125

2. Recommended Operating Conditions

Parameter

Symbol

Min.

Typ.

Max.

Unit

Analog Operating Voltage

AV_DD

DV_DD

T_OP

4.00

4.75

3.135

0

5.00

3.30

25

5.25

3.465

70

V

Digital Operating Voltage

V

Operating Ambient Temperature

Note) DV_SS= AV_SS= 0V

°C

When using a recommended analog voltage circuit, the output serves as AV_DD(typical 4.3V).

18

March 6, 2001

YMF753

3. DC Characteristics

3-1. AC-Link

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Input Voltage

V_IN

V_IH

V_IL

-0.30

-

DV_DD+ 0.30

V

Input Voltage High Level

Input Voltage Low Level

Output Voltage High Level

Output Voltage Low Level

Input Leakage Current

Output Leakage Current

0.65 ´ DV_DD

-

0.35 ´ DV_DD

V

V_OHI_OH= -5mA

0.9 ´ DV_DD

-

V

V_OLI_OL= 5mA

-

0.1 ´ DV_DD

V

-10

10

µA

-

Hi-Z

Note) Applicable to RESET#, SYNC, BIT_CLK, SDATA_IN and SDATA_OUT.

3-2. Miscellaneous

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Input Voltage High Level 1

Input Voltage Low Level 1

Input Voltage High Level 2

Input Voltage Low Level 2

V_IH1*1

V_IL1*1

V_IH2*2

V_IL2*2

0.7 ´ DV_DD

-

V

-

0.3 ´ DV_DD

0.8 ´ AV_DD

-

V

-

0.2 ´ AV_DD

V

*3, DV_DD=3.3V

2.0

-

V

Input Voltage High Level 3

Input Voltage Low Level 3

V_IH3

V_IL3

*3, DV_DD=5.0V 0.7 ´ DV_DD

-

V

*3, DV_DD=3.3V

*3, DV_DD=5.0V

-

0.8

V

-

0.3 ´ DV_DD

V

Output Voltage High Level 1

Output Voltage Low Level 1

Output Voltage High Level 2

Output Voltage Low Level 2

Output Voltage High Level 3

Output Voltage Low Level 3

Pull-up Resistor

V_OH1*4, I_OH= -4mA 0.65 ´ AV_DD

V_OL1*4, I_OL= 4mA

V_OH2*5, I_OH= -2mA 0.65 ´ AV_DD

-

0.4

-

V

-

V

-

V

V_OL2*5, I_OL= 2mA

V_OH3*6, I_OH= -2mA

V_OL3*6, I_OL= 2mA

R_ONUPID0#, ID1#

R_ONDW*3

-

0.4

-

V

DV_DD- 0.4

-

V

-

0.4

-

V

100

kW

Pull-down Resistor

-

Note) *1 : Applicable to XTL_IN, ID0# and ID1#.

*2 : Applicable to MSEL.

*3 : Applicable to ZV_LR, ZV_SIN and ZV_BCK.

*4 : Applicable to EAPD.

*5 : Applicable to DIT(No.43).

*6 : Applicable to EXT24M and DIT(No.48).

19

March 6, 2001

YMF753

4. AC Characteristics (Under recommended operating conditions, Capacitor load=50pF)

4-1. Reset

Parameter

Symbol

Min.

Typ.

Max.

Unit

Cold Reset (SDATA_OUT=“L”, SYNC=“L”)

RESET# active low pulse width

RESET# inactive to BIT_CLK start up delay

Warm Reset

Trst_low

Trst2clk

1.0

-

µs

ns

162.8

SYNC active high pulse width

Tsync_high

Tsync2clk

1.0

-

µs

ns

SYNC inactive to BIT_CLK start up delay

162.8

Cold Reset

Trst2clk

Trst_low

RESET#

V_IL

BIT_CLK

Warm Reset

Tsync2clk

Tsync_high

V_IH

SYNC

BIT_CLK

20

March 6, 2001

YMF753

4-2. AC-link Interface

Parameter

Symbol

Min.

Typ.

Max.

Unit

BIT_CLK frequency

-

12.288

81.4

-

MHz

ns

BIT_CLK clock period

BIT_CLK output jitter

Tclk_period

-

750

45.0

ps

BIT_CLK low pulse width

BIT_CLK high pulse width

SYNC frequency

Tclk_low

Tclk_high

36.0

40.7

48.0

20.8

19.5

1.3

-

ns

kHz

µs

SYNC period

Tsync_period

Tsync_low

Tsync_high

Tsetup

-

SYNC low pulse width

SYNC high pulse width

SDATA_OUT, SYNC setup time

SDATA_OUT hold time

SDATA_IN delay time

AC-link Low Power Mode

End of slot 2 to BIT_CLK, SDATA_IN low

-

µs

-

µs

10.0

20.0

-

ns

Thold

-

ns

Tco

-

15.0

ns

Ts2_pdown

-

1.0

µs

BIT_CLK

Tclk_high

Tclk_low

BIT_CLK

Tclk_period

SYNC

Tsync_high

Tsync_low

SYNC

Tsync_period

Data Output and Input Timing

Tco

Tsetup

BIT_CLK

SDATA_IN

Thold

SDATA_OUT,

SYNC

21

March 6, 2001

YMF753

AC-link Low Power Mode

Slot1

Slot2

BIT_CLK

SDATA_OUT

Write to 26h

Data PR4

Don’t Care

Ts2_pdown

SDATA_IN

4-3. Master Clock & External Clock Out

Parameter

Symbol

Min.

Typ.

Max.

Unit

XTL_IN, EXT24M clock period

XTL_IN clock duty

Tcycle

Duty-xtl

Duty-ext

-

40.69

-

ns

%

40

-

60

EXT24M clock duty

XTL_IN & EXT24M

XTL_IN

EXT24M

Tcycle

22

March 6, 2001

YMF753

4-4. Zoomed Video Port

Parameter

Symbol

Min.

Typ.

Max.

Unit

ZV_BCK frequency

ZV_BCK duty

f_BCK

D_BCK

t_LRD

t_LRS

t_DS

32fs

40

48fs

64fs

kHz

%

50

-

60

-

ZV_LR delay time

ZV_LR setup time

ZV_SIN setup time

ZV_SIN hold time

120

32

ns

-

ns

32

-

ns

t_DH

2

-

ns

Zoomed Video Port

1/f_BCK

ZV_BCK

t_DH

t_DS

ZV_SIN

ZV_LR

t_LRD

t_LRS

5. Power Consumption

Parameter

Min.

Typ.

Max.

Unit

Normal Operating

AV_DD= 4.3V / DV_DD= 3.3V

AV_DD= 5.0V / DV_DD= 5.0V

AV_DD= 4.3V

45

55

mA

35

43

8

AV_DD= 5.0V

DV_DD= 3.3V

DV_DD= 5.0V

12

Power Down Mode (PR0-PR5=0)

AV_DD= 4.3V / DV_DD= 3.3V

AV_DD= 5.0V / DV_DD= 5.0V

AV_DD= 4.3V

10

20

µA

7

12

2

AV_DD= 5.0V

DV_DD= 3.3V

DV_DD= 5.0V

4

23

March 6, 2001

YMF753

6. Analog Characteristics

Parameter

Min.

Typ.

Max.

Unit

Full Scale Line Input

AV_DD/ 5

AV_DD/ 50

AV_DD/ 5

Vrms

Full Scale Microphone Input (0dB)

Full Scale Microphone Input (+20dB)

Full Scale Line Output

Analog S/N

CD to LINE_OUT

90

95

dB

Hz

dB

Hz

dB

ms

dB

Stereo input except CD to LINE_OUT

Analog Frequency Response

S/N : D/A converter (fs=48kHz)

S/N : A/D converter (fs=48kHz)

90

20

85

75

20,000

90

85

THD+N : Line Output

AV_DD=5.0V

AV_DD=4.3V

-70

-68

-65

-62

D/A & A/D Frequency Response

Transition Band

20

19,200

28,800

19,200

28,800

70

Stop Band

Stop Band Rejection

Out-of-Band Rejection

Group Delay

40

1

Power Supply Rejection Rate (1kHz)

Crosstalk between Inputs Channels

Attenuation & Gain Step

PC_BEEP

-70

3.0

1.5

dB

kW

pF

V

Other than PC_BEEP

Input Impedance

10

Input Capacitor

7.5

Vrefout Voltage

AV_DD/ 2

Note) Typical conditions : T_OP=25°C, DV_DD=3.3V, AV_DD=4.3V to 5.0V,

1kHz input sine wave, fs=48kHz, 0dB=AV_DD/5 Vrms, 10kW / 50pF

S/N (dynamic range) measurement: -60dB input, THD+N measurement: -3dB input

24

March 6, 2001

YMF753

EXTERNAL DIMENSIONS

9.00±0.40

7.00±0.30

C-PK48SP-2

36

25

24

37

48

13

1

12

0.20TYP

or 0.18TYP

P-0.50TYP

(1.0)

0-10˚

0.50±0.20

LEAD THICKNESS : 0.125TYP or 0.17TYP

The shape of the molded corner may slightly different from the shape in this diagram.

The figures in the parenthesis ( ) should be used as a reference.

Plastic body dimension do not include burr of resin.

UNIT : mm

Note : The LSIs for surface mounting need for special care on storage and soldering conditions.

For detailed information, please contact your nearest agent of Yamaha.

25

March 6, 2001

YMF753

IMPORTANT NOTICE

1. Yamaha reserves the right to make changes to its Products and to this document

without notice. The information contained in this document has been carefully checked

and is believed to be reliable. However, Yamaha assumes no responsibilities for

inaccuracies and makes no commitment to update or to keep current the information

contained in this document.

2. These Yamaha Products are designed only for commercial and normal industrial

applications, and are not suitable for other uses, such as medical life support equipment,

nuclear facilities, critical care equipment or any other application the failure of which could

lead to death, personal injury or environmental or property damage. Use of the Products

in any such application is at the customer’s sole risk and expense.

3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL, OR

SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR

IMPROPER USE OR OPERATION OF THE PRODUCTS.

4. YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS

ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANY

THIRD PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF

NON-INFRANGIMENT WITH RESPECT TO THE PRODUCTS. YAMAHA SPECIALLY

EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING

FROM OR RELATED TO THE PRODUCTS’ INFRINGEMENT OF ANY THIRD PARTY’S

INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT, COPYRIGHT,

TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY.

5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE

CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA

ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR

OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE

EXAMPLES DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH

RESPECT TO THE PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT

LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A

PARTICULAR USE AND TITLE.

Note) The specifications of this product are subject to improvement change without prior notice.

YAMAHA CORPORATION

Address inquires to :

AGENCY

Semi-conductor Sales & Marketing Department

- Head Office

203, MatsunokiJima, Toyooka-mura.

Iwata-gun, Shizuoka-ken, 438-0192

Tel. +81-539-62-4918 Fax. +81-539-62-5054

2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568

Tel. +81-3-5488-5431 Fax. +81-3-5488-5088

1-13-17, Namba Naka, Naniwa-ku,

- Tokyo Office

- Osaka Office

Osaka City, Osaka, 556-0011

Tel. +81-6-6633-3690 Fax. +81-6-6633-3691

26

March 6, 2001

Printed in Japan

型号:	YMF753-S
生命周期：	Obsolete
IHS 制造商：	YAMAHA CORP
零件包装代码：	QFP
包装说明：	FQFP,
针数：	48
Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01
风险等级：	5.81
其他特性：	IT ALSO REQUIRES 3.3V AND 5V DIGITAL SUPPLY
商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	S-PQFP-G48
长度：	7 mm
功能数量：	1
端子数量：	48
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	FQFP
封装形状：	SQUARE
封装形式：	FLATPACK, FINE PITCH
认证状态：	Not Qualified
座面最大高度：	1.85 mm
最大供电电压 (Vsup)：	5.25 V
最小供电电压 (Vsup)：	4 V
表面贴装：	YES
温度等级：	COMMERCIAL
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	QUAD
宽度：	7 mm
Base Number Matches：	1

电子百科

产品导航

产品型号YMF753-S的概述

产品型号YMF753-S的Datasheet PDF文件预览

YMF753-S相关产品

YMF753-S相关文章

IC37:专业IC行业平台