TRCV012G5 and TRCV012G7
Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet
August 2000
Functional Overview
The Lucent Technologies Microelectronics Group TRCV012G5 operates at the OC-48/STM-16 data rate of
2.5 Gbits/s.* The TRCV012G7 device operates at either 2.5 Gbits/s or the RS FEC OC-48/STM-16 data rate of
2.7 Gbits/s. The device performs the data detection, clock recovery, and 1:16 demultiplexing operations required to
support 2.5 Gbits/s applications compliant with
Telcordia Technologies
and ITU standards. A differential limiting
amplifier with an adjustable threshold amplifies the 2.5 Gbits/s serial data waveform from an off-chip transimped-
ance amplifier (TIA). Alternatively, a CML logic level input can be selected as the data source. A PLL recovers the
clock which is used to retime the data. The decision sampling phase can be adjusted for optimal system perfor-
mance. The 2.5 Gbits/s serial data and the 2.5 GHz recovered clock signal are available at CML outputs, or alter-
natively, they can be disabled or the data can be muted. A 1:16 data demultiplexer performs the serial-to-parallel
conversion and generates 16 parallel outputs at a 155 Mbits/s rate as well as a parity indicator. The parallel output
data is aligned to a 155 MHz clock derived from the 2.5 GHz recovered clock. Loss of analog signal (LOSA) and
loss of digital transitions (LOSD) are indicated. A 155 MHz reference clock may optionally be applied to serve as a
frequency reference when data timing is lost.
Limiting Amplifier
Limiting Amplifier Operation
The limiting amplifier receives the input serial 2.5 Gbits/s data waveform from a transimpedance amplifier interface.
The limiting amplifier inputs are internally terminated with 50
Ω
resistors to ensure high input return loss perfor-
mance. The signal is amplified with a small signal gain of approximately 30 dB to a saturation level of approxi-
mately 800 mVp-p in order to provide a digital waveform to the clock and data recovery PLL. Full limiting is
guaranteed for inputs of 15 mVp-p or greater on each input rail (30 mVp-p differential). If the input signal level is
below a user-configurable threshold for a sufficiently long period of time, the LOSA signal is asserted. (For more
detail on the LOSA functions, see the Analog Loss of Signal (LOSAN, PRG_LOSA) section on page 16.)
A typical interface between the lightwave receiver and the limiting amplifier is shown in Figure 3.
Note:
It is recommended to use a differential interface from the lightwave receiver device with ac coupling.
The slicing level can be adjusted by varying the voltage on the SLADJ pin within ±300 mV of V
CC
/2. This feature
can be used to improve BER performance in optical receivers and optical amplifier systems. The relationship
between the external voltage and the slicing level is given in Table 9 on page 20. If the voltage at this pin is tied
below 0.5 V, the external slice adjustment is disabled and only the internal offset cancellation feature is active. The
user should connect the SLADJ pin to GND if the slice adjust feature is not needed. The limiting amplifier will per-
form in accordance with the specifications shown in Table 9.
SLADJ
VTHP
LIGHTWAVE RECEIVER
DEVICE
0.1
µF
TIA
0.1
µF
VTHN
0.047
µF
LAINP
LAINN
0.047
µF
50
Ω
50
Ω
OFFSET CANCEL
&
SLICE ADJUST
LIMITING
AMPLIFIER
5-8068(F)
Figure 3. Typical TIA to Limiting Amplifier Interface
* The OC-48/STM-16 data rate of 2.48832 Gbits/s is typically approximated as 2.5 Gbits/s in this document when referring to the application
rate. The RS FEC OC-48/STM-16 data rate is 2.66606 Gbits/s and is approximated as 2.7 Gbits/s in this document. Similarly, the OC-3/
STM-1 data rate of 155.52 Mbits/s is typically approximated as 155 Mbits/s, and the RS FEC OC-3/STM-1 data rate of 166.62 Mbits/s is
approximated as 166 Mbits/s. The exact frequencies are used only when necessary for clarity.
10
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
