TRCV012G5 and TRCV012G7
Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet
August 2000
(continued)
(continued)
Pin
115
Symbol*
PDDMXN
Type
†
I
u
Level
CMOS
Name/Description
Powerdown Demultiplexer Circuit (Active-Low).
0 = demultiplexer powered off, D[15:0]P/N and PARITYP/N
are high-impedance
1 or no connection = demultiplexer powered on
Mute Data to Demultiplexer Circuit (Active-Low).
0 = mute data
1 or no connection = normal data
Recovered Clock Output (155 MHz).
155 MHz recovered differential clock output. Pins are active
but forced to differential logic low when MUTE155N = 0.
Mute CK155P/N Clock Output (Active-Low).
Forces
CK155P/N to logic low when MUTE155N is active.
0 = muted
1 or no connection = enabled
Parity Input Over Data (D[15:0]).
Active only when
PDDMXN = 1.
Reference Clock Input (155 MHz).
This clock is optional. If
applying the REFCLKP/N, set the REFCLKP/N to one of
the following frequencies:
s
117
MUTEDMXN
I
u
CMOS
108
107
114
CK155P
CK155N
MUTE155N
O
LVPECL
I
u
CMOS
105
104
111
110
PARITYP
PARITYN
REFCLKP
REFCLKN
O
I
LVPECL
LVPECL
155.52 MHz if using the TRCV012G5, or the
TRCV012G7 at the 0C-48/STM-16 rate of 2.48832 GHz.
s
113
REFSELN
I
u
CMOS
166.62 MHz if using the TRCV012G7 at the RS FEC
0C-48/STM-16 rate of 2.66606 GHz.
Reference Select to PLL.
Selects LAINP/N or DATAP/N, or
REFCLKP/N as the input to the CDR PLL.
0 = select REFCLKP/N
1 or no connection = select LAINP/N or DATAP/N
* Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
† I = input, O = output. I
u
= an internal pull-up resistor on this pin, I
d
= an internal pull-down resistor on this pin, I
t
= an internal termination resis-
tance of 50
Ω
on this pin.
8
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
