TRCV012G5 and TRCV012G7
Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet
August 2000
(continued)
(continued)
Pin
43
44
124
Symbol*
DATCKP
DATCKN
ENDATCKN
Type
†
I
t
I
u
Level
CML
CMOS
Name/Description
Clock Input for DATAP/N.
Buffer is powered down when
ENDATCKN = 1.
External DATCKP/N Clock Select (Active-Low).
Selects
external DATCKP/N clock to demultiplexer.
0 = select DATCKP/N
1 or no connection = select VCO clock
Data Input for CML.
Use this input for system loopback
data when LAINP/N is used.
Enable DATAP/N Inputs (Active-Low).
Selects DATAP/N
as data source rather than limiting amplifier output.
0 = select DATAP/N
1 or no connection = select LAINP/N
Adjustable Sampling Circuit Reference Resistor.
Connect a 2.1 kΩ resistor to V
CCA
.
Adjustable Sampling Time Control Inputs.
AST[4:0]
allows introduction of an offset into the sampling time. The
most significant bit (A4) is the sign bit and bits A[3:0]
represent the magnitude. (See the Decision Circuit—
A4 is the polarity bit as follows:
1 = advance
0 = delay sampling point
AST[3:0] provides adjustments in steps (increments or
decrements) of 6.25 ps in the sampling instant.
* Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
† I = input, O = output. I
u
= an internal pull-up resistor on this pin, I
d
= an internal pull-down resistor on this pin, I
t
= an internal termination resis-
tance of 50
Ω
on this pin.
46
47
125
DATAP
DATAN
ENDATAN
I
t
I
u
CML
CMOS
37
2
3
4
5
6
ASTREF
AST4
AST3
AST2
AST1
AST0
I
I
d
Analog
CMOS
6
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
