AS4LC2M8S1
AS4LC1M16S1
®
18 A proper power-up initialization sequence (as described on page 10) is needed before proper device operation is ensured. (V
DD
and V
DDQ
must be
powered up simultaneously. V
SS
and V
SSQ
must be at the same potential.)Two AUTOREFRESH command wake-ups should be repeated any time the t
REF
refresh requirement is exceeded.
19 AC characteristics assume t
T
= 1 ns.
20 In addition to meeting the transition rate specification, the clock and CKE must transit between V
IH
and V
IL
(or between V
IL
and V
IH
) in a monotonic
manner.
21 AC timing and I
DD
tests have V
IL
= 0V and V
IH
= 3.0 V with timing referenced to 1.4V crossover point.
22 I
DD
specifications are tested after the device is properly initialized.
23 Minimum clock cycles = (minimum time/clock cycle time) rounded up.
Device operation
Command
Pin settings
Description
The following sequence is recommended prior to normal operation.
1 Apply power, start clock, and assert CKE and DQM high. All other
signals are NOP.
2 After power-up, pause for a minimum of 200µs. CKE/DQM =
high; all others NOP.
3 Precharge both banks.
4 Perform Mode Register Set command to initialize mode register.
5 Perform a minimum of 8 auto refresh cycles to stabilize internal
circuitry.
(Steps 4 and 5 may be interchanged.)
The mode register stores the user selected opcode for the SDRAM
operating modes. The CAS latency, burst length, burst type, test mode
and other vendor specific functions are selected/programmed during
the Mode Register Set command cycle. The default setting of the mode
register is not defined after power-up. Therefore, it is recommended
that the power-up and mode register set cycle be executed prior to
normal SDRAM operation. Refer to the Mode Register Set table and
timing for details.
The SDRAM performs a “no operation” (NOP) when RAS, CAS, and
WE = high. Since the NOP performs no operation, it may be used as a
wait state in performing normal SDRAM functions. The SDRAM is
deselected when CS is high. CS high disables the command decoder
such that RAS, CAS, WE and address inputs are ignored. Device
deselection is also considered a NOP.
The SDRAM is configured with two internal banks. Use the Bank
Activate command to select a row in one of the two idle banks. Initiate
a read or write operation after t
RCD
(min) from the time of bank
activation.
Use the Burst Read command to access a consecutive burst of data from
an active row in an active bank. Burst read can be initiated on any
column address of an active row. The burst length, sequence and
latency are determined by the mode register setting. The first output
data appears after the CAS latency from the read command. The output
goes into a high impedance state at the end of the burst (BL = 1,2,4,8)
unless a new burst read is initiated to form a gapless output data
stream. A full-page burst does not terminate automatically at the end of
the burst. Terminate the burst with a burst stop command, precharge
command to the same bank or another burst read/write
Power up
Mode register set
CS = RAS = CAS = WE = low;
A0~A11 = opcode
Device deselect and
no operation
CS = high, or
RAS, CAS, WE = high
Bank activation
CS = RAS = low; CAS = WE =
high; A0~A10 = row address;
A11 = bank select
Burst read
CS = CAS = A10 = low; RAS =
WE = high; A11 = bank select,
A0~A8 = column address; (A9
= don’t care for 2M × 8; A8,
A9 = don’t care for 1M × 16)
5/21/01; v.1.1
Alliance Semiconductor
P. 10 of 29
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
