AS4LC2M8S1
AS4LC1M16S1
®
Read—DQM operation
*
T0
CLK
t
CKS
t
CKH
t
CK*†ƒ
T1
t
CL
T2
t
CH
T3
t
CL
T4
T5
T6
T7
T8
CKE
t
CMS
t
CMH
NOP
READ
t
CMS
t
CMH
t
DQZ
t
AS
t
AH
Column m
(A0-A7)
3
COMMAND
DQMƒ
A0–A9
A10
BA
DQ
ACTIVE
NOP
NOP
NOP
NOP
NOP
NOP
ROW
t
AS
t
AS
t
AH
t
AH
ROW
ENABLE AUTOPRECHARGE
ROW
DISABLE AUTOPRECHARGE
BANK
BANK
t
AC*†ƒ
t
LZ
t
OH
D
OUT m
t
HZ
t
LZ
t
AC*†ƒ
t
AC*†ƒ
t
OH
D
OUT m+2
t
OH
D
OUT m+3
t
HZ
t
RCD
CAS latency
* For this example, the burst length = 4, and the CAS latency = 2.
† A8 and A9 = “Don’t care.”
ƒ DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
Write—DQM operation
*
T0
CLK
t
CKS
t
CKH
t
CK*†ƒ
T1
t
CL
T2
t
CH
T3
T4
T5
T6
T7
CKE
t
CMS
t
CMH
NOP
WRITE
t
CMS
t
CMH
NOP
NOP
NOP
NOP
NOP
COMMAND
DQMƒ
ACTIVE
t
AS
t
AH
Column m
(A0-A7)
†
ENABLE AUTOPRECHARGE
DISABLE AUTOPRECHARGE
BANK
A0–A9
A10
BA
DQ
*
ROW
t
AS
t
AS
t
AH
t
AH
ROW
BANK
t
DS
t
RCD
t
DH
D
IN
m
t
DS
t
DH
t
DS
t
DH
D
IN
m+2
D
IN
m+3
For this example, the burst length = 4.
A8 and A9 = “Don’t care.”
ƒ
DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
†
5/21/01; v.1.1
Alliance Semiconductor
P. 13 of 29
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
