AS4LC2M8S1
AS4LC1M16S1
®
Command
Pin settings
Auto refresh
CS = RAS = CAS = low; WE =
CKE = high; A0~A11 = don’t
care
Self refresh
CS = RAS = CAS = CKE = low;
WE = high; A0~A11 = don’t
care
Description
SDRAM storage cells must be refreshed every 64 ms to maintain data
integrity. Use the auto refresh command to accomplish the refreshing
of all rows in both banks of the SDRAM. The row address is provided
by an internal counter which increments automatically. Auto refresh
can only be asserted when both banks are idle and the device is not in
the power down mode. The time required to complete the auto refresh
operation is t
RC
(min). Use NOPs in the interim until the auto refresh
operation is complete. Both banks will be in the idle state after this
operation.
Self refresh is another mode for refreshing SDRAM cells. In this mode,
refresh address and timing are provided internally. Self refresh entry is
allowed only when both banks are idle. The internal clock and all input
buffers with the exception of CKE are disabled in this mode. Exit self
refresh by restarting the external clock and then asserting CKE high.
NOPs must follow for a time of t
RC
(min) for the SDRAM to reach the
idle state where normal operation is allowed. If burst auto refresh is
used in normal operation, burst 2048 auto refresh cycles immediately
after exiting self refresh.
Initialize and load mode register
T0
T1
t
CK
t
CKS
t
CKH
Tn
t
CH
CLK
CKE
t
CMH
t
CL
Tm
Tp+1
Tp+2
Tp+3
t
CMS
PRECHARGE
ALL
COMMAND
DQM
*
NOP
AUTO REFRESH
NOP NOP
AUTO REFRESH
NOP NOP
LOAD MODE
REGISTER
NOP
ACTIVE
t
AS
t
AH
CODE
BANK ROW
ADDRESS
High Z
A10=HIGH
DQ
T=200µs
(min)
t
RP
t
RCAR
t
MRD
Power up:
V
DD
and
CLK stable.
Precharge
all banks.
(8 AUTO REFRESH
CYCLES)
AUTO REFRESH
Program Mode Register
†ƒ
* DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
† The Mode Register may be loaded prior to the auto refresh cycles if desired.
ƒ Outputs are guaranteed High-Z after command is issued.
5/21/01; v.1.1
Alliance Semiconductor
P. 12 of 29
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
