Stratix Device Family Data Sheet
Stratix Device Handbook, Volume 1
Chapter
2
Date/Version
July 2005 v3.2
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Changes Made
Added
section.
Updated
section.
Format changes.
Updated fast regional clock networks description on
Deleted the word preliminary from the “specification for the maximum
time to relock is 100 µs” on
Added information about differential SSTL and HSTL outputs in
Updated notes in
Added information about
m
counter to
Updated Note 1 in
Updated description of
Updated
Added references to AN 349 and AN 329 to
updated the table, updated Notes 3 and
4. Notes 4, 5, and 6, are now Notes 5, 6, and 7, respectively.
Updated
Added information about PCI Compliance to
updated the table and deleted Note 1.
Updated reference to device pin-outs now being available on the web
on
Added Notes 4 and 5 to
Updated Note 3 in
Updated Note 5 in
Added note 3 to rows 11 and 12 in
Deleted “Stratix and Stratix GX Device PLL Availability” table.
Added I/O standards row in
that support max and min
strength.
Row
clk [1,3,8,10]
was removed from
Added checkmarks in Enhanced column for LVPECL, 3.3-V PCML,
LVDS, and HyperTransport technology rows in
Removed the Left and Right I/O Banks row in
Changed
RCLK
values in
and
External RAM Interfacing section replaced.
Added 672-pin BGA package information in
Removed support for series and parallel on-chip termination.
Termination Technology renamed differential on-chip termination.
Updated the number of channels per PLL in Tables 2-38 through 2-
42.
Updated
and
Updated DDR I information.
Updated
Added
and
2–72.
Updated
and
Updated the Lock Detect section.
September 2004, v3.1
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April 2004, v3.0
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November 2003, v2.2
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October 2003, v2.1
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Section I–2
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
