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EP1S40B1508C6ES 参数 Datasheet PDF下载

EP1S40B1508C6ES图片预览
型号: EP1S40B1508C6ES
PDF下载: 下载PDF文件 查看货源
内容描述: Stratix器件系列数据手册 [Stratix Device Family Data Sheet]
分类和应用:
文件页数/大小: 290 页 / 3583 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix Architecture  
Table 2–26. External RAM Support in EP1S60 & EP1S80 Devices  
Maximum Clock Rate (MHz)  
-5 Speed Grade -6 Speed Grade -7 Speed Grade  
DDR Memory Type  
I/O Standard  
DDR SDRAM (1), (2)  
SSTL-2  
167  
150  
133  
167  
200  
167  
133  
133  
167  
200  
133  
133  
133  
133  
167  
DDR SDRAM - side banks (2), (3) SSTL-2  
QDR SRAM (4)  
QDRII SRAM (4)  
ZBT SRAM (5)  
1.5-V HSTL  
1.5-V HSTL  
LVTTL  
Notes to Table 2–26:  
(1) These maximum clock rates apply if the Stratix device uses DQS phase-shift circuitry to interface with DDR  
SDRAM. DQS phase-shift circuitry is only available in the top and bottom I/O banks (I/O banks 3, 4, 7, and 8).  
(2) For more information on DDR SDRAM, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices.  
(3) DDR SDRAM is supported on the Stratix device side I/O banks (I/O banks 1, 2, 5, and 6) without dedicated DQS  
phase-shift circuitry. The read DQS signal is ignored in this mode. Numbers are preliminary.  
(4) For more information on QDR or QDRII SRAM, see AN 349: QDR SRAM Controller Reference Design for Stratix &  
Stratix GX Devices.  
(5) For more information on ZBT SRAM, see AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX  
Devices.  
In addition to six I/O registers and one input latch in the IOE for  
interfacing to these high-speed memory interfaces, Stratix devices also  
have dedicated circuitry for interfacing with DDR SDRAM. In every  
Stratix device, the I/O banks at the top (I/O banks 3 and 4) and bottom  
(I/O banks 7 and 8) of the device support DDR SDRAM up to 200 MHz.  
These pins support DQS signals with DQ bus modes of ×8, ×16, or ×32.  
Table 2–27 shows the number of DQ and DQS buses that are supported  
per device.  
Table 2–27. DQS & DQ Bus Mode Support (Part 1 of 2) Note (1)  
Number of ×8  
Groups  
Number of ×16  
Groups  
Number of ×32  
Groups  
Device  
Package  
EP1S10  
672-pin BGA  
12 (2)  
0
0
672-pin FineLine BGA  
484-pin FineLine BGA  
780-pin FineLine BGA  
16 (3)  
0
4
EP1S20  
484-pin FineLine BGA  
18(4)  
16(3)  
7 (5)  
7 (5)  
4
4
672-pin BGA  
672-pin FineLine BGA  
780-pin FineLine BGA  
20  
7 (5)  
4
Altera Corporation  
July 2005  
2–117  
Stratix Device Handbook, Volume 1