I/O Structure
Tables 2–25 and 2–26 show the performance specification for DDR
SDRAM, RLDRAM II, QDR SRAM, QDRII SRAM, and ZBT SRAM
interfaces in EP1S10 through EP1S40 devices and in EP1S60 and EP1S80
devices. The DDR SDRAM and QDR SRAM numbers in Table 2–25 have
been verified with hardware characterization with third-party DDR
SDRAM and QDR SRAM devices over temperature and voltage
extremes.
Table 2–25. External RAM Support in EP1S10 through EP1S40 Devices
Maximum Clock Rate (MHz)
-5 Speed
Grade
I/O
Standard
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
DDR Memory Type
Wire-
Bond
Flip-
Chip
Wire-
Bond
Flip-
Chip
Wire-
Bond
Flip-Chip Flip-Chip
DDR SDRAM (1), (2) SSTL-2
200
150
167
133
133
110
133
133
100
100
100
100
100
100
DDR SDRAM - side
SSTL-2
banks (2), (3), (4)
RLDRAM II (4)
QDR SRAM (6)
QDRII SRAM (6)
ZBT SRAM (7)
1.8-V HSTL
1.5-V HSTL
1.5-V HSTL
LVTTL
200
167
200
200
(5)
(5)
(5)
(5)
(5)
(5)
167
167
200
133
133
200
133
133
167
100
100
167
100
100
133
100
100
133
Notes to Table 2–25:
(1) These maximum clock rates apply if the Stratix device uses DQS phase-shift circuitry to interface with DDR
SDRAM. DQS phase-shift circuitry is only available in the top and bottom I/O banks (I/O banks 3, 4, 7, and 8).
(2) For more information on DDR SDRAM, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices.
(3) DDR SDRAM is supported on the Stratix device side I/O banks (I/O banks 1, 2, 5, and 6) without dedicated DQS
phase-shift circuitry. The read DQS signal is ignored in this mode.
(4) These performance specifications are preliminary.
(5) This device does not support RLDRAM II.
(6) For more information on QDR or QDRII SRAM, see AN 349: QDR SRAM Controller Reference Design for Stratix &
Stratix GX Devices.
(7) For more information on ZBT SRAM, see AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX
Devices.
2–116
Altera Corporation
July 2005
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
